1 2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
3 * micromips.igen (process_isa_mode): Fix left shift of negative
6 2015-11-17 Mike Frysinger <vapier@gentoo.org>
8 * sim-main.h (WITH_MODULO_MEMORY): Delete.
10 2015-11-15 Mike Frysinger <vapier@gentoo.org>
12 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
14 2015-11-14 Mike Frysinger <vapier@gentoo.org>
16 * interp.c (sim_close): Rename to ...
17 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
19 * sim-main.h (mips_sim_close): Declare.
20 (SIM_CLOSE_HOOK): Define.
22 2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
23 Ali Lown <ali.lown@imgtec.com>
25 * Makefile.in (tmp-micromips): New rule.
26 (tmp-mach-multi): Add support for micromips.
27 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
28 that works for both mips64 and micromips64.
29 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
31 Add build support for micromips.
32 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
33 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
34 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
35 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
36 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
37 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
38 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
39 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
40 Refactored instruction code to use these functions.
41 * dsp2.igen: Refactored instruction code to use the new functions.
42 * interp.c (decode_coproc): Refactored to work with any instruction
44 (isa_mode): New variable
45 (RSVD_INSTRUCTION): Changed to 0x00000039.
46 * m16.igen (BREAK16): Refactored instruction to use do_break16.
47 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
48 * micromips.dc: New file.
49 * micromips.igen: New file.
50 * micromips16.dc: New file.
51 * micromipsdsp.igen: New file.
52 * micromipsrun.c: New file.
53 * mips.igen (do_swc1): Changed to work with any instruction encoding.
54 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
55 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
56 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
57 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
58 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
59 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
60 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
61 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
62 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
63 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
64 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
65 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
66 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
67 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
68 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
69 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
70 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
71 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
73 Refactored instruction code to use these functions.
74 (RSVD): Changed to use new reserved instruction.
75 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
76 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
77 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
78 do_store_double): Added micromips32 and micromips64 models.
79 Added include for micromips.igen and micromipsdsp.igen
80 Add micromips32 and micromips64 models.
81 (DecodeCoproc): Updated to use new macro definition.
82 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
83 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
84 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
85 Refactored instruction code to use these functions.
86 * sim-main.h (CP0_operation): New enum.
87 (DecodeCoproc): Updated macro.
88 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
89 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
90 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
91 ISA_MODE_MICROMIPS): New defines.
92 (sim_state): Add isa_mode field.
94 2015-06-23 Mike Frysinger <vapier@gentoo.org>
96 * configure: Regenerate.
98 2015-06-12 Mike Frysinger <vapier@gentoo.org>
100 * configure.ac: Change configure.in to configure.ac.
101 * configure: Regenerate.
103 2015-06-12 Mike Frysinger <vapier@gentoo.org>
105 * configure: Regenerate.
107 2015-06-12 Mike Frysinger <vapier@gentoo.org>
109 * interp.c [TRACE]: Delete.
110 (TRACE): Change to WITH_TRACE_ANY_P.
111 [!WITH_TRACE_ANY_P] (open_trace): Define.
112 (mips_option_handler, open_trace, sim_close, dotrace):
113 Change defined(TRACE) to WITH_TRACE_ANY_P.
114 (sim_open): Delete TRACE ifdef check.
115 * sim-main.c (load_memory): Delete TRACE ifdef check.
116 (store_memory): Likewise.
117 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
118 [!WITH_TRACE_ANY_P] (dotrace): Define.
120 2015-04-18 Mike Frysinger <vapier@gentoo.org>
122 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
125 2015-04-18 Mike Frysinger <vapier@gentoo.org>
127 * sim-main.h (SIM_CPU): Delete.
129 2015-04-18 Mike Frysinger <vapier@gentoo.org>
131 * sim-main.h (sim_cia): Delete.
133 2015-04-17 Mike Frysinger <vapier@gentoo.org>
135 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
137 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
138 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
139 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
140 CIA_SET to CPU_PC_SET.
141 * sim-main.h (CIA_GET, CIA_SET): Delete.
143 2015-04-15 Mike Frysinger <vapier@gentoo.org>
145 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
146 * sim-main.h (STATE_CPU): Delete.
148 2015-04-13 Mike Frysinger <vapier@gentoo.org>
150 * configure: Regenerate.
152 2015-04-13 Mike Frysinger <vapier@gentoo.org>
154 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
155 * interp.c (mips_pc_get, mips_pc_set): New functions.
156 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
157 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
158 (sim_pc_get): Delete.
159 * sim-main.h (SIM_CPU): Define.
160 (struct sim_state): Change cpu to an array of pointers.
163 2015-04-13 Mike Frysinger <vapier@gentoo.org>
165 * interp.c (mips_option_handler, open_trace, sim_close,
166 sim_write, sim_read, sim_store_register, sim_fetch_register,
167 sim_create_inferior, pr_addr, pr_uword64): Convert old style
169 (sim_open): Convert old style prototype. Change casts with
170 sim_write to unsigned char *.
171 (fetch_str): Change null to unsigned char, and change cast to
173 (sim_monitor): Change c & ch to unsigned char. Change cast to
176 2015-04-12 Mike Frysinger <vapier@gentoo.org>
178 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
180 2015-04-06 Mike Frysinger <vapier@gentoo.org>
182 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
184 2015-04-01 Mike Frysinger <vapier@gentoo.org>
186 * tconfig.h (SIM_HAVE_PROFILE): Delete.
188 2015-03-31 Mike Frysinger <vapier@gentoo.org>
190 * config.in, configure: Regenerate.
192 2015-03-24 Mike Frysinger <vapier@gentoo.org>
194 * interp.c (sim_pc_get): New function.
196 2015-03-24 Mike Frysinger <vapier@gentoo.org>
198 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
199 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
201 2015-03-24 Mike Frysinger <vapier@gentoo.org>
203 * configure: Regenerate.
205 2015-03-23 Mike Frysinger <vapier@gentoo.org>
207 * configure: Regenerate.
209 2015-03-23 Mike Frysinger <vapier@gentoo.org>
211 * configure: Regenerate.
212 * configure.ac (mips_extra_objs): Delete.
213 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
214 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
216 2015-03-23 Mike Frysinger <vapier@gentoo.org>
218 * configure: Regenerate.
219 * configure.ac: Delete sim_hw checks for dv-sockser.
221 2015-03-16 Mike Frysinger <vapier@gentoo.org>
223 * config.in, configure: Regenerate.
224 * tconfig.in: Rename file ...
225 * tconfig.h: ... here.
227 2015-03-15 Mike Frysinger <vapier@gentoo.org>
229 * tconfig.in: Delete includes.
230 [HAVE_DV_SOCKSER]: Delete.
232 2015-03-14 Mike Frysinger <vapier@gentoo.org>
234 * Makefile.in (SIM_RUN_OBJS): Delete.
236 2015-03-14 Mike Frysinger <vapier@gentoo.org>
238 * configure.ac (AC_CHECK_HEADERS): Delete.
239 * aclocal.m4, configure: Regenerate.
241 2014-08-19 Alan Modra <amodra@gmail.com>
243 * configure: Regenerate.
245 2014-08-15 Roland McGrath <mcgrathr@google.com>
247 * configure: Regenerate.
248 * config.in: Regenerate.
250 2014-03-04 Mike Frysinger <vapier@gentoo.org>
252 * configure: Regenerate.
254 2013-09-23 Alan Modra <amodra@gmail.com>
256 * configure: Regenerate.
258 2013-06-03 Mike Frysinger <vapier@gentoo.org>
260 * aclocal.m4, configure: Regenerate.
262 2013-05-10 Freddie Chopin <freddie_chopin@op.pl>
264 * configure: Rebuild.
266 2013-03-26 Mike Frysinger <vapier@gentoo.org>
268 * configure: Regenerate.
270 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
272 * configure.ac: Address use of dv-sockser.o.
273 * tconfig.in: Conditionalize use of dv_sockser_install.
274 * configure: Regenerated.
275 * config.in: Regenerated.
277 2012-10-04 Chao-ying Fu <fu@mips.com>
278 Steve Ellcey <sellcey@mips.com>
280 * mips/mips3264r2.igen (rdhwr): New.
282 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
284 * configure.ac: Always link against dv-sockser.o.
285 * configure: Regenerate.
287 2012-06-15 Joel Brobecker <brobecker@adacore.com>
289 * config.in, configure: Regenerate.
291 2012-05-18 Nick Clifton <nickc@redhat.com>
294 * interp.c: Include config.h before system header files.
296 2012-03-24 Mike Frysinger <vapier@gentoo.org>
298 * aclocal.m4, config.in, configure: Regenerate.
300 2011-12-03 Mike Frysinger <vapier@gentoo.org>
302 * aclocal.m4: New file.
303 * configure: Regenerate.
305 2011-10-19 Mike Frysinger <vapier@gentoo.org>
307 * configure: Regenerate after common/acinclude.m4 update.
309 2011-10-17 Mike Frysinger <vapier@gentoo.org>
311 * configure.ac: Change include to common/acinclude.m4.
313 2011-10-17 Mike Frysinger <vapier@gentoo.org>
315 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
316 call. Replace common.m4 include with SIM_AC_COMMON.
317 * configure: Regenerate.
319 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
321 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
323 (tmp-mach-multi): Exit early when igen fails.
325 2011-07-05 Mike Frysinger <vapier@gentoo.org>
327 * interp.c (sim_do_command): Delete.
329 2011-02-14 Mike Frysinger <vapier@gentoo.org>
331 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
332 (tx3904sio_fifo_reset): Likewise.
333 * interp.c (sim_monitor): Likewise.
335 2010-04-14 Mike Frysinger <vapier@gentoo.org>
337 * interp.c (sim_write): Add const to buffer arg.
339 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
341 * interp.c: Don't include sysdep.h
343 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
345 * configure: Regenerate.
347 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
349 * config.in: Regenerate.
350 * configure: Likewise.
352 * configure: Regenerate.
354 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
356 * configure: Regenerate to track ../common/common.m4 changes.
359 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
360 Daniel Jacobowitz <dan@codesourcery.com>
361 Joseph Myers <joseph@codesourcery.com>
363 * configure: Regenerate.
365 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
367 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
368 that unconditionally allows fmt_ps.
369 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
370 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
371 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
372 filter from 64,f to 32,f.
373 (PREFX): Change filter from 64 to 32.
374 (LDXC1, LUXC1): Provide separate mips32r2 implementations
375 that use do_load_double instead of do_load. Make both LUXC1
376 versions unpredictable if SizeFGR () != 64.
377 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
378 instead of do_store. Remove unused variable. Make both SUXC1
379 versions unpredictable if SizeFGR () != 64.
381 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
383 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
384 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
385 shifts for that case.
387 2007-09-04 Nick Clifton <nickc@redhat.com>
389 * interp.c (options enum): Add OPTION_INFO_MEMORY.
390 (display_mem_info): New static variable.
391 (mips_option_handler): Handle OPTION_INFO_MEMORY.
392 (mips_options): Add info-memory and memory-info.
393 (sim_open): After processing the command line and board
394 specification, check display_mem_info. If it is set then
395 call the real handler for the --memory-info command line
398 2007-08-24 Joel Brobecker <brobecker@adacore.com>
400 * configure.ac: Change license of multi-run.c to GPL version 3.
401 * configure: Regenerate.
403 2007-06-28 Richard Sandiford <richard@codesourcery.com>
405 * configure.ac, configure: Revert last patch.
407 2007-06-26 Richard Sandiford <richard@codesourcery.com>
409 * configure.ac (sim_mipsisa3264_configs): New variable.
410 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
411 every configuration support all four targets, using the triplet to
412 determine the default.
413 * configure: Regenerate.
415 2007-06-25 Richard Sandiford <richard@codesourcery.com>
417 * Makefile.in (m16run.o): New rule.
419 2007-05-15 Thiemo Seufer <ths@mips.com>
421 * mips3264r2.igen (DSHD): Fix compile warning.
423 2007-05-14 Thiemo Seufer <ths@mips.com>
425 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
426 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
427 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
428 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
431 2007-03-01 Thiemo Seufer <ths@mips.com>
433 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
436 2007-02-20 Thiemo Seufer <ths@mips.com>
438 * dsp.igen: Update copyright notice.
439 * dsp2.igen: Fix copyright notice.
441 2007-02-20 Thiemo Seufer <ths@mips.com>
442 Chao-Ying Fu <fu@mips.com>
444 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
445 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
446 Add dsp2 to sim_igen_machine.
447 * configure: Regenerate.
448 * dsp.igen (do_ph_op): Add MUL support when op = 2.
449 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
450 (mulq_rs.ph): Use do_ph_mulq.
451 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
452 * mips.igen: Add dsp2 model and include dsp2.igen.
453 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
454 for *mips32r2, *mips64r2, *dsp.
455 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
456 for *mips32r2, *mips64r2, *dsp2.
457 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
459 2007-02-19 Thiemo Seufer <ths@mips.com>
460 Nigel Stephens <nigel@mips.com>
462 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
463 jumps with hazard barrier.
465 2007-02-19 Thiemo Seufer <ths@mips.com>
466 Nigel Stephens <nigel@mips.com>
468 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
469 after each call to sim_io_write.
471 2007-02-19 Thiemo Seufer <ths@mips.com>
472 Nigel Stephens <nigel@mips.com>
474 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
475 supported by this simulator.
476 (decode_coproc): Recognise additional CP0 Config registers
479 2007-02-19 Thiemo Seufer <ths@mips.com>
480 Nigel Stephens <nigel@mips.com>
481 David Ung <davidu@mips.com>
483 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
484 uninterpreted formats. If fmt is one of the uninterpreted types
485 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
486 fmt_word, and fmt_uninterpreted_64 like fmt_long.
487 (store_fpr): When writing an invalid odd register, set the
488 matching even register to fmt_unknown, not the following register.
489 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
490 the the memory window at offset 0 set by --memory-size command
492 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
494 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
496 (sim_monitor): When returning the memory size to the MIPS
497 application, use the value in STATE_MEM_SIZE, not an arbitrary
499 (cop_lw): Don' mess around with FPR_STATE, just pass
500 fmt_uninterpreted_32 to StoreFPR.
502 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
504 * mips.igen (not_word_value): Single version for mips32, mips64
507 2007-02-19 Thiemo Seufer <ths@mips.com>
508 Nigel Stephens <nigel@mips.com>
510 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
513 2007-02-17 Thiemo Seufer <ths@mips.com>
515 * configure.ac (mips*-sde-elf*): Move in front of generic machine
517 * configure: Regenerate.
519 2007-02-17 Thiemo Seufer <ths@mips.com>
521 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
522 Add mdmx to sim_igen_machine.
523 (mipsisa64*-*-*): Likewise. Remove dsp.
524 (mipsisa32*-*-*): Remove dsp.
525 * configure: Regenerate.
527 2007-02-13 Thiemo Seufer <ths@mips.com>
529 * configure.ac: Add mips*-sde-elf* target.
530 * configure: Regenerate.
532 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
534 * acconfig.h: Remove.
535 * config.in, configure: Regenerate.
537 2006-11-07 Thiemo Seufer <ths@mips.com>
539 * dsp.igen (do_w_op): Fix compiler warning.
541 2006-08-29 Thiemo Seufer <ths@mips.com>
542 David Ung <davidu@mips.com>
544 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
546 * configure: Regenerate.
547 * mips.igen (model): Add smartmips.
548 (MADDU): Increment ACX if carry.
549 (do_mult): Clear ACX.
550 (ROR,RORV): Add smartmips.
551 (include): Include smartmips.igen.
552 * sim-main.h (ACX): Set to REGISTERS[89].
553 * smartmips.igen: New file.
555 2006-08-29 Thiemo Seufer <ths@mips.com>
556 David Ung <davidu@mips.com>
558 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
559 mips3264r2.igen. Add missing dependency rules.
560 * m16e.igen: Support for mips16e save/restore instructions.
562 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
564 * configure: Regenerated.
566 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
568 * configure: Regenerated.
570 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
572 * configure: Regenerated.
574 2006-05-15 Chao-ying Fu <fu@mips.com>
576 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
578 2006-04-18 Nick Clifton <nickc@redhat.com>
580 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
583 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
585 * configure: Regenerate.
587 2005-12-14 Chao-ying Fu <fu@mips.com>
589 * Makefile.in (SIM_OBJS): Add dsp.o.
590 (dsp.o): New dependency.
591 (IGEN_INCLUDE): Add dsp.igen.
592 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
593 mipsisa64*-*-*): Add dsp to sim_igen_machine.
594 * configure: Regenerate.
595 * mips.igen: Add dsp model and include dsp.igen.
596 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
597 because these instructions are extended in DSP ASE.
598 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
599 adding 6 DSP accumulator registers and 1 DSP control register.
600 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
601 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
602 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
603 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
604 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
605 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
606 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
607 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
608 DSPCR_CCOND_SMASK): New define.
609 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
610 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
612 2005-07-08 Ian Lance Taylor <ian@airs.com>
614 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
616 2005-06-16 David Ung <davidu@mips.com>
617 Nigel Stephens <nigel@mips.com>
619 * mips.igen: New mips16e model and include m16e.igen.
620 (check_u64): Add mips16e tag.
621 * m16e.igen: New file for MIPS16e instructions.
622 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
623 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
625 * configure: Regenerate.
627 2005-05-26 David Ung <davidu@mips.com>
629 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
630 tags to all instructions which are applicable to the new ISAs.
631 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
633 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
635 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
637 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
638 * configure: Regenerate.
640 2005-03-23 Mark Kettenis <kettenis@gnu.org>
642 * configure: Regenerate.
644 2005-01-14 Andrew Cagney <cagney@gnu.org>
646 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
647 explicit call to AC_CONFIG_HEADER.
648 * configure: Regenerate.
650 2005-01-12 Andrew Cagney <cagney@gnu.org>
652 * configure.ac: Update to use ../common/common.m4.
653 * configure: Re-generate.
655 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
657 * configure: Regenerated to track ../common/aclocal.m4 changes.
659 2005-01-07 Andrew Cagney <cagney@gnu.org>
661 * configure.ac: Rename configure.in, require autoconf 2.59.
662 * configure: Re-generate.
664 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
666 * configure: Regenerate for ../common/aclocal.m4 update.
668 2004-09-24 Monika Chaddha <monika@acmet.com>
670 Committed by Andrew Cagney.
671 * m16.igen (CMP, CMPI): Fix assembler.
673 2004-08-18 Chris Demetriou <cgd@broadcom.com>
675 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
676 * configure: Regenerate.
678 2004-06-25 Chris Demetriou <cgd@broadcom.com>
680 * configure.in (sim_m16_machine): Include mipsIII.
681 * configure: Regenerate.
683 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
685 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
687 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
689 2004-04-10 Chris Demetriou <cgd@broadcom.com>
691 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
693 2004-04-09 Chris Demetriou <cgd@broadcom.com>
695 * mips.igen (check_fmt): Remove.
696 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
697 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
698 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
699 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
700 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
701 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
702 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
703 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
704 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
705 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
707 2004-04-09 Chris Demetriou <cgd@broadcom.com>
709 * sb1.igen (check_sbx): New function.
710 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
712 2004-03-29 Chris Demetriou <cgd@broadcom.com>
713 Richard Sandiford <rsandifo@redhat.com>
715 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
716 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
717 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
718 separate implementations for mipsIV and mipsV. Use new macros to
719 determine whether the restrictions apply.
721 2004-01-19 Chris Demetriou <cgd@broadcom.com>
723 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
724 (check_mult_hilo): Improve comments.
725 (check_div_hilo): Likewise. Also, fork off a new version
726 to handle mips32/mips64 (since there are no hazards to check
729 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
731 * mips.igen (do_dmultx): Fix check for negative operands.
733 2003-05-16 Ian Lance Taylor <ian@airs.com>
735 * Makefile.in (SHELL): Make sure this is defined.
736 (various): Use $(SHELL) whenever we invoke move-if-change.
738 2003-05-03 Chris Demetriou <cgd@broadcom.com>
740 * cp1.c: Tweak attribution slightly.
743 * mdmx.igen: Likewise.
744 * mips3d.igen: Likewise.
745 * sb1.igen: Likewise.
747 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
749 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
752 2003-02-27 Andrew Cagney <cagney@redhat.com>
754 * interp.c (sim_open): Rename _bfd to bfd.
755 (sim_create_inferior): Ditto.
757 2003-01-14 Chris Demetriou <cgd@broadcom.com>
759 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
761 2003-01-14 Chris Demetriou <cgd@broadcom.com>
763 * mips.igen (EI, DI): Remove.
765 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
767 * Makefile.in (tmp-run-multi): Fix mips16 filter.
769 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
770 Andrew Cagney <ac131313@redhat.com>
771 Gavin Romig-Koch <gavin@redhat.com>
772 Graydon Hoare <graydon@redhat.com>
773 Aldy Hernandez <aldyh@redhat.com>
774 Dave Brolley <brolley@redhat.com>
775 Chris Demetriou <cgd@broadcom.com>
777 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
778 (sim_mach_default): New variable.
779 (mips64vr-*-*, mips64vrel-*-*): New configurations.
780 Add a new simulator generator, MULTI.
781 * configure: Regenerate.
782 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
783 (multi-run.o): New dependency.
784 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
785 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
786 (tmp-multi): Combine them.
787 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
788 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
789 (distclean-extra): New rule.
790 * sim-main.h: Include bfd.h.
791 (MIPS_MACH): New macro.
792 * mips.igen (vr4120, vr5400, vr5500): New models.
793 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
794 * vr.igen: Replace with new version.
796 2003-01-04 Chris Demetriou <cgd@broadcom.com>
798 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
799 * configure: Regenerate.
801 2002-12-31 Chris Demetriou <cgd@broadcom.com>
803 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
804 * mips.igen: Remove all invocations of check_branch_bug and
807 2002-12-16 Chris Demetriou <cgd@broadcom.com>
809 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
811 2002-07-30 Chris Demetriou <cgd@broadcom.com>
813 * mips.igen (do_load_double, do_store_double): New functions.
814 (LDC1, SDC1): Rename to...
815 (LDC1b, SDC1b): respectively.
816 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
818 2002-07-29 Michael Snyder <msnyder@redhat.com>
820 * cp1.c (fp_recip2): Modify initialization expression so that
821 GCC will recognize it as constant.
823 2002-06-18 Chris Demetriou <cgd@broadcom.com>
825 * mdmx.c (SD_): Delete.
826 (Unpredictable): Re-define, for now, to directly invoke
827 unpredictable_action().
828 (mdmx_acc_op): Fix error in .ob immediate handling.
830 2002-06-18 Andrew Cagney <cagney@redhat.com>
832 * interp.c (sim_firmware_command): Initialize `address'.
834 2002-06-16 Andrew Cagney <ac131313@redhat.com>
836 * configure: Regenerated to track ../common/aclocal.m4 changes.
838 2002-06-14 Chris Demetriou <cgd@broadcom.com>
839 Ed Satterthwaite <ehs@broadcom.com>
841 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
842 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
843 * mips.igen: Include mips3d.igen.
844 (mips3d): New model name for MIPS-3D ASE instructions.
845 (CVT.W.fmt): Don't use this instruction for word (source) format
847 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
848 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
849 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
850 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
851 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
852 (RSquareRoot1, RSquareRoot2): New macros.
853 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
854 (fp_rsqrt2): New functions.
855 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
856 * configure: Regenerate.
858 2002-06-13 Chris Demetriou <cgd@broadcom.com>
859 Ed Satterthwaite <ehs@broadcom.com>
861 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
862 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
863 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
864 (convert): Note that this function is not used for paired-single
866 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
867 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
868 (check_fmt_p): Enable paired-single support.
869 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
870 (PUU.PS): New instructions.
871 (CVT.S.fmt): Don't use this instruction for paired-single format
873 * sim-main.h (FP_formats): New value 'fmt_ps.'
874 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
875 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
877 2002-06-12 Chris Demetriou <cgd@broadcom.com>
879 * mips.igen: Fix formatting of function calls in
882 2002-06-12 Chris Demetriou <cgd@broadcom.com>
884 * mips.igen (MOVN, MOVZ): Trace result.
885 (TNEI): Print "tnei" as the opcode name in traces.
886 (CEIL.W): Add disassembly string for traces.
887 (RSQRT.fmt): Make location of disassembly string consistent
888 with other instructions.
890 2002-06-12 Chris Demetriou <cgd@broadcom.com>
892 * mips.igen (X): Delete unused function.
894 2002-06-08 Andrew Cagney <cagney@redhat.com>
896 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
898 2002-06-07 Chris Demetriou <cgd@broadcom.com>
899 Ed Satterthwaite <ehs@broadcom.com>
901 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
902 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
903 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
904 (fp_nmsub): New prototypes.
905 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
906 (NegMultiplySub): New defines.
907 * mips.igen (RSQRT.fmt): Use RSquareRoot().
908 (MADD.D, MADD.S): Replace with...
909 (MADD.fmt): New instruction.
910 (MSUB.D, MSUB.S): Replace with...
911 (MSUB.fmt): New instruction.
912 (NMADD.D, NMADD.S): Replace with...
913 (NMADD.fmt): New instruction.
914 (NMSUB.D, MSUB.S): Replace with...
915 (NMSUB.fmt): New instruction.
917 2002-06-07 Chris Demetriou <cgd@broadcom.com>
918 Ed Satterthwaite <ehs@broadcom.com>
920 * cp1.c: Fix more comment spelling and formatting.
921 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
922 (denorm_mode): New function.
923 (fpu_unary, fpu_binary): Round results after operation, collect
924 status from rounding operations, and update the FCSR.
925 (convert): Collect status from integer conversions and rounding
926 operations, and update the FCSR. Adjust NaN values that result
927 from conversions. Convert to use sim_io_eprintf rather than
928 fprintf, and remove some debugging code.
929 * cp1.h (fenr_FS): New define.
931 2002-06-07 Chris Demetriou <cgd@broadcom.com>
933 * cp1.c (convert): Remove unusable debugging code, and move MIPS
934 rounding mode to sim FP rounding mode flag conversion code into...
935 (rounding_mode): New function.
937 2002-06-07 Chris Demetriou <cgd@broadcom.com>
939 * cp1.c: Clean up formatting of a few comments.
940 (value_fpr): Reformat switch statement.
942 2002-06-06 Chris Demetriou <cgd@broadcom.com>
943 Ed Satterthwaite <ehs@broadcom.com>
946 * sim-main.h: Include cp1.h.
947 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
948 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
949 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
950 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
951 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
952 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
953 * cp1.c: Don't include sim-fpu.h; already included by
954 sim-main.h. Clean up formatting of some comments.
955 (NaN, Equal, Less): Remove.
956 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
957 (fp_cmp): New functions.
958 * mips.igen (do_c_cond_fmt): Remove.
959 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
960 Compare. Add result tracing.
961 (CxC1): Remove, replace with...
962 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
963 (DMxC1): Remove, replace with...
964 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
965 (MxC1): Remove, replace with...
966 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
968 2002-06-04 Chris Demetriou <cgd@broadcom.com>
970 * sim-main.h (FGRIDX): Remove, replace all uses with...
971 (FGR_BASE): New macro.
972 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
973 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
974 (NR_FGR, FGR): Likewise.
975 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
976 * mips.igen: Likewise.
978 2002-06-04 Chris Demetriou <cgd@broadcom.com>
980 * cp1.c: Add an FSF Copyright notice to this file.
982 2002-06-04 Chris Demetriou <cgd@broadcom.com>
983 Ed Satterthwaite <ehs@broadcom.com>
985 * cp1.c (Infinity): Remove.
986 * sim-main.h (Infinity): Likewise.
988 * cp1.c (fp_unary, fp_binary): New functions.
989 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
990 (fp_sqrt): New functions, implemented in terms of the above.
991 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
992 (Recip, SquareRoot): Remove (replaced by functions above).
993 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
994 (fp_recip, fp_sqrt): New prototypes.
995 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
996 (Recip, SquareRoot): Replace prototypes with #defines which
997 invoke the functions above.
999 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1001 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1002 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1003 file, remove PARAMS from prototypes.
1004 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1005 simulator state arguments.
1006 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1007 pass simulator state arguments.
1008 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1009 (store_fpr, convert): Remove 'sd' argument.
1010 (value_fpr): Likewise. Convert to use 'SD' instead.
1012 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1014 * cp1.c (Min, Max): Remove #if 0'd functions.
1015 * sim-main.h (Min, Max): Remove.
1017 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1019 * cp1.c: fix formatting of switch case and default labels.
1020 * interp.c: Likewise.
1021 * sim-main.c: Likewise.
1023 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1025 * cp1.c: Clean up comments which describe FP formats.
1026 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1028 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1029 Ed Satterthwaite <ehs@broadcom.com>
1031 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1032 Broadcom SiByte SB-1 processor configurations.
1033 * configure: Regenerate.
1034 * sb1.igen: New file.
1035 * mips.igen: Include sb1.igen.
1037 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1038 * mdmx.igen: Add "sb1" model to all appropriate functions and
1040 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1041 (ob_func, ob_acc): Reference the above.
1042 (qh_acc): Adjust to keep the same size as ob_acc.
1043 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1044 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1046 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1048 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1050 2002-06-02 Chris Demetriou <cgd@broadcom.com>
1051 Ed Satterthwaite <ehs@broadcom.com>
1053 * mips.igen (mdmx): New (pseudo-)model.
1054 * mdmx.c, mdmx.igen: New files.
1055 * Makefile.in (SIM_OBJS): Add mdmx.o.
1056 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1058 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1059 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1060 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1061 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1062 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1063 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1064 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1065 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1066 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1067 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1068 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1069 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1070 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1071 (qh_fmtsel): New macros.
1072 (_sim_cpu): New member "acc".
1073 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1074 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1076 2002-05-01 Chris Demetriou <cgd@broadcom.com>
1078 * interp.c: Use 'deprecated' rather than 'depreciated.'
1079 * sim-main.h: Likewise.
1081 2002-05-01 Chris Demetriou <cgd@broadcom.com>
1083 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1084 which wouldn't compile anyway.
1085 * sim-main.h (unpredictable_action): New function prototype.
1086 (Unpredictable): Define to call igen function unpredictable().
1087 (NotWordValue): New macro to call igen function not_word_value().
1088 (UndefinedResult): Remove.
1089 * interp.c (undefined_result): Remove.
1090 (unpredictable_action): New function.
1091 * mips.igen (not_word_value, unpredictable): New functions.
1092 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1093 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1094 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1095 NotWordValue() to check for unpredictable inputs, then
1096 Unpredictable() to handle them.
1098 2002-02-24 Chris Demetriou <cgd@broadcom.com>
1100 * mips.igen: Fix formatting of calls to Unpredictable().
1102 2002-04-20 Andrew Cagney <ac131313@redhat.com>
1104 * interp.c (sim_open): Revert previous change.
1106 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
1108 * interp.c (sim_open): Disable chunk of code that wrote code in
1109 vector table entries.
1111 2002-03-19 Chris Demetriou <cgd@broadcom.com>
1113 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1114 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1117 2002-03-19 Chris Demetriou <cgd@broadcom.com>
1119 * cp1.c: Fix many formatting issues.
1121 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1123 * cp1.c (fpu_format_name): New function to replace...
1124 (DOFMT): This. Delete, and update all callers.
1125 (fpu_rounding_mode_name): New function to replace...
1126 (RMMODE): This. Delete, and update all callers.
1128 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1130 * interp.c: Move FPU support routines from here to...
1131 * cp1.c: Here. New file.
1132 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1133 (cp1.o): New target.
1135 2002-03-12 Chris Demetriou <cgd@broadcom.com>
1137 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1138 * mips.igen (mips32, mips64): New models, add to all instructions
1139 and functions as appropriate.
1140 (loadstore_ea, check_u64): New variant for model mips64.
1141 (check_fmt_p): New variant for models mipsV and mips64, remove
1142 mipsV model marking fro other variant.
1145 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1146 for mips32 and mips64.
1147 (DCLO, DCLZ): New instructions for mips64.
1149 2002-03-07 Chris Demetriou <cgd@broadcom.com>
1151 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1152 immediate or code as a hex value with the "%#lx" format.
1153 (ANDI): Likewise, and fix printed instruction name.
1155 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1157 * sim-main.h (UndefinedResult, Unpredictable): New macros
1158 which currently do nothing.
1160 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1162 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1163 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1164 (status_CU3): New definitions.
1166 * sim-main.h (ExceptionCause): Add new values for MIPS32
1167 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1168 for DebugBreakPoint and NMIReset to note their status in
1170 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1171 (SignalExceptionCacheErr): New exception macros.
1173 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1175 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1176 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1178 (SignalExceptionCoProcessorUnusable): Take as argument the
1179 unusable coprocessor number.
1181 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1183 * mips.igen: Fix formatting of all SignalException calls.
1185 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1187 * sim-main.h (SIGNEXTEND): Remove.
1189 2002-03-04 Chris Demetriou <cgd@broadcom.com>
1191 * mips.igen: Remove gencode comment from top of file, fix
1192 spelling in another comment.
1194 2002-03-04 Chris Demetriou <cgd@broadcom.com>
1196 * mips.igen (check_fmt, check_fmt_p): New functions to check
1197 whether specific floating point formats are usable.
1198 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1199 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1200 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1201 Use the new functions.
1202 (do_c_cond_fmt): Remove format checks...
1203 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1205 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1207 * mips.igen: Fix formatting of check_fpu calls.
1209 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1211 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1213 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1215 * mips.igen: Remove whitespace at end of lines.
1217 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1219 * mips.igen (loadstore_ea): New function to do effective
1220 address calculations.
1221 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1222 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1223 CACHE): Use loadstore_ea to do effective address computations.
1225 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1227 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1228 * mips.igen (LL, CxC1, MxC1): Likewise.
1230 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1232 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1233 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1234 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1235 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1236 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1237 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1238 Don't split opcode fields by hand, use the opcode field values
1241 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1243 * mips.igen (do_divu): Fix spacing.
1245 * mips.igen (do_dsllv): Move to be right before DSLLV,
1246 to match the rest of the do_<shift> functions.
1248 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1250 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1251 DSRL32, do_dsrlv): Trace inputs and results.
1253 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1255 * mips.igen (CACHE): Provide instruction-printing string.
1257 * interp.c (signal_exception): Comment tokens after #endif.
1259 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1261 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1262 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1263 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1264 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1265 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1266 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1267 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1268 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1270 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1272 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1273 instruction-printing string.
1274 (LWU): Use '64' as the filter flag.
1276 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1278 * mips.igen (SDXC1): Fix instruction-printing string.
1280 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1282 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1283 filter flags "32,f".
1285 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1287 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1290 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1292 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1293 add a comma) so that it more closely match the MIPS ISA
1294 documentation opcode partitioning.
1295 (PREF): Put useful names on opcode fields, and include
1296 instruction-printing string.
1298 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1300 * mips.igen (check_u64): New function which in the future will
1301 check whether 64-bit instructions are usable and signal an
1302 exception if not. Currently a no-op.
1303 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1304 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1305 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1306 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1308 * mips.igen (check_fpu): New function which in the future will
1309 check whether FPU instructions are usable and signal an exception
1310 if not. Currently a no-op.
1311 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1312 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1313 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1314 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1315 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1316 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1317 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1318 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1320 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1322 * mips.igen (do_load_left, do_load_right): Move to be immediately
1324 (do_store_left, do_store_right): Move to be immediately following
1327 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1329 * mips.igen (mipsV): New model name. Also, add it to
1330 all instructions and functions where it is appropriate.
1332 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1334 * mips.igen: For all functions and instructions, list model
1335 names that support that instruction one per line.
1337 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1339 * mips.igen: Add some additional comments about supported
1340 models, and about which instructions go where.
1341 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1342 order as is used in the rest of the file.
1344 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1346 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1347 indicating that ALU32_END or ALU64_END are there to check
1349 (DADD): Likewise, but also remove previous comment about
1352 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1354 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1355 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1356 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1357 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1358 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1359 fields (i.e., add and move commas) so that they more closely
1360 match the MIPS ISA documentation opcode partitioning.
1362 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1364 * mips.igen (ADDI): Print immediate value.
1365 (BREAK): Print code.
1366 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1367 (SLL): Print "nop" specially, and don't run the code
1368 that does the shift for the "nop" case.
1370 2001-11-17 Fred Fish <fnf@redhat.com>
1372 * sim-main.h (float_operation): Move enum declaration outside
1373 of _sim_cpu struct declaration.
1375 2001-04-12 Jim Blandy <jimb@redhat.com>
1377 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1378 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1380 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1381 PENDING_FILL, and you can get the intended effect gracefully by
1382 calling PENDING_SCHED directly.
1384 2001-02-23 Ben Elliston <bje@redhat.com>
1386 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1387 already defined elsewhere.
1389 2001-02-19 Ben Elliston <bje@redhat.com>
1391 * sim-main.h (sim_monitor): Return an int.
1392 * interp.c (sim_monitor): Add return values.
1393 (signal_exception): Handle error conditions from sim_monitor.
1395 2001-02-08 Ben Elliston <bje@redhat.com>
1397 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1398 (store_memory): Likewise, pass cia to sim_core_write*.
1400 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1402 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1403 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1405 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1407 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1408 * Makefile.in: Don't delete *.igen when cleaning directory.
1410 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1412 * m16.igen (break): Call SignalException not sim_engine_halt.
1414 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1416 From Jason Eckhardt:
1417 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1419 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1421 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1423 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1425 * mips.igen (do_dmultx): Fix typo.
1427 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1429 * configure: Regenerated to track ../common/aclocal.m4 changes.
1431 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1433 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1435 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1437 * sim-main.h (GPR_CLEAR): Define macro.
1439 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1441 * interp.c (decode_coproc): Output long using %lx and not %s.
1443 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1445 * interp.c (sim_open): Sort & extend dummy memory regions for
1446 --board=jmr3904 for eCos.
1448 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1450 * configure: Regenerated.
1452 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1454 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1455 calls, conditional on the simulator being in verbose mode.
1457 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1459 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1460 cache don't get ReservedInstruction traps.
1462 1999-11-29 Mark Salter <msalter@cygnus.com>
1464 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1465 to clear status bits in sdisr register. This is how the hardware works.
1467 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1468 being used by cygmon.
1470 1999-11-11 Andrew Haley <aph@cygnus.com>
1472 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1475 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1477 * mips.igen (MULT): Correct previous mis-applied patch.
1479 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1481 * mips.igen (delayslot32): Handle sequence like
1482 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1483 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1484 (MULT): Actually pass the third register...
1486 1999-09-03 Mark Salter <msalter@cygnus.com>
1488 * interp.c (sim_open): Added more memory aliases for additional
1489 hardware being touched by cygmon on jmr3904 board.
1491 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1493 * configure: Regenerated to track ../common/aclocal.m4 changes.
1495 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1497 * interp.c (sim_store_register): Handle case where client - GDB -
1498 specifies that a 4 byte register is 8 bytes in size.
1499 (sim_fetch_register): Ditto.
1501 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1503 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1504 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1505 (idt_monitor_base): Base address for IDT monitor traps.
1506 (pmon_monitor_base): Ditto for PMON.
1507 (lsipmon_monitor_base): Ditto for LSI PMON.
1508 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1509 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1510 (sim_firmware_command): New function.
1511 (mips_option_handler): Call it for OPTION_FIRMWARE.
1512 (sim_open): Allocate memory for idt_monitor region. If "--board"
1513 option was given, add no monitor by default. Add BREAK hooks only if
1514 monitors are also there.
1516 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1518 * interp.c (sim_monitor): Flush output before reading input.
1520 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1522 * tconfig.in (SIM_HANDLES_LMA): Always define.
1524 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1526 From Mark Salter <msalter@cygnus.com>:
1527 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1528 (sim_open): Add setup for BSP board.
1530 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1532 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1533 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1534 them as unimplemented.
1536 1999-05-08 Felix Lee <flee@cygnus.com>
1538 * configure: Regenerated to track ../common/aclocal.m4 changes.
1540 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1542 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1544 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1546 * configure.in: Any mips64vr5*-*-* target should have
1547 -DTARGET_ENABLE_FR=1.
1548 (default_endian): Any mips64vr*el-*-* target should default to
1550 * configure: Re-generate.
1552 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1554 * mips.igen (ldl): Extend from _16_, not 32.
1556 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1558 * interp.c (sim_store_register): Force registers written to by GDB
1559 into an un-interpreted state.
1561 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1563 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1564 CPU, start periodic background I/O polls.
1565 (tx3904sio_poll): New function: periodic I/O poller.
1567 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1569 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1571 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1573 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1576 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1578 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1579 (load_word): Call SIM_CORE_SIGNAL hook on error.
1580 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1581 starting. For exception dispatching, pass PC instead of NULL_CIA.
1582 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1583 * sim-main.h (COP0_BADVADDR): Define.
1584 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1585 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1586 (_sim_cpu): Add exc_* fields to store register value snapshots.
1587 * mips.igen (*): Replace memory-related SignalException* calls
1588 with references to SIM_CORE_SIGNAL hook.
1590 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1592 * sim-main.c (*): Minor warning cleanups.
1594 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1596 * m16.igen (DADDIU5): Correct type-o.
1598 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1600 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1603 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1605 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1607 (interp.o): Add dependency on itable.h
1608 (oengine.c, gencode): Delete remaining references.
1609 (BUILT_SRC_FROM_GEN): Clean up.
1611 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1614 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1615 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1616 tmp-run-hack) : New.
1617 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1618 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1619 Drop the "64" qualifier to get the HACK generator working.
1620 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1621 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1622 qualifier to get the hack generator working.
1623 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1624 (DSLL): Use do_dsll.
1625 (DSLLV): Use do_dsllv.
1626 (DSRA): Use do_dsra.
1627 (DSRL): Use do_dsrl.
1628 (DSRLV): Use do_dsrlv.
1629 (BC1): Move *vr4100 to get the HACK generator working.
1630 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1631 get the HACK generator working.
1632 (MACC) Rename to get the HACK generator working.
1633 (DMACC,MACCS,DMACCS): Add the 64.
1635 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1637 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1638 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1640 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1642 * mips/interp.c (DEBUG): Cleanups.
1644 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1646 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1647 (tx3904sio_tickle): fflush after a stdout character output.
1649 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1651 * interp.c (sim_close): Uninstall modules.
1653 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1655 * sim-main.h, interp.c (sim_monitor): Change to global
1658 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1660 * configure.in (vr4100): Only include vr4100 instructions in
1662 * configure: Re-generate.
1663 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1665 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1667 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1668 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1671 * configure.in (sim_default_gen, sim_use_gen): Replace with
1673 (--enable-sim-igen): Delete config option. Always using IGEN.
1674 * configure: Re-generate.
1676 * Makefile.in (gencode): Kill, kill, kill.
1679 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1681 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1682 bit mips16 igen simulator.
1683 * configure: Re-generate.
1685 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1686 as part of vr4100 ISA.
1687 * vr.igen: Mark all instructions as 64 bit only.
1689 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1691 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1694 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1696 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1697 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1698 * configure: Re-generate.
1700 * m16.igen (BREAK): Define breakpoint instruction.
1701 (JALX32): Mark instruction as mips16 and not r3900.
1702 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1704 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1706 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1708 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1709 insn as a debug breakpoint.
1711 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1713 (PENDING_SCHED): Clean up trace statement.
1714 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1715 (PENDING_FILL): Delay write by only one cycle.
1716 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1718 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1720 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1722 (pending_tick): Move incrementing of index to FOR statement.
1723 (pending_tick): Only update PENDING_OUT after a write has occured.
1725 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1727 * configure: Re-generate.
1729 * interp.c (sim_engine_run OLD): Delete explicit call to
1730 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1732 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1734 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1735 interrupt level number to match changed SignalExceptionInterrupt
1738 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1740 * interp.c: #include "itable.h" if WITH_IGEN.
1741 (get_insn_name): New function.
1742 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1743 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1745 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1747 * configure: Rebuilt to inhale new common/aclocal.m4.
1749 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1751 * dv-tx3904sio.c: Include sim-assert.h.
1753 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1755 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1756 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1757 Reorganize target-specific sim-hardware checks.
1758 * configure: rebuilt.
1759 * interp.c (sim_open): For tx39 target boards, set
1760 OPERATING_ENVIRONMENT, add tx3904sio devices.
1761 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1762 ROM executables. Install dv-sockser into sim-modules list.
1764 * dv-tx3904irc.c: Compiler warning clean-up.
1765 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1766 frequent hw-trace messages.
1768 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1770 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1772 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1774 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1776 * vr.igen: New file.
1777 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1778 * mips.igen: Define vr4100 model. Include vr.igen.
1779 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1781 * mips.igen (check_mf_hilo): Correct check.
1783 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1785 * sim-main.h (interrupt_event): Add prototype.
1787 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1788 register_ptr, register_value.
1789 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1791 * sim-main.h (tracefh): Make extern.
1793 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1795 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1796 Reduce unnecessarily high timer event frequency.
1797 * dv-tx3904cpu.c: Ditto for interrupt event.
1799 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1801 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1803 (interrupt_event): Made non-static.
1805 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1806 interchange of configuration values for external vs. internal
1809 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1811 * mips.igen (BREAK): Moved code to here for
1812 simulator-reserved break instructions.
1813 * gencode.c (build_instruction): Ditto.
1814 * interp.c (signal_exception): Code moved from here. Non-
1815 reserved instructions now use exception vector, rather
1817 * sim-main.h: Moved magic constants to here.
1819 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1821 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1822 register upon non-zero interrupt event level, clear upon zero
1824 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1825 by passing zero event value.
1826 (*_io_{read,write}_buffer): Endianness fixes.
1827 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1828 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1830 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1831 serial I/O and timer module at base address 0xFFFF0000.
1833 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1835 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1838 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1840 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1842 * configure: Update.
1844 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1846 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1847 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1848 * configure.in: Include tx3904tmr in hw_device list.
1849 * configure: Rebuilt.
1850 * interp.c (sim_open): Instantiate three timer instances.
1851 Fix address typo of tx3904irc instance.
1853 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1855 * interp.c (signal_exception): SystemCall exception now uses
1856 the exception vector.
1858 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1860 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1863 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1865 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1867 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1869 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1871 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1872 sim-main.h. Declare a struct hw_descriptor instead of struct
1873 hw_device_descriptor.
1875 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1878 right bits and then re-align left hand bytes to correct byte
1879 lanes. Fix incorrect computation in do_store_left when loading
1880 bytes from second word.
1882 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1884 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1885 * interp.c (sim_open): Only create a device tree when HW is
1888 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1889 * interp.c (signal_exception): Ditto.
1891 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1893 * gencode.c: Mark BEGEZALL as LIKELY.
1895 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1897 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1898 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1900 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1902 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1903 modules. Recognize TX39 target with "mips*tx39" pattern.
1904 * configure: Rebuilt.
1905 * sim-main.h (*): Added many macros defining bits in
1906 TX39 control registers.
1907 (SignalInterrupt): Send actual PC instead of NULL.
1908 (SignalNMIReset): New exception type.
1909 * interp.c (board): New variable for future use to identify
1910 a particular board being simulated.
1911 (mips_option_handler,mips_options): Added "--board" option.
1912 (interrupt_event): Send actual PC.
1913 (sim_open): Make memory layout conditional on board setting.
1914 (signal_exception): Initial implementation of hardware interrupt
1915 handling. Accept another break instruction variant for simulator
1917 (decode_coproc): Implement RFE instruction for TX39.
1918 (mips.igen): Decode RFE instruction as such.
1919 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1920 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1921 bbegin to implement memory map.
1922 * dv-tx3904cpu.c: New file.
1923 * dv-tx3904irc.c: New file.
1925 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1927 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1929 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1931 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1932 with calls to check_div_hilo.
1934 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1936 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1937 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1938 Add special r3900 version of do_mult_hilo.
1939 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1940 with calls to check_mult_hilo.
1941 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1942 with calls to check_div_hilo.
1944 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1946 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1947 Document a replacement.
1949 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1951 * interp.c (sim_monitor): Make mon_printf work.
1953 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1955 * sim-main.h (INSN_NAME): New arg `cpu'.
1957 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1959 * configure: Regenerated to track ../common/aclocal.m4 changes.
1961 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1963 * configure: Regenerated to track ../common/aclocal.m4 changes.
1966 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1968 * acconfig.h: New file.
1969 * configure.in: Reverted change of Apr 24; use sinclude again.
1971 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1973 * configure: Regenerated to track ../common/aclocal.m4 changes.
1976 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1978 * configure.in: Don't call sinclude.
1980 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1982 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1984 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1986 * mips.igen (ERET): Implement.
1988 * interp.c (decode_coproc): Return sign-extended EPC.
1990 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1992 * interp.c (signal_exception): Do not ignore Trap.
1993 (signal_exception): On TRAP, restart at exception address.
1994 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1995 (signal_exception): Update.
1996 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1997 so that TRAP instructions are caught.
1999 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2001 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2002 contains HI/LO access history.
2003 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2004 (HIACCESS, LOACCESS): Delete, replace with
2005 (HIHISTORY, LOHISTORY): New macros.
2006 (CHECKHILO): Delete all, moved to mips.igen
2008 * gencode.c (build_instruction): Do not generate checks for
2009 correct HI/LO register usage.
2011 * interp.c (old_engine_run): Delete checks for correct HI/LO
2014 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2015 check_mf_cycles): New functions.
2016 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2017 do_divu, domultx, do_mult, do_multu): Use.
2019 * tx.igen ("madd", "maddu"): Use.
2021 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2023 * mips.igen (DSRAV): Use function do_dsrav.
2024 (SRAV): Use new function do_srav.
2026 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2027 (B): Sign extend 11 bit immediate.
2028 (EXT-B*): Shift 16 bit immediate left by 1.
2029 (ADDIU*): Don't sign extend immediate value.
2031 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2033 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2035 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2038 * mips.igen (delayslot32, nullify_next_insn): New functions.
2039 (m16.igen): Always include.
2040 (do_*): Add more tracing.
2042 * m16.igen (delayslot16): Add NIA argument, could be called by a
2043 32 bit MIPS16 instruction.
2045 * interp.c (ifetch16): Move function from here.
2046 * sim-main.c (ifetch16): To here.
2048 * sim-main.c (ifetch16, ifetch32): Update to match current
2049 implementations of LH, LW.
2050 (signal_exception): Don't print out incorrect hex value of illegal
2053 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2055 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2058 * m16.igen: Implement MIPS16 instructions.
2060 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2061 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2062 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2063 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2064 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2065 bodies of corresponding code from 32 bit insn to these. Also used
2066 by MIPS16 versions of functions.
2068 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2069 (IMEM16): Drop NR argument from macro.
2071 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2073 * Makefile.in (SIM_OBJS): Add sim-main.o.
2075 * sim-main.h (address_translation, load_memory, store_memory,
2076 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2078 (pr_addr, pr_uword64): Declare.
2079 (sim-main.c): Include when H_REVEALS_MODULE_P.
2081 * interp.c (address_translation, load_memory, store_memory,
2082 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2084 * sim-main.c: To here. Fix compilation problems.
2086 * configure.in: Enable inlining.
2087 * configure: Re-config.
2089 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2091 * configure: Regenerated to track ../common/aclocal.m4 changes.
2093 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2095 * mips.igen: Include tx.igen.
2096 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2097 * tx.igen: New file, contains MADD and MADDU.
2099 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2100 the hardwired constant `7'.
2101 (store_memory): Ditto.
2102 (LOADDRMASK): Move definition to sim-main.h.
2104 mips.igen (MTC0): Enable for r3900.
2107 mips.igen (do_load_byte): Delete.
2108 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2109 do_store_right): New functions.
2110 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2112 configure.in: Let the tx39 use igen again.
2115 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2117 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2118 not an address sized quantity. Return zero for cache sizes.
2120 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2122 * mips.igen (r3900): r3900 does not support 64 bit integer
2125 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2127 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2129 * configure : Rebuild.
2131 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2133 * configure: Regenerated to track ../common/aclocal.m4 changes.
2135 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2137 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2139 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2141 * configure: Regenerated to track ../common/aclocal.m4 changes.
2142 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2144 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2146 * configure: Regenerated to track ../common/aclocal.m4 changes.
2148 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2150 * interp.c (Max, Min): Comment out functions. Not yet used.
2152 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2154 * configure: Regenerated to track ../common/aclocal.m4 changes.
2156 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2158 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2159 configurable settings for stand-alone simulator.
2161 * configure.in: Added X11 search, just in case.
2163 * configure: Regenerated.
2165 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2167 * interp.c (sim_write, sim_read, load_memory, store_memory):
2168 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2170 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2172 * sim-main.h (GETFCC): Return an unsigned value.
2174 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2176 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2177 (DADD): Result destination is RD not RT.
2179 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2181 * sim-main.h (HIACCESS, LOACCESS): Always define.
2183 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2185 * interp.c (sim_info): Delete.
2187 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2189 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2190 (mips_option_handler): New argument `cpu'.
2191 (sim_open): Update call to sim_add_option_table.
2193 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2195 * mips.igen (CxC1): Add tracing.
2197 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2199 * sim-main.h (Max, Min): Declare.
2201 * interp.c (Max, Min): New functions.
2203 * mips.igen (BC1): Add tracing.
2205 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
2207 * interp.c Added memory map for stack in vr4100
2209 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2211 * interp.c (load_memory): Add missing "break"'s.
2213 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2215 * interp.c (sim_store_register, sim_fetch_register): Pass in
2216 length parameter. Return -1.
2218 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2220 * interp.c: Added hardware init hook, fixed warnings.
2222 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2224 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2226 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2228 * interp.c (ifetch16): New function.
2230 * sim-main.h (IMEM32): Rename IMEM.
2231 (IMEM16_IMMED): Define.
2233 (DELAY_SLOT): Update.
2235 * m16run.c (sim_engine_run): New file.
2237 * m16.igen: All instructions except LB.
2238 (LB): Call do_load_byte.
2239 * mips.igen (do_load_byte): New function.
2240 (LB): Call do_load_byte.
2242 * mips.igen: Move spec for insn bit size and high bit from here.
2243 * Makefile.in (tmp-igen, tmp-m16): To here.
2245 * m16.dc: New file, decode mips16 instructions.
2247 * Makefile.in (SIM_NO_ALL): Define.
2248 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2250 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2252 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2253 point unit to 32 bit registers.
2254 * configure: Re-generate.
2256 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2258 * configure.in (sim_use_gen): Make IGEN the default simulator
2259 generator for generic 32 and 64 bit mips targets.
2260 * configure: Re-generate.
2262 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2264 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2267 * interp.c (sim_fetch_register, sim_store_register): Read/write
2268 FGR from correct location.
2269 (sim_open): Set size of FGR's according to
2270 WITH_TARGET_FLOATING_POINT_BITSIZE.
2272 * sim-main.h (FGR): Store floating point registers in a separate
2275 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2277 * configure: Regenerated to track ../common/aclocal.m4 changes.
2279 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2281 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2283 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2285 * interp.c (pending_tick): New function. Deliver pending writes.
2287 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2288 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2289 it can handle mixed sized quantites and single bits.
2291 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2293 * interp.c (oengine.h): Do not include when building with IGEN.
2294 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2295 (sim_info): Ditto for PROCESSOR_64BIT.
2296 (sim_monitor): Replace ut_reg with unsigned_word.
2297 (*): Ditto for t_reg.
2298 (LOADDRMASK): Define.
2299 (sim_open): Remove defunct check that host FP is IEEE compliant,
2300 using software to emulate floating point.
2301 (value_fpr, ...): Always compile, was conditional on HASFPU.
2303 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2305 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2308 * interp.c (SD, CPU): Define.
2309 (mips_option_handler): Set flags in each CPU.
2310 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2311 (sim_close): Do not clear STATE, deleted anyway.
2312 (sim_write, sim_read): Assume CPU zero's vm should be used for
2314 (sim_create_inferior): Set the PC for all processors.
2315 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2317 (mips16_entry): Pass correct nr of args to store_word, load_word.
2318 (ColdReset): Cold reset all cpu's.
2319 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2320 (sim_monitor, load_memory, store_memory, signal_exception): Use
2321 `CPU' instead of STATE_CPU.
2324 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2327 * sim-main.h (signal_exception): Add sim_cpu arg.
2328 (SignalException*): Pass both SD and CPU to signal_exception.
2329 * interp.c (signal_exception): Update.
2331 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2333 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2334 address_translation): Ditto
2335 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2337 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2339 * configure: Regenerated to track ../common/aclocal.m4 changes.
2341 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2343 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2345 * mips.igen (model): Map processor names onto BFD name.
2347 * sim-main.h (CPU_CIA): Delete.
2348 (SET_CIA, GET_CIA): Define
2350 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2352 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2355 * configure.in (default_endian): Configure a big-endian simulator
2357 * configure: Re-generate.
2359 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2361 * configure: Regenerated to track ../common/aclocal.m4 changes.
2363 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2365 * interp.c (sim_monitor): Handle Densan monitor outbyte
2366 and inbyte functions.
2368 1997-12-29 Felix Lee <flee@cygnus.com>
2370 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2372 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2374 * Makefile.in (tmp-igen): Arrange for $zero to always be
2375 reset to zero after every instruction.
2377 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2379 * configure: Regenerated to track ../common/aclocal.m4 changes.
2382 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2384 * mips.igen (MSUB): Fix to work like MADD.
2385 * gencode.c (MSUB): Similarly.
2387 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2389 * configure: Regenerated to track ../common/aclocal.m4 changes.
2391 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2393 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2395 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2397 * sim-main.h (sim-fpu.h): Include.
2399 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2400 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2401 using host independant sim_fpu module.
2403 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2405 * interp.c (signal_exception): Report internal errors with SIGABRT
2408 * sim-main.h (C0_CONFIG): New register.
2409 (signal.h): No longer include.
2411 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2413 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2415 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2417 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2419 * mips.igen: Tag vr5000 instructions.
2420 (ANDI): Was missing mipsIV model, fix assembler syntax.
2421 (do_c_cond_fmt): New function.
2422 (C.cond.fmt): Handle mips I-III which do not support CC field
2424 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2425 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2427 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2428 vr5000 which saves LO in a GPR separatly.
2430 * configure.in (enable-sim-igen): For vr5000, select vr5000
2431 specific instructions.
2432 * configure: Re-generate.
2434 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2436 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2438 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2439 fmt_uninterpreted_64 bit cases to switch. Convert to
2442 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2444 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2445 as specified in IV3.2 spec.
2446 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2448 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2450 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2451 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2452 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2453 PENDING_FILL versions of instructions. Simplify.
2455 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2457 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2459 (MTHI, MFHI): Disable code checking HI-LO.
2461 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2463 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2465 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2467 * gencode.c (build_mips16_operands): Replace IPC with cia.
2469 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2470 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2472 (UndefinedResult): Replace function with macro/function
2474 (sim_engine_run): Don't save PC in IPC.
2476 * sim-main.h (IPC): Delete.
2479 * interp.c (signal_exception, store_word, load_word,
2480 address_translation, load_memory, store_memory, cache_op,
2481 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2482 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2483 current instruction address - cia - argument.
2484 (sim_read, sim_write): Call address_translation directly.
2485 (sim_engine_run): Rename variable vaddr to cia.
2486 (signal_exception): Pass cia to sim_monitor
2488 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2489 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2490 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2492 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2493 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2496 * interp.c (signal_exception): Pass restart address to
2499 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2500 idecode.o): Add dependency.
2502 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2504 (DELAY_SLOT): Update NIA not PC with branch address.
2505 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2507 * mips.igen: Use CIA not PC in branch calculations.
2508 (illegal): Call SignalException.
2509 (BEQ, ADDIU): Fix assembler.
2511 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2513 * m16.igen (JALX): Was missing.
2515 * configure.in (enable-sim-igen): New configuration option.
2516 * configure: Re-generate.
2518 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2520 * interp.c (load_memory, store_memory): Delete parameter RAW.
2521 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2522 bypassing {load,store}_memory.
2524 * sim-main.h (ByteSwapMem): Delete definition.
2526 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2528 * interp.c (sim_do_command, sim_commands): Delete mips specific
2529 commands. Handled by module sim-options.
2531 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2532 (WITH_MODULO_MEMORY): Define.
2534 * interp.c (sim_info): Delete code printing memory size.
2536 * interp.c (mips_size): Nee sim_size, delete function.
2538 (monitor, monitor_base, monitor_size): Delete global variables.
2539 (sim_open, sim_close): Delete code creating monitor and other
2540 memory regions. Use sim-memopts module, via sim_do_commandf, to
2541 manage memory regions.
2542 (load_memory, store_memory): Use sim-core for memory model.
2544 * interp.c (address_translation): Delete all memory map code
2545 except line forcing 32 bit addresses.
2547 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2549 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2552 * interp.c (logfh, logfile): Delete globals.
2553 (sim_open, sim_close): Delete code opening & closing log file.
2554 (mips_option_handler): Delete -l and -n options.
2555 (OPTION mips_options): Ditto.
2557 * interp.c (OPTION mips_options): Rename option trace to dinero.
2558 (mips_option_handler): Update.
2560 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2562 * interp.c (fetch_str): New function.
2563 (sim_monitor): Rewrite using sim_read & sim_write.
2564 (sim_open): Check magic number.
2565 (sim_open): Write monitor vectors into memory using sim_write.
2566 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2567 (sim_read, sim_write): Simplify - transfer data one byte at a
2569 (load_memory, store_memory): Clarify meaning of parameter RAW.
2571 * sim-main.h (isHOST): Defete definition.
2572 (isTARGET): Mark as depreciated.
2573 (address_translation): Delete parameter HOST.
2575 * interp.c (address_translation): Delete parameter HOST.
2577 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2581 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2582 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2584 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2586 * mips.igen: Add model filter field to records.
2588 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2590 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2592 interp.c (sim_engine_run): Do not compile function sim_engine_run
2593 when WITH_IGEN == 1.
2595 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2596 target architecture.
2598 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2599 igen. Replace with configuration variables sim_igen_flags /
2602 * m16.igen: New file. Copy mips16 insns here.
2603 * mips.igen: From here.
2605 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2607 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2609 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2611 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2613 * gencode.c (build_instruction): Follow sim_write's lead in using
2614 BigEndianMem instead of !ByteSwapMem.
2616 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2618 * configure.in (sim_gen): Dependent on target, select type of
2619 generator. Always select old style generator.
2621 configure: Re-generate.
2623 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2625 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2626 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2627 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2628 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2629 SIM_@sim_gen@_*, set by autoconf.
2631 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2633 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2635 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2636 CURRENT_FLOATING_POINT instead.
2638 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2639 (address_translation): Raise exception InstructionFetch when
2640 translation fails and isINSTRUCTION.
2642 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2643 sim_engine_run): Change type of of vaddr and paddr to
2645 (address_translation, prefetch, load_memory, store_memory,
2646 cache_op): Change type of vAddr and pAddr to address_word.
2648 * gencode.c (build_instruction): Change type of vaddr and paddr to
2651 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2653 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2654 macro to obtain result of ALU op.
2656 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2658 * interp.c (sim_info): Call profile_print.
2660 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2662 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2664 * sim-main.h (WITH_PROFILE): Do not define, defined in
2665 common/sim-config.h. Use sim-profile module.
2666 (simPROFILE): Delete defintion.
2668 * interp.c (PROFILE): Delete definition.
2669 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2670 (sim_close): Delete code writing profile histogram.
2671 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2673 (sim_engine_run): Delete code profiling the PC.
2675 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2677 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2679 * interp.c (sim_monitor): Make register pointers of type
2682 * sim-main.h: Make registers of type unsigned_word not
2685 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2687 * interp.c (sync_operation): Rename from SyncOperation, make
2688 global, add SD argument.
2689 (prefetch): Rename from Prefetch, make global, add SD argument.
2690 (decode_coproc): Make global.
2692 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2694 * gencode.c (build_instruction): Generate DecodeCoproc not
2695 decode_coproc calls.
2697 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2698 (SizeFGR): Move to sim-main.h
2699 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2700 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2701 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2703 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2704 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2705 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2706 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2707 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2708 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2710 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2712 (sim-alu.h): Include.
2713 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2714 (sim_cia): Typedef to instruction_address.
2716 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2718 * Makefile.in (interp.o): Rename generated file engine.c to
2723 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2727 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2729 * gencode.c (build_instruction): For "FPSQRT", output correct
2730 number of arguments to Recip.
2732 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2734 * Makefile.in (interp.o): Depends on sim-main.h
2736 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2738 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2739 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2740 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2741 STATE, DSSTATE): Define
2742 (GPR, FGRIDX, ..): Define.
2744 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2745 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2746 (GPR, FGRIDX, ...): Delete macros.
2748 * interp.c: Update names to match defines from sim-main.h
2750 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2752 * interp.c (sim_monitor): Add SD argument.
2753 (sim_warning): Delete. Replace calls with calls to
2755 (sim_error): Delete. Replace calls with sim_io_error.
2756 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2757 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2758 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2760 (mips_size): Rename from sim_size. Add SD argument.
2762 * interp.c (simulator): Delete global variable.
2763 (callback): Delete global variable.
2764 (mips_option_handler, sim_open, sim_write, sim_read,
2765 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2766 sim_size,sim_monitor): Use sim_io_* not callback->*.
2767 (sim_open): ZALLOC simulator struct.
2768 (PROFILE): Do not define.
2770 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2772 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2773 support.h with corresponding code.
2775 * sim-main.h (word64, uword64), support.h: Move definition to
2777 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2780 * Makefile.in: Update dependencies
2781 * interp.c: Do not include.
2783 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2785 * interp.c (address_translation, load_memory, store_memory,
2786 cache_op): Rename to from AddressTranslation et.al., make global,
2789 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2792 * interp.c (SignalException): Rename to signal_exception, make
2795 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2797 * sim-main.h (SignalException, SignalExceptionInterrupt,
2798 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2799 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2800 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2803 * interp.c, support.h: Use.
2805 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2807 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2808 to value_fpr / store_fpr. Add SD argument.
2809 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2810 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2812 * sim-main.h (ValueFPR, StoreFPR): Define.
2814 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2816 * interp.c (sim_engine_run): Check consistency between configure
2817 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2820 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2821 (mips_fpu): Configure WITH_FLOATING_POINT.
2822 (mips_endian): Configure WITH_TARGET_ENDIAN.
2823 * configure: Update.
2825 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2827 * configure: Regenerated to track ../common/aclocal.m4 changes.
2829 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2831 * configure: Regenerated.
2833 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2835 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2837 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2839 * gencode.c (print_igen_insn_models): Assume certain architectures
2840 include all mips* instructions.
2841 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2844 * Makefile.in (tmp.igen): Add target. Generate igen input from
2847 * gencode.c (FEATURE_IGEN): Define.
2848 (main): Add --igen option. Generate output in igen format.
2849 (process_instructions): Format output according to igen option.
2850 (print_igen_insn_format): New function.
2851 (print_igen_insn_models): New function.
2852 (process_instructions): Only issue warnings and ignore
2853 instructions when no FEATURE_IGEN.
2855 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2857 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2860 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2862 * configure: Regenerated to track ../common/aclocal.m4 changes.
2864 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2866 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2867 SIM_RESERVED_BITS): Delete, moved to common.
2868 (SIM_EXTRA_CFLAGS): Update.
2870 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2872 * configure.in: Configure non-strict memory alignment.
2873 * configure: Regenerated to track ../common/aclocal.m4 changes.
2875 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2877 * configure: Regenerated to track ../common/aclocal.m4 changes.
2879 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2881 * gencode.c (SDBBP,DERET): Added (3900) insns.
2882 (RFE): Turn on for 3900.
2883 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2884 (dsstate): Made global.
2885 (SUBTARGET_R3900): Added.
2886 (CANCELDELAYSLOT): New.
2887 (SignalException): Ignore SystemCall rather than ignore and
2888 terminate. Add DebugBreakPoint handling.
2889 (decode_coproc): New insns RFE, DERET; and new registers Debug
2890 and DEPC protected by SUBTARGET_R3900.
2891 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2893 * Makefile.in,configure.in: Add mips subtarget option.
2894 * configure: Update.
2896 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2898 * gencode.c: Add r3900 (tx39).
2901 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2903 * gencode.c (build_instruction): Don't need to subtract 4 for
2906 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2908 * interp.c: Correct some HASFPU problems.
2910 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2912 * configure: Regenerated to track ../common/aclocal.m4 changes.
2914 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2916 * interp.c (mips_options): Fix samples option short form, should
2919 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2921 * interp.c (sim_info): Enable info code. Was just returning.
2923 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2925 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2928 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2930 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2932 (build_instruction): Ditto for LL.
2934 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2936 * configure: Regenerated to track ../common/aclocal.m4 changes.
2938 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2940 * configure: Regenerated to track ../common/aclocal.m4 changes.
2943 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2945 * interp.c (sim_open): Add call to sim_analyze_program, update
2948 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2950 * interp.c (sim_kill): Delete.
2951 (sim_create_inferior): Add ABFD argument. Set PC from same.
2952 (sim_load): Move code initializing trap handlers from here.
2953 (sim_open): To here.
2954 (sim_load): Delete, use sim-hload.c.
2956 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2958 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2960 * configure: Regenerated to track ../common/aclocal.m4 changes.
2963 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2965 * interp.c (sim_open): Add ABFD argument.
2966 (sim_load): Move call to sim_config from here.
2967 (sim_open): To here. Check return status.
2969 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2971 * gencode.c (build_instruction): Two arg MADD should
2972 not assign result to $0.
2974 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2976 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2977 * sim/mips/configure.in: Regenerate.
2979 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2981 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2982 signed8, unsigned8 et.al. types.
2984 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2985 hosts when selecting subreg.
2987 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2989 * interp.c (sim_engine_run): Reset the ZERO register to zero
2990 regardless of FEATURE_WARN_ZERO.
2991 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2993 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2995 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2996 (SignalException): For BreakPoints ignore any mode bits and just
2998 (SignalException): Always set the CAUSE register.
3000 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3002 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3003 exception has been taken.
3005 * interp.c: Implement the ERET and mt/f sr instructions.
3007 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3009 * interp.c (SignalException): Don't bother restarting an
3012 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3014 * interp.c (SignalException): Really take an interrupt.
3015 (interrupt_event): Only deliver interrupts when enabled.
3017 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3019 * interp.c (sim_info): Only print info when verbose.
3020 (sim_info) Use sim_io_printf for output.
3022 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3024 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3027 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3029 * interp.c (sim_do_command): Check for common commands if a
3030 simulator specific command fails.
3032 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3034 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3035 and simBE when DEBUG is defined.
3037 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3039 * interp.c (interrupt_event): New function. Pass exception event
3040 onto exception handler.
3042 * configure.in: Check for stdlib.h.
3043 * configure: Regenerate.
3045 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3046 variable declaration.
3047 (build_instruction): Initialize memval1.
3048 (build_instruction): Add UNUSED attribute to byte, bigend,
3050 (build_operands): Ditto.
3052 * interp.c: Fix GCC warnings.
3053 (sim_get_quit_code): Delete.
3055 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3056 * Makefile.in: Ditto.
3057 * configure: Re-generate.
3059 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3061 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3063 * interp.c (mips_option_handler): New function parse argumes using
3065 (myname): Replace with STATE_MY_NAME.
3066 (sim_open): Delete check for host endianness - performed by
3068 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3069 (sim_open): Move much of the initialization from here.
3070 (sim_load): To here. After the image has been loaded and
3072 (sim_open): Move ColdReset from here.
3073 (sim_create_inferior): To here.
3074 (sim_open): Make FP check less dependant on host endianness.
3076 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3078 * interp.c (sim_set_callbacks): Delete.
3080 * interp.c (membank, membank_base, membank_size): Replace with
3081 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3082 (sim_open): Remove call to callback->init. gdb/run do this.
3086 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3088 * interp.c (big_endian_p): Delete, replaced by
3089 current_target_byte_order.
3091 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3093 * interp.c (host_read_long, host_read_word, host_swap_word,
3094 host_swap_long): Delete. Using common sim-endian.
3095 (sim_fetch_register, sim_store_register): Use H2T.
3096 (pipeline_ticks): Delete. Handled by sim-events.
3098 (sim_engine_run): Update.
3100 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3102 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3104 (SignalException): To here. Signal using sim_engine_halt.
3105 (sim_stop_reason): Delete, moved to common.
3107 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3109 * interp.c (sim_open): Add callback argument.
3110 (sim_set_callbacks): Delete SIM_DESC argument.
3113 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3115 * Makefile.in (SIM_OBJS): Add common modules.
3117 * interp.c (sim_set_callbacks): Also set SD callback.
3118 (set_endianness, xfer_*, swap_*): Delete.
3119 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3120 Change to functions using sim-endian macros.
3121 (control_c, sim_stop): Delete, use common version.
3122 (simulate): Convert into.
3123 (sim_engine_run): This function.
3124 (sim_resume): Delete.
3126 * interp.c (simulation): New variable - the simulator object.
3127 (sim_kind): Delete global - merged into simulation.
3128 (sim_load): Cleanup. Move PC assignment from here.
3129 (sim_create_inferior): To here.
3131 * sim-main.h: New file.
3132 * interp.c (sim-main.h): Include.
3134 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3136 * configure: Regenerated to track ../common/aclocal.m4 changes.
3138 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3140 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3142 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3144 * gencode.c (build_instruction): DIV instructions: check
3145 for division by zero and integer overflow before using
3146 host's division operation.
3148 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3150 * Makefile.in (SIM_OBJS): Add sim-load.o.
3151 * interp.c: #include bfd.h.
3152 (target_byte_order): Delete.
3153 (sim_kind, myname, big_endian_p): New static locals.
3154 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3155 after argument parsing. Recognize -E arg, set endianness accordingly.
3156 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3157 load file into simulator. Set PC from bfd.
3158 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3159 (set_endianness): Use big_endian_p instead of target_byte_order.
3161 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3163 * interp.c (sim_size): Delete prototype - conflicts with
3164 definition in remote-sim.h. Correct definition.
3166 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3168 * configure: Regenerated to track ../common/aclocal.m4 changes.
3171 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3173 * interp.c (sim_open): New arg `kind'.
3175 * configure: Regenerated to track ../common/aclocal.m4 changes.
3177 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3179 * configure: Regenerated to track ../common/aclocal.m4 changes.
3181 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3183 * interp.c (sim_open): Set optind to 0 before calling getopt.
3185 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3187 * configure: Regenerated to track ../common/aclocal.m4 changes.
3189 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3191 * interp.c : Replace uses of pr_addr with pr_uword64
3192 where the bit length is always 64 independent of SIM_ADDR.
3193 (pr_uword64) : added.
3195 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3197 * configure: Re-generate.
3199 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3201 * configure: Regenerate to track ../common/aclocal.m4 changes.
3203 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3205 * interp.c (sim_open): New SIM_DESC result. Argument is now
3207 (other sim_*): New SIM_DESC argument.
3209 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3211 * interp.c: Fix printing of addresses for non-64-bit targets.
3212 (pr_addr): Add function to print address based on size.
3214 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3216 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3218 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3220 * gencode.c (build_mips16_operands): Correct computation of base
3221 address for extended PC relative instruction.
3223 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3225 * interp.c (mips16_entry): Add support for floating point cases.
3226 (SignalException): Pass floating point cases to mips16_entry.
3227 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3229 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3231 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3232 and then set the state to fmt_uninterpreted.
3233 (COP_SW): Temporarily set the state to fmt_word while calling
3236 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3238 * gencode.c (build_instruction): The high order may be set in the
3239 comparison flags at any ISA level, not just ISA 4.
3241 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3243 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3244 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3245 * configure.in: sinclude ../common/aclocal.m4.
3246 * configure: Regenerated.
3248 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3250 * configure: Rebuild after change to aclocal.m4.
3252 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3254 * configure configure.in Makefile.in: Update to new configure
3255 scheme which is more compatible with WinGDB builds.
3256 * configure.in: Improve comment on how to run autoconf.
3257 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3258 * Makefile.in: Use autoconf substitution to install common
3261 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3263 * gencode.c (build_instruction): Use BigEndianCPU instead of
3266 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3268 * interp.c (sim_monitor): Make output to stdout visible in
3269 wingdb's I/O log window.
3271 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3273 * support.h: Undo previous change to SIGTRAP
3276 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3278 * interp.c (store_word, load_word): New static functions.
3279 (mips16_entry): New static function.
3280 (SignalException): Look for mips16 entry and exit instructions.
3281 (simulate): Use the correct index when setting fpr_state after
3282 doing a pending move.
3284 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3286 * interp.c: Fix byte-swapping code throughout to work on
3287 both little- and big-endian hosts.
3289 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3291 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3292 with gdb/config/i386/xm-windows.h.
3294 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3296 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3297 that messes up arithmetic shifts.
3299 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3301 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3302 SIGTRAP and SIGQUIT for _WIN32.
3304 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3306 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3307 force a 64 bit multiplication.
3308 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3309 destination register is 0, since that is the default mips16 nop
3312 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3314 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3315 (build_endian_shift): Don't check proc64.
3316 (build_instruction): Always set memval to uword64. Cast op2 to
3317 uword64 when shifting it left in memory instructions. Always use
3318 the same code for stores--don't special case proc64.
3320 * gencode.c (build_mips16_operands): Fix base PC value for PC
3322 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3324 * interp.c (simJALDELAYSLOT): Define.
3325 (JALDELAYSLOT): Define.
3326 (INDELAYSLOT, INJALDELAYSLOT): Define.
3327 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3329 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3331 * interp.c (sim_open): add flush_cache as a PMON routine
3332 (sim_monitor): handle flush_cache by ignoring it
3334 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3336 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3338 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3339 (BigEndianMem): Rename to ByteSwapMem and change sense.
3340 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3341 BigEndianMem references to !ByteSwapMem.
3342 (set_endianness): New function, with prototype.
3343 (sim_open): Call set_endianness.
3344 (sim_info): Use simBE instead of BigEndianMem.
3345 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3346 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3347 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3348 ifdefs, keeping the prototype declaration.
3349 (swap_word): Rewrite correctly.
3350 (ColdReset): Delete references to CONFIG. Delete endianness related
3351 code; moved to set_endianness.
3353 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3355 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3356 * interp.c (CHECKHILO): Define away.
3357 (simSIGINT): New macro.
3358 (membank_size): Increase from 1MB to 2MB.
3359 (control_c): New function.
3360 (sim_resume): Rename parameter signal to signal_number. Add local
3361 variable prev. Call signal before and after simulate.
3362 (sim_stop_reason): Add simSIGINT support.
3363 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3365 (sim_warning): Delete call to SignalException. Do call printf_filtered
3367 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3368 a call to sim_warning.
3370 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3372 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3373 16 bit instructions.
3375 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3377 Add support for mips16 (16 bit MIPS implementation):
3378 * gencode.c (inst_type): Add mips16 instruction encoding types.
3379 (GETDATASIZEINSN): Define.
3380 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3381 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3383 (MIPS16_DECODE): New table, for mips16 instructions.
3384 (bitmap_val): New static function.
3385 (struct mips16_op): Define.
3386 (mips16_op_table): New table, for mips16 operands.
3387 (build_mips16_operands): New static function.
3388 (process_instructions): If PC is odd, decode a mips16
3389 instruction. Break out instruction handling into new
3390 build_instruction function.
3391 (build_instruction): New static function, broken out of
3392 process_instructions. Check modifiers rather than flags for SHIFT
3393 bit count and m[ft]{hi,lo} direction.
3394 (usage): Pass program name to fprintf.
3395 (main): Remove unused variable this_option_optind. Change
3396 ``*loptarg++'' to ``loptarg++''.
3397 (my_strtoul): Parenthesize && within ||.
3398 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3399 (simulate): If PC is odd, fetch a 16 bit instruction, and
3400 increment PC by 2 rather than 4.
3401 * configure.in: Add case for mips16*-*-*.
3402 * configure: Rebuild.
3404 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3406 * interp.c: Allow -t to enable tracing in standalone simulator.
3407 Fix garbage output in trace file and error messages.
3409 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3411 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3412 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3413 * configure.in: Simplify using macros in ../common/aclocal.m4.
3414 * configure: Regenerated.
3415 * tconfig.in: New file.
3417 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3419 * interp.c: Fix bugs in 64-bit port.
3420 Use ansi function declarations for msvc compiler.
3421 Initialize and test file pointer in trace code.
3422 Prevent duplicate definition of LAST_EMED_REGNUM.
3424 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3426 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3428 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3430 * interp.c (SignalException): Check for explicit terminating
3432 * gencode.c: Pass instruction value through SignalException()
3433 calls for Trap, Breakpoint and Syscall.
3435 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3437 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3438 only used on those hosts that provide it.
3439 * configure.in: Add sqrt() to list of functions to be checked for.
3440 * config.in: Re-generated.
3441 * configure: Re-generated.
3443 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3445 * gencode.c (process_instructions): Call build_endian_shift when
3446 expanding STORE RIGHT, to fix swr.
3447 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3448 clear the high bits.
3449 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3450 Fix float to int conversions to produce signed values.
3452 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3454 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3455 (process_instructions): Correct handling of nor instruction.
3456 Correct shift count for 32 bit shift instructions. Correct sign
3457 extension for arithmetic shifts to not shift the number of bits in
3458 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3459 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3461 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3462 It's OK to have a mult follow a mult. What's not OK is to have a
3463 mult follow an mfhi.
3464 (Convert): Comment out incorrect rounding code.
3466 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3468 * interp.c (sim_monitor): Improved monitor printf
3469 simulation. Tidied up simulator warnings, and added "--log" option
3470 for directing warning message output.
3471 * gencode.c: Use sim_warning() rather than WARNING macro.
3473 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3475 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3476 getopt1.o, rather than on gencode.c. Link objects together.
3477 Don't link against -liberty.
3478 (gencode.o, getopt.o, getopt1.o): New targets.
3479 * gencode.c: Include <ctype.h> and "ansidecl.h".
3480 (AND): Undefine after including "ansidecl.h".
3481 (ULONG_MAX): Define if not defined.
3482 (OP_*): Don't define macros; now defined in opcode/mips.h.
3483 (main): Call my_strtoul rather than strtoul.
3484 (my_strtoul): New static function.
3486 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3488 * gencode.c (process_instructions): Generate word64 and uword64
3489 instead of `long long' and `unsigned long long' data types.
3490 * interp.c: #include sysdep.h to get signals, and define default
3492 * (Convert): Work around for Visual-C++ compiler bug with type
3494 * support.h: Make things compile under Visual-C++ by using
3495 __int64 instead of `long long'. Change many refs to long long
3496 into word64/uword64 typedefs.
3498 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3500 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3501 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3503 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3504 (AC_PROG_INSTALL): Added.
3505 (AC_PROG_CC): Moved to before configure.host call.
3506 * configure: Rebuilt.
3508 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3510 * configure.in: Define @SIMCONF@ depending on mips target.
3511 * configure: Rebuild.
3512 * Makefile.in (run): Add @SIMCONF@ to control simulator
3514 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3515 * interp.c: Remove some debugging, provide more detailed error
3516 messages, update memory accesses to use LOADDRMASK.
3518 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3520 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3521 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3523 * configure: Rebuild.
3524 * config.in: New file, generated by autoheader.
3525 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3526 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3527 HAVE_ANINT and HAVE_AINT, as appropriate.
3528 * Makefile.in (run): Use @LIBS@ rather than -lm.
3529 (interp.o): Depend upon config.h.
3530 (Makefile): Just rebuild Makefile.
3531 (clean): Remove stamp-h.
3532 (mostlyclean): Make the same as clean, not as distclean.
3533 (config.h, stamp-h): New targets.
3535 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3537 * interp.c (ColdReset): Fix boolean test. Make all simulator
3540 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3542 * interp.c (xfer_direct_word, xfer_direct_long,
3543 swap_direct_word, swap_direct_long, xfer_big_word,
3544 xfer_big_long, xfer_little_word, xfer_little_long,
3545 swap_word,swap_long): Added.
3546 * interp.c (ColdReset): Provide function indirection to
3547 host<->simulated_target transfer routines.
3548 * interp.c (sim_store_register, sim_fetch_register): Updated to
3549 make use of indirected transfer routines.
3551 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3553 * gencode.c (process_instructions): Ensure FP ABS instruction
3555 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3556 system call support.
3558 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3560 * interp.c (sim_do_command): Complain if callback structure not
3563 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3565 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3566 support for Sun hosts.
3567 * Makefile.in (gencode): Ensure the host compiler and libraries
3568 used for cross-hosted build.
3570 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3572 * interp.c, gencode.c: Some more (TODO) tidying.
3574 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3576 * gencode.c, interp.c: Replaced explicit long long references with
3577 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3578 * support.h (SET64LO, SET64HI): Macros added.
3580 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3582 * configure: Regenerate with autoconf 2.7.
3584 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3586 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3587 * support.h: Remove superfluous "1" from #if.
3588 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3590 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3592 * interp.c (StoreFPR): Control UndefinedResult() call on
3593 WARN_RESULT manifest.
3595 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3597 * gencode.c: Tidied instruction decoding, and added FP instruction
3600 * interp.c: Added dineroIII, and BSD profiling support. Also
3601 run-time FP handling.
3603 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3605 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3606 gencode.c, interp.c, support.h: created.