1 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
3 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
5 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
7 2004-04-10 Chris Demetriou <cgd@broadcom.com>
9 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
11 2004-04-09 Chris Demetriou <cgd@broadcom.com>
13 * mips.igen (check_fmt): Remove.
14 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
15 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
16 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
17 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
18 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
19 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
20 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
21 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
22 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
23 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
25 2004-04-09 Chris Demetriou <cgd@broadcom.com>
27 * sb1.igen (check_sbx): New function.
28 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
30 2004-03-29 Chris Demetriou <cgd@broadcom.com>
31 Richard Sandiford <rsandifo@redhat.com>
33 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
34 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
35 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
36 separate implementations for mipsIV and mipsV. Use new macros to
37 determine whether the restrictions apply.
39 2004-01-19 Chris Demetriou <cgd@broadcom.com>
41 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
42 (check_mult_hilo): Improve comments.
43 (check_div_hilo): Likewise. Also, fork off a new version
44 to handle mips32/mips64 (since there are no hazards to check
47 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
49 * mips.igen (do_dmultx): Fix check for negative operands.
51 2003-05-16 Ian Lance Taylor <ian@airs.com>
53 * Makefile.in (SHELL): Make sure this is defined.
54 (various): Use $(SHELL) whenever we invoke move-if-change.
56 2003-05-03 Chris Demetriou <cgd@broadcom.com>
58 * cp1.c: Tweak attribution slightly.
61 * mdmx.igen: Likewise.
62 * mips3d.igen: Likewise.
65 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
67 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
70 2003-02-27 Andrew Cagney <cagney@redhat.com>
72 * interp.c (sim_open): Rename _bfd to bfd.
73 (sim_create_inferior): Ditto.
75 2003-01-14 Chris Demetriou <cgd@broadcom.com>
77 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
79 2003-01-14 Chris Demetriou <cgd@broadcom.com>
81 * mips.igen (EI, DI): Remove.
83 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
85 * Makefile.in (tmp-run-multi): Fix mips16 filter.
87 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
88 Andrew Cagney <ac131313@redhat.com>
89 Gavin Romig-Koch <gavin@redhat.com>
90 Graydon Hoare <graydon@redhat.com>
91 Aldy Hernandez <aldyh@redhat.com>
92 Dave Brolley <brolley@redhat.com>
93 Chris Demetriou <cgd@broadcom.com>
95 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
96 (sim_mach_default): New variable.
97 (mips64vr-*-*, mips64vrel-*-*): New configurations.
98 Add a new simulator generator, MULTI.
99 * configure: Regenerate.
100 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
101 (multi-run.o): New dependency.
102 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
103 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
104 (tmp-multi): Combine them.
105 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
106 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
107 (distclean-extra): New rule.
108 * sim-main.h: Include bfd.h.
109 (MIPS_MACH): New macro.
110 * mips.igen (vr4120, vr5400, vr5500): New models.
111 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
112 * vr.igen: Replace with new version.
114 2003-01-04 Chris Demetriou <cgd@broadcom.com>
116 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
117 * configure: Regenerate.
119 2002-12-31 Chris Demetriou <cgd@broadcom.com>
121 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
122 * mips.igen: Remove all invocations of check_branch_bug and
125 2002-12-16 Chris Demetriou <cgd@broadcom.com>
127 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
129 2002-07-30 Chris Demetriou <cgd@broadcom.com>
131 * mips.igen (do_load_double, do_store_double): New functions.
132 (LDC1, SDC1): Rename to...
133 (LDC1b, SDC1b): respectively.
134 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
136 2002-07-29 Michael Snyder <msnyder@redhat.com>
138 * cp1.c (fp_recip2): Modify initialization expression so that
139 GCC will recognize it as constant.
141 2002-06-18 Chris Demetriou <cgd@broadcom.com>
143 * mdmx.c (SD_): Delete.
144 (Unpredictable): Re-define, for now, to directly invoke
145 unpredictable_action().
146 (mdmx_acc_op): Fix error in .ob immediate handling.
148 2002-06-18 Andrew Cagney <cagney@redhat.com>
150 * interp.c (sim_firmware_command): Initialize `address'.
152 2002-06-16 Andrew Cagney <ac131313@redhat.com>
154 * configure: Regenerated to track ../common/aclocal.m4 changes.
156 2002-06-14 Chris Demetriou <cgd@broadcom.com>
157 Ed Satterthwaite <ehs@broadcom.com>
159 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
160 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
161 * mips.igen: Include mips3d.igen.
162 (mips3d): New model name for MIPS-3D ASE instructions.
163 (CVT.W.fmt): Don't use this instruction for word (source) format
165 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
166 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
167 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
168 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
169 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
170 (RSquareRoot1, RSquareRoot2): New macros.
171 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
172 (fp_rsqrt2): New functions.
173 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
174 * configure: Regenerate.
176 2002-06-13 Chris Demetriou <cgd@broadcom.com>
177 Ed Satterthwaite <ehs@broadcom.com>
179 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
180 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
181 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
182 (convert): Note that this function is not used for paired-single
184 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
185 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
186 (check_fmt_p): Enable paired-single support.
187 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
188 (PUU.PS): New instructions.
189 (CVT.S.fmt): Don't use this instruction for paired-single format
191 * sim-main.h (FP_formats): New value 'fmt_ps.'
192 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
193 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
195 2002-06-12 Chris Demetriou <cgd@broadcom.com>
197 * mips.igen: Fix formatting of function calls in
200 2002-06-12 Chris Demetriou <cgd@broadcom.com>
202 * mips.igen (MOVN, MOVZ): Trace result.
203 (TNEI): Print "tnei" as the opcode name in traces.
204 (CEIL.W): Add disassembly string for traces.
205 (RSQRT.fmt): Make location of disassembly string consistent
206 with other instructions.
208 2002-06-12 Chris Demetriou <cgd@broadcom.com>
210 * mips.igen (X): Delete unused function.
212 2002-06-08 Andrew Cagney <cagney@redhat.com>
214 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
216 2002-06-07 Chris Demetriou <cgd@broadcom.com>
217 Ed Satterthwaite <ehs@broadcom.com>
219 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
220 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
221 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
222 (fp_nmsub): New prototypes.
223 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
224 (NegMultiplySub): New defines.
225 * mips.igen (RSQRT.fmt): Use RSquareRoot().
226 (MADD.D, MADD.S): Replace with...
227 (MADD.fmt): New instruction.
228 (MSUB.D, MSUB.S): Replace with...
229 (MSUB.fmt): New instruction.
230 (NMADD.D, NMADD.S): Replace with...
231 (NMADD.fmt): New instruction.
232 (NMSUB.D, MSUB.S): Replace with...
233 (NMSUB.fmt): New instruction.
235 2002-06-07 Chris Demetriou <cgd@broadcom.com>
236 Ed Satterthwaite <ehs@broadcom.com>
238 * cp1.c: Fix more comment spelling and formatting.
239 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
240 (denorm_mode): New function.
241 (fpu_unary, fpu_binary): Round results after operation, collect
242 status from rounding operations, and update the FCSR.
243 (convert): Collect status from integer conversions and rounding
244 operations, and update the FCSR. Adjust NaN values that result
245 from conversions. Convert to use sim_io_eprintf rather than
246 fprintf, and remove some debugging code.
247 * cp1.h (fenr_FS): New define.
249 2002-06-07 Chris Demetriou <cgd@broadcom.com>
251 * cp1.c (convert): Remove unusable debugging code, and move MIPS
252 rounding mode to sim FP rounding mode flag conversion code into...
253 (rounding_mode): New function.
255 2002-06-07 Chris Demetriou <cgd@broadcom.com>
257 * cp1.c: Clean up formatting of a few comments.
258 (value_fpr): Reformat switch statement.
260 2002-06-06 Chris Demetriou <cgd@broadcom.com>
261 Ed Satterthwaite <ehs@broadcom.com>
264 * sim-main.h: Include cp1.h.
265 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
266 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
267 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
268 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
269 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
270 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
271 * cp1.c: Don't include sim-fpu.h; already included by
272 sim-main.h. Clean up formatting of some comments.
273 (NaN, Equal, Less): Remove.
274 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
275 (fp_cmp): New functions.
276 * mips.igen (do_c_cond_fmt): Remove.
277 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
278 Compare. Add result tracing.
279 (CxC1): Remove, replace with...
280 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
281 (DMxC1): Remove, replace with...
282 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
283 (MxC1): Remove, replace with...
284 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
286 2002-06-04 Chris Demetriou <cgd@broadcom.com>
288 * sim-main.h (FGRIDX): Remove, replace all uses with...
289 (FGR_BASE): New macro.
290 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
291 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
292 (NR_FGR, FGR): Likewise.
293 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
294 * mips.igen: Likewise.
296 2002-06-04 Chris Demetriou <cgd@broadcom.com>
298 * cp1.c: Add an FSF Copyright notice to this file.
300 2002-06-04 Chris Demetriou <cgd@broadcom.com>
301 Ed Satterthwaite <ehs@broadcom.com>
303 * cp1.c (Infinity): Remove.
304 * sim-main.h (Infinity): Likewise.
306 * cp1.c (fp_unary, fp_binary): New functions.
307 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
308 (fp_sqrt): New functions, implemented in terms of the above.
309 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
310 (Recip, SquareRoot): Remove (replaced by functions above).
311 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
312 (fp_recip, fp_sqrt): New prototypes.
313 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
314 (Recip, SquareRoot): Replace prototypes with #defines which
315 invoke the functions above.
317 2002-06-03 Chris Demetriou <cgd@broadcom.com>
319 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
320 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
321 file, remove PARAMS from prototypes.
322 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
323 simulator state arguments.
324 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
325 pass simulator state arguments.
326 * cp1.c (SD): Redefine as CPU_STATE(cpu).
327 (store_fpr, convert): Remove 'sd' argument.
328 (value_fpr): Likewise. Convert to use 'SD' instead.
330 2002-06-03 Chris Demetriou <cgd@broadcom.com>
332 * cp1.c (Min, Max): Remove #if 0'd functions.
333 * sim-main.h (Min, Max): Remove.
335 2002-06-03 Chris Demetriou <cgd@broadcom.com>
337 * cp1.c: fix formatting of switch case and default labels.
338 * interp.c: Likewise.
339 * sim-main.c: Likewise.
341 2002-06-03 Chris Demetriou <cgd@broadcom.com>
343 * cp1.c: Clean up comments which describe FP formats.
344 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
346 2002-06-03 Chris Demetriou <cgd@broadcom.com>
347 Ed Satterthwaite <ehs@broadcom.com>
349 * configure.in (mipsisa64sb1*-*-*): New target for supporting
350 Broadcom SiByte SB-1 processor configurations.
351 * configure: Regenerate.
352 * sb1.igen: New file.
353 * mips.igen: Include sb1.igen.
355 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
356 * mdmx.igen: Add "sb1" model to all appropriate functions and
358 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
359 (ob_func, ob_acc): Reference the above.
360 (qh_acc): Adjust to keep the same size as ob_acc.
361 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
362 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
364 2002-06-03 Chris Demetriou <cgd@broadcom.com>
366 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
368 2002-06-02 Chris Demetriou <cgd@broadcom.com>
369 Ed Satterthwaite <ehs@broadcom.com>
371 * mips.igen (mdmx): New (pseudo-)model.
372 * mdmx.c, mdmx.igen: New files.
373 * Makefile.in (SIM_OBJS): Add mdmx.o.
374 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
376 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
377 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
378 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
379 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
380 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
381 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
382 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
383 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
384 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
385 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
386 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
387 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
388 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
389 (qh_fmtsel): New macros.
390 (_sim_cpu): New member "acc".
391 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
392 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
394 2002-05-01 Chris Demetriou <cgd@broadcom.com>
396 * interp.c: Use 'deprecated' rather than 'depreciated.'
397 * sim-main.h: Likewise.
399 2002-05-01 Chris Demetriou <cgd@broadcom.com>
401 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
402 which wouldn't compile anyway.
403 * sim-main.h (unpredictable_action): New function prototype.
404 (Unpredictable): Define to call igen function unpredictable().
405 (NotWordValue): New macro to call igen function not_word_value().
406 (UndefinedResult): Remove.
407 * interp.c (undefined_result): Remove.
408 (unpredictable_action): New function.
409 * mips.igen (not_word_value, unpredictable): New functions.
410 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
411 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
412 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
413 NotWordValue() to check for unpredictable inputs, then
414 Unpredictable() to handle them.
416 2002-02-24 Chris Demetriou <cgd@broadcom.com>
418 * mips.igen: Fix formatting of calls to Unpredictable().
420 2002-04-20 Andrew Cagney <ac131313@redhat.com>
422 * interp.c (sim_open): Revert previous change.
424 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
426 * interp.c (sim_open): Disable chunk of code that wrote code in
427 vector table entries.
429 2002-03-19 Chris Demetriou <cgd@broadcom.com>
431 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
432 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
435 2002-03-19 Chris Demetriou <cgd@broadcom.com>
437 * cp1.c: Fix many formatting issues.
439 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
441 * cp1.c (fpu_format_name): New function to replace...
442 (DOFMT): This. Delete, and update all callers.
443 (fpu_rounding_mode_name): New function to replace...
444 (RMMODE): This. Delete, and update all callers.
446 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
448 * interp.c: Move FPU support routines from here to...
449 * cp1.c: Here. New file.
450 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
453 2002-03-12 Chris Demetriou <cgd@broadcom.com>
455 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
456 * mips.igen (mips32, mips64): New models, add to all instructions
457 and functions as appropriate.
458 (loadstore_ea, check_u64): New variant for model mips64.
459 (check_fmt_p): New variant for models mipsV and mips64, remove
460 mipsV model marking fro other variant.
463 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
464 for mips32 and mips64.
465 (DCLO, DCLZ): New instructions for mips64.
467 2002-03-07 Chris Demetriou <cgd@broadcom.com>
469 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
470 immediate or code as a hex value with the "%#lx" format.
471 (ANDI): Likewise, and fix printed instruction name.
473 2002-03-05 Chris Demetriou <cgd@broadcom.com>
475 * sim-main.h (UndefinedResult, Unpredictable): New macros
476 which currently do nothing.
478 2002-03-05 Chris Demetriou <cgd@broadcom.com>
480 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
481 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
482 (status_CU3): New definitions.
484 * sim-main.h (ExceptionCause): Add new values for MIPS32
485 and MIPS64: MDMX, MCheck, CacheErr. Update comments
486 for DebugBreakPoint and NMIReset to note their status in
488 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
489 (SignalExceptionCacheErr): New exception macros.
491 2002-03-05 Chris Demetriou <cgd@broadcom.com>
493 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
494 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
496 (SignalExceptionCoProcessorUnusable): Take as argument the
497 unusable coprocessor number.
499 2002-03-05 Chris Demetriou <cgd@broadcom.com>
501 * mips.igen: Fix formatting of all SignalException calls.
503 2002-03-05 Chris Demetriou <cgd@broadcom.com>
505 * sim-main.h (SIGNEXTEND): Remove.
507 2002-03-04 Chris Demetriou <cgd@broadcom.com>
509 * mips.igen: Remove gencode comment from top of file, fix
510 spelling in another comment.
512 2002-03-04 Chris Demetriou <cgd@broadcom.com>
514 * mips.igen (check_fmt, check_fmt_p): New functions to check
515 whether specific floating point formats are usable.
516 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
517 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
518 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
519 Use the new functions.
520 (do_c_cond_fmt): Remove format checks...
521 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
523 2002-03-03 Chris Demetriou <cgd@broadcom.com>
525 * mips.igen: Fix formatting of check_fpu calls.
527 2002-03-03 Chris Demetriou <cgd@broadcom.com>
529 * mips.igen (FLOOR.L.fmt): Store correct destination register.
531 2002-03-03 Chris Demetriou <cgd@broadcom.com>
533 * mips.igen: Remove whitespace at end of lines.
535 2002-03-02 Chris Demetriou <cgd@broadcom.com>
537 * mips.igen (loadstore_ea): New function to do effective
538 address calculations.
539 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
540 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
541 CACHE): Use loadstore_ea to do effective address computations.
543 2002-03-02 Chris Demetriou <cgd@broadcom.com>
545 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
546 * mips.igen (LL, CxC1, MxC1): Likewise.
548 2002-03-02 Chris Demetriou <cgd@broadcom.com>
550 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
551 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
552 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
553 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
554 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
555 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
556 Don't split opcode fields by hand, use the opcode field values
559 2002-03-01 Chris Demetriou <cgd@broadcom.com>
561 * mips.igen (do_divu): Fix spacing.
563 * mips.igen (do_dsllv): Move to be right before DSLLV,
564 to match the rest of the do_<shift> functions.
566 2002-03-01 Chris Demetriou <cgd@broadcom.com>
568 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
569 DSRL32, do_dsrlv): Trace inputs and results.
571 2002-03-01 Chris Demetriou <cgd@broadcom.com>
573 * mips.igen (CACHE): Provide instruction-printing string.
575 * interp.c (signal_exception): Comment tokens after #endif.
577 2002-02-28 Chris Demetriou <cgd@broadcom.com>
579 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
580 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
581 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
582 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
583 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
584 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
585 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
586 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
588 2002-02-28 Chris Demetriou <cgd@broadcom.com>
590 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
591 instruction-printing string.
592 (LWU): Use '64' as the filter flag.
594 2002-02-28 Chris Demetriou <cgd@broadcom.com>
596 * mips.igen (SDXC1): Fix instruction-printing string.
598 2002-02-28 Chris Demetriou <cgd@broadcom.com>
600 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
603 2002-02-27 Chris Demetriou <cgd@broadcom.com>
605 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
608 2002-02-27 Chris Demetriou <cgd@broadcom.com>
610 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
611 add a comma) so that it more closely match the MIPS ISA
612 documentation opcode partitioning.
613 (PREF): Put useful names on opcode fields, and include
614 instruction-printing string.
616 2002-02-27 Chris Demetriou <cgd@broadcom.com>
618 * mips.igen (check_u64): New function which in the future will
619 check whether 64-bit instructions are usable and signal an
620 exception if not. Currently a no-op.
621 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
622 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
623 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
624 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
626 * mips.igen (check_fpu): New function which in the future will
627 check whether FPU instructions are usable and signal an exception
628 if not. Currently a no-op.
629 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
630 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
631 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
632 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
633 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
634 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
635 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
636 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
638 2002-02-27 Chris Demetriou <cgd@broadcom.com>
640 * mips.igen (do_load_left, do_load_right): Move to be immediately
642 (do_store_left, do_store_right): Move to be immediately following
645 2002-02-27 Chris Demetriou <cgd@broadcom.com>
647 * mips.igen (mipsV): New model name. Also, add it to
648 all instructions and functions where it is appropriate.
650 2002-02-18 Chris Demetriou <cgd@broadcom.com>
652 * mips.igen: For all functions and instructions, list model
653 names that support that instruction one per line.
655 2002-02-11 Chris Demetriou <cgd@broadcom.com>
657 * mips.igen: Add some additional comments about supported
658 models, and about which instructions go where.
659 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
660 order as is used in the rest of the file.
662 2002-02-11 Chris Demetriou <cgd@broadcom.com>
664 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
665 indicating that ALU32_END or ALU64_END are there to check
667 (DADD): Likewise, but also remove previous comment about
670 2002-02-10 Chris Demetriou <cgd@broadcom.com>
672 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
673 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
674 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
675 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
676 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
677 fields (i.e., add and move commas) so that they more closely
678 match the MIPS ISA documentation opcode partitioning.
680 2002-02-10 Chris Demetriou <cgd@broadcom.com>
682 * mips.igen (ADDI): Print immediate value.
684 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
685 (SLL): Print "nop" specially, and don't run the code
686 that does the shift for the "nop" case.
688 2001-11-17 Fred Fish <fnf@redhat.com>
690 * sim-main.h (float_operation): Move enum declaration outside
691 of _sim_cpu struct declaration.
693 2001-04-12 Jim Blandy <jimb@redhat.com>
695 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
696 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
698 * sim-main.h (COCIDX): Remove definition; this isn't supported by
699 PENDING_FILL, and you can get the intended effect gracefully by
700 calling PENDING_SCHED directly.
702 2001-02-23 Ben Elliston <bje@redhat.com>
704 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
705 already defined elsewhere.
707 2001-02-19 Ben Elliston <bje@redhat.com>
709 * sim-main.h (sim_monitor): Return an int.
710 * interp.c (sim_monitor): Add return values.
711 (signal_exception): Handle error conditions from sim_monitor.
713 2001-02-08 Ben Elliston <bje@redhat.com>
715 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
716 (store_memory): Likewise, pass cia to sim_core_write*.
718 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
720 On advice from Chris G. Demetriou <cgd@sibyte.com>:
721 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
723 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
725 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
726 * Makefile.in: Don't delete *.igen when cleaning directory.
728 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
730 * m16.igen (break): Call SignalException not sim_engine_halt.
732 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
735 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
737 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
739 * mips.igen (MxC1, DMxC1): Fix printf formatting.
741 2000-05-24 Michael Hayes <mhayes@cygnus.com>
743 * mips.igen (do_dmultx): Fix typo.
745 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
747 * configure: Regenerated to track ../common/aclocal.m4 changes.
749 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
751 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
753 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
755 * sim-main.h (GPR_CLEAR): Define macro.
757 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
759 * interp.c (decode_coproc): Output long using %lx and not %s.
761 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
763 * interp.c (sim_open): Sort & extend dummy memory regions for
764 --board=jmr3904 for eCos.
766 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
768 * configure: Regenerated.
770 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
772 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
773 calls, conditional on the simulator being in verbose mode.
775 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
777 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
778 cache don't get ReservedInstruction traps.
780 1999-11-29 Mark Salter <msalter@cygnus.com>
782 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
783 to clear status bits in sdisr register. This is how the hardware works.
785 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
786 being used by cygmon.
788 1999-11-11 Andrew Haley <aph@cygnus.com>
790 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
793 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
795 * mips.igen (MULT): Correct previous mis-applied patch.
797 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
799 * mips.igen (delayslot32): Handle sequence like
800 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
801 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
802 (MULT): Actually pass the third register...
804 1999-09-03 Mark Salter <msalter@cygnus.com>
806 * interp.c (sim_open): Added more memory aliases for additional
807 hardware being touched by cygmon on jmr3904 board.
809 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
811 * configure: Regenerated to track ../common/aclocal.m4 changes.
813 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
815 * interp.c (sim_store_register): Handle case where client - GDB -
816 specifies that a 4 byte register is 8 bytes in size.
817 (sim_fetch_register): Ditto.
819 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
821 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
822 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
823 (idt_monitor_base): Base address for IDT monitor traps.
824 (pmon_monitor_base): Ditto for PMON.
825 (lsipmon_monitor_base): Ditto for LSI PMON.
826 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
827 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
828 (sim_firmware_command): New function.
829 (mips_option_handler): Call it for OPTION_FIRMWARE.
830 (sim_open): Allocate memory for idt_monitor region. If "--board"
831 option was given, add no monitor by default. Add BREAK hooks only if
832 monitors are also there.
834 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
836 * interp.c (sim_monitor): Flush output before reading input.
838 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
840 * tconfig.in (SIM_HANDLES_LMA): Always define.
842 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
844 From Mark Salter <msalter@cygnus.com>:
845 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
846 (sim_open): Add setup for BSP board.
848 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
850 * mips.igen (MULT, MULTU): Add syntax for two operand version.
851 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
852 them as unimplemented.
854 1999-05-08 Felix Lee <flee@cygnus.com>
856 * configure: Regenerated to track ../common/aclocal.m4 changes.
858 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
860 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
862 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
864 * configure.in: Any mips64vr5*-*-* target should have
865 -DTARGET_ENABLE_FR=1.
866 (default_endian): Any mips64vr*el-*-* target should default to
868 * configure: Re-generate.
870 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
872 * mips.igen (ldl): Extend from _16_, not 32.
874 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
876 * interp.c (sim_store_register): Force registers written to by GDB
877 into an un-interpreted state.
879 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
881 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
882 CPU, start periodic background I/O polls.
883 (tx3904sio_poll): New function: periodic I/O poller.
885 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
887 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
889 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
891 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
894 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
896 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
897 (load_word): Call SIM_CORE_SIGNAL hook on error.
898 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
899 starting. For exception dispatching, pass PC instead of NULL_CIA.
900 (decode_coproc): Use COP0_BADVADDR to store faulting address.
901 * sim-main.h (COP0_BADVADDR): Define.
902 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
903 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
904 (_sim_cpu): Add exc_* fields to store register value snapshots.
905 * mips.igen (*): Replace memory-related SignalException* calls
906 with references to SIM_CORE_SIGNAL hook.
908 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
910 * sim-main.c (*): Minor warning cleanups.
912 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
914 * m16.igen (DADDIU5): Correct type-o.
916 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
918 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
921 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
923 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
925 (interp.o): Add dependency on itable.h
926 (oengine.c, gencode): Delete remaining references.
927 (BUILT_SRC_FROM_GEN): Clean up.
929 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
932 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
933 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
935 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
936 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
937 Drop the "64" qualifier to get the HACK generator working.
938 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
939 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
940 qualifier to get the hack generator working.
941 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
943 (DSLLV): Use do_dsllv.
946 (DSRLV): Use do_dsrlv.
947 (BC1): Move *vr4100 to get the HACK generator working.
948 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
949 get the HACK generator working.
950 (MACC) Rename to get the HACK generator working.
951 (DMACC,MACCS,DMACCS): Add the 64.
953 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
955 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
956 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
958 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
960 * mips/interp.c (DEBUG): Cleanups.
962 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
964 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
965 (tx3904sio_tickle): fflush after a stdout character output.
967 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
969 * interp.c (sim_close): Uninstall modules.
971 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
973 * sim-main.h, interp.c (sim_monitor): Change to global
976 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
978 * configure.in (vr4100): Only include vr4100 instructions in
980 * configure: Re-generate.
981 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
983 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
985 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
986 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
989 * configure.in (sim_default_gen, sim_use_gen): Replace with
991 (--enable-sim-igen): Delete config option. Always using IGEN.
992 * configure: Re-generate.
994 * Makefile.in (gencode): Kill, kill, kill.
997 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
999 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1000 bit mips16 igen simulator.
1001 * configure: Re-generate.
1003 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1004 as part of vr4100 ISA.
1005 * vr.igen: Mark all instructions as 64 bit only.
1007 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1009 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1012 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1014 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1015 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1016 * configure: Re-generate.
1018 * m16.igen (BREAK): Define breakpoint instruction.
1019 (JALX32): Mark instruction as mips16 and not r3900.
1020 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1022 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1024 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1026 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1027 insn as a debug breakpoint.
1029 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1031 (PENDING_SCHED): Clean up trace statement.
1032 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1033 (PENDING_FILL): Delay write by only one cycle.
1034 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1036 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1038 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1040 (pending_tick): Move incrementing of index to FOR statement.
1041 (pending_tick): Only update PENDING_OUT after a write has occured.
1043 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1045 * configure: Re-generate.
1047 * interp.c (sim_engine_run OLD): Delete explicit call to
1048 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1050 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1052 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1053 interrupt level number to match changed SignalExceptionInterrupt
1056 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1058 * interp.c: #include "itable.h" if WITH_IGEN.
1059 (get_insn_name): New function.
1060 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1061 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1063 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1065 * configure: Rebuilt to inhale new common/aclocal.m4.
1067 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1069 * dv-tx3904sio.c: Include sim-assert.h.
1071 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1073 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1074 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1075 Reorganize target-specific sim-hardware checks.
1076 * configure: rebuilt.
1077 * interp.c (sim_open): For tx39 target boards, set
1078 OPERATING_ENVIRONMENT, add tx3904sio devices.
1079 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1080 ROM executables. Install dv-sockser into sim-modules list.
1082 * dv-tx3904irc.c: Compiler warning clean-up.
1083 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1084 frequent hw-trace messages.
1086 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1088 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1090 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1092 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1094 * vr.igen: New file.
1095 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1096 * mips.igen: Define vr4100 model. Include vr.igen.
1097 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1099 * mips.igen (check_mf_hilo): Correct check.
1101 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1103 * sim-main.h (interrupt_event): Add prototype.
1105 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1106 register_ptr, register_value.
1107 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1109 * sim-main.h (tracefh): Make extern.
1111 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1113 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1114 Reduce unnecessarily high timer event frequency.
1115 * dv-tx3904cpu.c: Ditto for interrupt event.
1117 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1119 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1121 (interrupt_event): Made non-static.
1123 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1124 interchange of configuration values for external vs. internal
1127 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1129 * mips.igen (BREAK): Moved code to here for
1130 simulator-reserved break instructions.
1131 * gencode.c (build_instruction): Ditto.
1132 * interp.c (signal_exception): Code moved from here. Non-
1133 reserved instructions now use exception vector, rather
1135 * sim-main.h: Moved magic constants to here.
1137 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1139 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1140 register upon non-zero interrupt event level, clear upon zero
1142 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1143 by passing zero event value.
1144 (*_io_{read,write}_buffer): Endianness fixes.
1145 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1146 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1148 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1149 serial I/O and timer module at base address 0xFFFF0000.
1151 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1153 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1156 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1158 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1160 * configure: Update.
1162 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1164 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1165 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1166 * configure.in: Include tx3904tmr in hw_device list.
1167 * configure: Rebuilt.
1168 * interp.c (sim_open): Instantiate three timer instances.
1169 Fix address typo of tx3904irc instance.
1171 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1173 * interp.c (signal_exception): SystemCall exception now uses
1174 the exception vector.
1176 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1178 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1181 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1183 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1185 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1187 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1189 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1190 sim-main.h. Declare a struct hw_descriptor instead of struct
1191 hw_device_descriptor.
1193 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1195 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1196 right bits and then re-align left hand bytes to correct byte
1197 lanes. Fix incorrect computation in do_store_left when loading
1198 bytes from second word.
1200 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1202 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1203 * interp.c (sim_open): Only create a device tree when HW is
1206 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1207 * interp.c (signal_exception): Ditto.
1209 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1211 * gencode.c: Mark BEGEZALL as LIKELY.
1213 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1215 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1216 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1218 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1220 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1221 modules. Recognize TX39 target with "mips*tx39" pattern.
1222 * configure: Rebuilt.
1223 * sim-main.h (*): Added many macros defining bits in
1224 TX39 control registers.
1225 (SignalInterrupt): Send actual PC instead of NULL.
1226 (SignalNMIReset): New exception type.
1227 * interp.c (board): New variable for future use to identify
1228 a particular board being simulated.
1229 (mips_option_handler,mips_options): Added "--board" option.
1230 (interrupt_event): Send actual PC.
1231 (sim_open): Make memory layout conditional on board setting.
1232 (signal_exception): Initial implementation of hardware interrupt
1233 handling. Accept another break instruction variant for simulator
1235 (decode_coproc): Implement RFE instruction for TX39.
1236 (mips.igen): Decode RFE instruction as such.
1237 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1238 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1239 bbegin to implement memory map.
1240 * dv-tx3904cpu.c: New file.
1241 * dv-tx3904irc.c: New file.
1243 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1245 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1247 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1249 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1250 with calls to check_div_hilo.
1252 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1254 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1255 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1256 Add special r3900 version of do_mult_hilo.
1257 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1258 with calls to check_mult_hilo.
1259 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1260 with calls to check_div_hilo.
1262 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1264 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1265 Document a replacement.
1267 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1269 * interp.c (sim_monitor): Make mon_printf work.
1271 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1273 * sim-main.h (INSN_NAME): New arg `cpu'.
1275 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1277 * configure: Regenerated to track ../common/aclocal.m4 changes.
1279 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1281 * configure: Regenerated to track ../common/aclocal.m4 changes.
1284 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1286 * acconfig.h: New file.
1287 * configure.in: Reverted change of Apr 24; use sinclude again.
1289 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1291 * configure: Regenerated to track ../common/aclocal.m4 changes.
1294 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1296 * configure.in: Don't call sinclude.
1298 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1300 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1302 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1304 * mips.igen (ERET): Implement.
1306 * interp.c (decode_coproc): Return sign-extended EPC.
1308 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1310 * interp.c (signal_exception): Do not ignore Trap.
1311 (signal_exception): On TRAP, restart at exception address.
1312 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1313 (signal_exception): Update.
1314 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1315 so that TRAP instructions are caught.
1317 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1319 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1320 contains HI/LO access history.
1321 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1322 (HIACCESS, LOACCESS): Delete, replace with
1323 (HIHISTORY, LOHISTORY): New macros.
1324 (CHECKHILO): Delete all, moved to mips.igen
1326 * gencode.c (build_instruction): Do not generate checks for
1327 correct HI/LO register usage.
1329 * interp.c (old_engine_run): Delete checks for correct HI/LO
1332 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1333 check_mf_cycles): New functions.
1334 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1335 do_divu, domultx, do_mult, do_multu): Use.
1337 * tx.igen ("madd", "maddu"): Use.
1339 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1341 * mips.igen (DSRAV): Use function do_dsrav.
1342 (SRAV): Use new function do_srav.
1344 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1345 (B): Sign extend 11 bit immediate.
1346 (EXT-B*): Shift 16 bit immediate left by 1.
1347 (ADDIU*): Don't sign extend immediate value.
1349 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1351 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1353 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1356 * mips.igen (delayslot32, nullify_next_insn): New functions.
1357 (m16.igen): Always include.
1358 (do_*): Add more tracing.
1360 * m16.igen (delayslot16): Add NIA argument, could be called by a
1361 32 bit MIPS16 instruction.
1363 * interp.c (ifetch16): Move function from here.
1364 * sim-main.c (ifetch16): To here.
1366 * sim-main.c (ifetch16, ifetch32): Update to match current
1367 implementations of LH, LW.
1368 (signal_exception): Don't print out incorrect hex value of illegal
1371 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1373 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1376 * m16.igen: Implement MIPS16 instructions.
1378 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1379 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1380 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1381 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1382 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1383 bodies of corresponding code from 32 bit insn to these. Also used
1384 by MIPS16 versions of functions.
1386 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1387 (IMEM16): Drop NR argument from macro.
1389 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1391 * Makefile.in (SIM_OBJS): Add sim-main.o.
1393 * sim-main.h (address_translation, load_memory, store_memory,
1394 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1396 (pr_addr, pr_uword64): Declare.
1397 (sim-main.c): Include when H_REVEALS_MODULE_P.
1399 * interp.c (address_translation, load_memory, store_memory,
1400 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1402 * sim-main.c: To here. Fix compilation problems.
1404 * configure.in: Enable inlining.
1405 * configure: Re-config.
1407 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1409 * configure: Regenerated to track ../common/aclocal.m4 changes.
1411 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1413 * mips.igen: Include tx.igen.
1414 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1415 * tx.igen: New file, contains MADD and MADDU.
1417 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1418 the hardwired constant `7'.
1419 (store_memory): Ditto.
1420 (LOADDRMASK): Move definition to sim-main.h.
1422 mips.igen (MTC0): Enable for r3900.
1425 mips.igen (do_load_byte): Delete.
1426 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1427 do_store_right): New functions.
1428 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1430 configure.in: Let the tx39 use igen again.
1433 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1435 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1436 not an address sized quantity. Return zero for cache sizes.
1438 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1440 * mips.igen (r3900): r3900 does not support 64 bit integer
1443 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1445 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1447 * configure : Rebuild.
1449 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1451 * configure: Regenerated to track ../common/aclocal.m4 changes.
1453 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1455 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1457 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1459 * configure: Regenerated to track ../common/aclocal.m4 changes.
1460 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1462 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1464 * configure: Regenerated to track ../common/aclocal.m4 changes.
1466 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1468 * interp.c (Max, Min): Comment out functions. Not yet used.
1470 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1472 * configure: Regenerated to track ../common/aclocal.m4 changes.
1474 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1476 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1477 configurable settings for stand-alone simulator.
1479 * configure.in: Added X11 search, just in case.
1481 * configure: Regenerated.
1483 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1485 * interp.c (sim_write, sim_read, load_memory, store_memory):
1486 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1488 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1490 * sim-main.h (GETFCC): Return an unsigned value.
1492 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1494 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1495 (DADD): Result destination is RD not RT.
1497 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1499 * sim-main.h (HIACCESS, LOACCESS): Always define.
1501 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1503 * interp.c (sim_info): Delete.
1505 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1507 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1508 (mips_option_handler): New argument `cpu'.
1509 (sim_open): Update call to sim_add_option_table.
1511 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1513 * mips.igen (CxC1): Add tracing.
1515 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1517 * sim-main.h (Max, Min): Declare.
1519 * interp.c (Max, Min): New functions.
1521 * mips.igen (BC1): Add tracing.
1523 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1525 * interp.c Added memory map for stack in vr4100
1527 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1529 * interp.c (load_memory): Add missing "break"'s.
1531 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1533 * interp.c (sim_store_register, sim_fetch_register): Pass in
1534 length parameter. Return -1.
1536 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1538 * interp.c: Added hardware init hook, fixed warnings.
1540 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1542 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1544 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1546 * interp.c (ifetch16): New function.
1548 * sim-main.h (IMEM32): Rename IMEM.
1549 (IMEM16_IMMED): Define.
1551 (DELAY_SLOT): Update.
1553 * m16run.c (sim_engine_run): New file.
1555 * m16.igen: All instructions except LB.
1556 (LB): Call do_load_byte.
1557 * mips.igen (do_load_byte): New function.
1558 (LB): Call do_load_byte.
1560 * mips.igen: Move spec for insn bit size and high bit from here.
1561 * Makefile.in (tmp-igen, tmp-m16): To here.
1563 * m16.dc: New file, decode mips16 instructions.
1565 * Makefile.in (SIM_NO_ALL): Define.
1566 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1568 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1570 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1571 point unit to 32 bit registers.
1572 * configure: Re-generate.
1574 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1576 * configure.in (sim_use_gen): Make IGEN the default simulator
1577 generator for generic 32 and 64 bit mips targets.
1578 * configure: Re-generate.
1580 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1582 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1585 * interp.c (sim_fetch_register, sim_store_register): Read/write
1586 FGR from correct location.
1587 (sim_open): Set size of FGR's according to
1588 WITH_TARGET_FLOATING_POINT_BITSIZE.
1590 * sim-main.h (FGR): Store floating point registers in a separate
1593 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1595 * configure: Regenerated to track ../common/aclocal.m4 changes.
1597 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1599 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1601 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1603 * interp.c (pending_tick): New function. Deliver pending writes.
1605 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1606 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1607 it can handle mixed sized quantites and single bits.
1609 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1611 * interp.c (oengine.h): Do not include when building with IGEN.
1612 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1613 (sim_info): Ditto for PROCESSOR_64BIT.
1614 (sim_monitor): Replace ut_reg with unsigned_word.
1615 (*): Ditto for t_reg.
1616 (LOADDRMASK): Define.
1617 (sim_open): Remove defunct check that host FP is IEEE compliant,
1618 using software to emulate floating point.
1619 (value_fpr, ...): Always compile, was conditional on HASFPU.
1621 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1623 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1626 * interp.c (SD, CPU): Define.
1627 (mips_option_handler): Set flags in each CPU.
1628 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1629 (sim_close): Do not clear STATE, deleted anyway.
1630 (sim_write, sim_read): Assume CPU zero's vm should be used for
1632 (sim_create_inferior): Set the PC for all processors.
1633 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1635 (mips16_entry): Pass correct nr of args to store_word, load_word.
1636 (ColdReset): Cold reset all cpu's.
1637 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1638 (sim_monitor, load_memory, store_memory, signal_exception): Use
1639 `CPU' instead of STATE_CPU.
1642 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1645 * sim-main.h (signal_exception): Add sim_cpu arg.
1646 (SignalException*): Pass both SD and CPU to signal_exception.
1647 * interp.c (signal_exception): Update.
1649 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1651 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1652 address_translation): Ditto
1653 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1655 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1657 * configure: Regenerated to track ../common/aclocal.m4 changes.
1659 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1661 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1663 * mips.igen (model): Map processor names onto BFD name.
1665 * sim-main.h (CPU_CIA): Delete.
1666 (SET_CIA, GET_CIA): Define
1668 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1670 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1673 * configure.in (default_endian): Configure a big-endian simulator
1675 * configure: Re-generate.
1677 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1679 * configure: Regenerated to track ../common/aclocal.m4 changes.
1681 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1683 * interp.c (sim_monitor): Handle Densan monitor outbyte
1684 and inbyte functions.
1686 1997-12-29 Felix Lee <flee@cygnus.com>
1688 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1690 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1692 * Makefile.in (tmp-igen): Arrange for $zero to always be
1693 reset to zero after every instruction.
1695 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1697 * configure: Regenerated to track ../common/aclocal.m4 changes.
1700 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1702 * mips.igen (MSUB): Fix to work like MADD.
1703 * gencode.c (MSUB): Similarly.
1705 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1707 * configure: Regenerated to track ../common/aclocal.m4 changes.
1709 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1711 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1713 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1715 * sim-main.h (sim-fpu.h): Include.
1717 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1718 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1719 using host independant sim_fpu module.
1721 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1723 * interp.c (signal_exception): Report internal errors with SIGABRT
1726 * sim-main.h (C0_CONFIG): New register.
1727 (signal.h): No longer include.
1729 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1731 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1733 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1735 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1737 * mips.igen: Tag vr5000 instructions.
1738 (ANDI): Was missing mipsIV model, fix assembler syntax.
1739 (do_c_cond_fmt): New function.
1740 (C.cond.fmt): Handle mips I-III which do not support CC field
1742 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1743 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1745 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1746 vr5000 which saves LO in a GPR separatly.
1748 * configure.in (enable-sim-igen): For vr5000, select vr5000
1749 specific instructions.
1750 * configure: Re-generate.
1752 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1754 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1756 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1757 fmt_uninterpreted_64 bit cases to switch. Convert to
1760 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1762 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1763 as specified in IV3.2 spec.
1764 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1766 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1768 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1769 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1770 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1771 PENDING_FILL versions of instructions. Simplify.
1773 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1775 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1777 (MTHI, MFHI): Disable code checking HI-LO.
1779 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1781 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1783 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1785 * gencode.c (build_mips16_operands): Replace IPC with cia.
1787 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1788 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1790 (UndefinedResult): Replace function with macro/function
1792 (sim_engine_run): Don't save PC in IPC.
1794 * sim-main.h (IPC): Delete.
1797 * interp.c (signal_exception, store_word, load_word,
1798 address_translation, load_memory, store_memory, cache_op,
1799 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1800 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1801 current instruction address - cia - argument.
1802 (sim_read, sim_write): Call address_translation directly.
1803 (sim_engine_run): Rename variable vaddr to cia.
1804 (signal_exception): Pass cia to sim_monitor
1806 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1807 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1808 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1810 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1811 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1814 * interp.c (signal_exception): Pass restart address to
1817 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1818 idecode.o): Add dependency.
1820 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1822 (DELAY_SLOT): Update NIA not PC with branch address.
1823 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1825 * mips.igen: Use CIA not PC in branch calculations.
1826 (illegal): Call SignalException.
1827 (BEQ, ADDIU): Fix assembler.
1829 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1831 * m16.igen (JALX): Was missing.
1833 * configure.in (enable-sim-igen): New configuration option.
1834 * configure: Re-generate.
1836 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1838 * interp.c (load_memory, store_memory): Delete parameter RAW.
1839 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1840 bypassing {load,store}_memory.
1842 * sim-main.h (ByteSwapMem): Delete definition.
1844 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1846 * interp.c (sim_do_command, sim_commands): Delete mips specific
1847 commands. Handled by module sim-options.
1849 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1850 (WITH_MODULO_MEMORY): Define.
1852 * interp.c (sim_info): Delete code printing memory size.
1854 * interp.c (mips_size): Nee sim_size, delete function.
1856 (monitor, monitor_base, monitor_size): Delete global variables.
1857 (sim_open, sim_close): Delete code creating monitor and other
1858 memory regions. Use sim-memopts module, via sim_do_commandf, to
1859 manage memory regions.
1860 (load_memory, store_memory): Use sim-core for memory model.
1862 * interp.c (address_translation): Delete all memory map code
1863 except line forcing 32 bit addresses.
1865 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1867 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1870 * interp.c (logfh, logfile): Delete globals.
1871 (sim_open, sim_close): Delete code opening & closing log file.
1872 (mips_option_handler): Delete -l and -n options.
1873 (OPTION mips_options): Ditto.
1875 * interp.c (OPTION mips_options): Rename option trace to dinero.
1876 (mips_option_handler): Update.
1878 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1880 * interp.c (fetch_str): New function.
1881 (sim_monitor): Rewrite using sim_read & sim_write.
1882 (sim_open): Check magic number.
1883 (sim_open): Write monitor vectors into memory using sim_write.
1884 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1885 (sim_read, sim_write): Simplify - transfer data one byte at a
1887 (load_memory, store_memory): Clarify meaning of parameter RAW.
1889 * sim-main.h (isHOST): Defete definition.
1890 (isTARGET): Mark as depreciated.
1891 (address_translation): Delete parameter HOST.
1893 * interp.c (address_translation): Delete parameter HOST.
1895 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1899 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1900 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1902 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1904 * mips.igen: Add model filter field to records.
1906 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1908 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1910 interp.c (sim_engine_run): Do not compile function sim_engine_run
1911 when WITH_IGEN == 1.
1913 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1914 target architecture.
1916 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1917 igen. Replace with configuration variables sim_igen_flags /
1920 * m16.igen: New file. Copy mips16 insns here.
1921 * mips.igen: From here.
1923 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1925 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1927 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1929 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1931 * gencode.c (build_instruction): Follow sim_write's lead in using
1932 BigEndianMem instead of !ByteSwapMem.
1934 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1936 * configure.in (sim_gen): Dependent on target, select type of
1937 generator. Always select old style generator.
1939 configure: Re-generate.
1941 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1943 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1944 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1945 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1946 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1947 SIM_@sim_gen@_*, set by autoconf.
1949 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1951 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1953 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1954 CURRENT_FLOATING_POINT instead.
1956 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1957 (address_translation): Raise exception InstructionFetch when
1958 translation fails and isINSTRUCTION.
1960 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1961 sim_engine_run): Change type of of vaddr and paddr to
1963 (address_translation, prefetch, load_memory, store_memory,
1964 cache_op): Change type of vAddr and pAddr to address_word.
1966 * gencode.c (build_instruction): Change type of vaddr and paddr to
1969 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1971 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1972 macro to obtain result of ALU op.
1974 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1976 * interp.c (sim_info): Call profile_print.
1978 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1980 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1982 * sim-main.h (WITH_PROFILE): Do not define, defined in
1983 common/sim-config.h. Use sim-profile module.
1984 (simPROFILE): Delete defintion.
1986 * interp.c (PROFILE): Delete definition.
1987 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1988 (sim_close): Delete code writing profile histogram.
1989 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1991 (sim_engine_run): Delete code profiling the PC.
1993 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1995 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1997 * interp.c (sim_monitor): Make register pointers of type
2000 * sim-main.h: Make registers of type unsigned_word not
2003 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2005 * interp.c (sync_operation): Rename from SyncOperation, make
2006 global, add SD argument.
2007 (prefetch): Rename from Prefetch, make global, add SD argument.
2008 (decode_coproc): Make global.
2010 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2012 * gencode.c (build_instruction): Generate DecodeCoproc not
2013 decode_coproc calls.
2015 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2016 (SizeFGR): Move to sim-main.h
2017 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2018 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2019 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2021 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2022 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2023 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2024 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2025 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2026 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2028 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2030 (sim-alu.h): Include.
2031 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2032 (sim_cia): Typedef to instruction_address.
2034 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2036 * Makefile.in (interp.o): Rename generated file engine.c to
2041 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2043 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2045 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2047 * gencode.c (build_instruction): For "FPSQRT", output correct
2048 number of arguments to Recip.
2050 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2052 * Makefile.in (interp.o): Depends on sim-main.h
2054 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2056 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2057 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2058 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2059 STATE, DSSTATE): Define
2060 (GPR, FGRIDX, ..): Define.
2062 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2063 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2064 (GPR, FGRIDX, ...): Delete macros.
2066 * interp.c: Update names to match defines from sim-main.h
2068 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2070 * interp.c (sim_monitor): Add SD argument.
2071 (sim_warning): Delete. Replace calls with calls to
2073 (sim_error): Delete. Replace calls with sim_io_error.
2074 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2075 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2076 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2078 (mips_size): Rename from sim_size. Add SD argument.
2080 * interp.c (simulator): Delete global variable.
2081 (callback): Delete global variable.
2082 (mips_option_handler, sim_open, sim_write, sim_read,
2083 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2084 sim_size,sim_monitor): Use sim_io_* not callback->*.
2085 (sim_open): ZALLOC simulator struct.
2086 (PROFILE): Do not define.
2088 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2090 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2091 support.h with corresponding code.
2093 * sim-main.h (word64, uword64), support.h: Move definition to
2095 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2098 * Makefile.in: Update dependencies
2099 * interp.c: Do not include.
2101 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2103 * interp.c (address_translation, load_memory, store_memory,
2104 cache_op): Rename to from AddressTranslation et.al., make global,
2107 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2110 * interp.c (SignalException): Rename to signal_exception, make
2113 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2115 * sim-main.h (SignalException, SignalExceptionInterrupt,
2116 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2117 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2118 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2121 * interp.c, support.h: Use.
2123 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2125 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2126 to value_fpr / store_fpr. Add SD argument.
2127 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2128 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2130 * sim-main.h (ValueFPR, StoreFPR): Define.
2132 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2134 * interp.c (sim_engine_run): Check consistency between configure
2135 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2138 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2139 (mips_fpu): Configure WITH_FLOATING_POINT.
2140 (mips_endian): Configure WITH_TARGET_ENDIAN.
2141 * configure: Update.
2143 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2145 * configure: Regenerated to track ../common/aclocal.m4 changes.
2147 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2149 * configure: Regenerated.
2151 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2153 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2155 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2157 * gencode.c (print_igen_insn_models): Assume certain architectures
2158 include all mips* instructions.
2159 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2162 * Makefile.in (tmp.igen): Add target. Generate igen input from
2165 * gencode.c (FEATURE_IGEN): Define.
2166 (main): Add --igen option. Generate output in igen format.
2167 (process_instructions): Format output according to igen option.
2168 (print_igen_insn_format): New function.
2169 (print_igen_insn_models): New function.
2170 (process_instructions): Only issue warnings and ignore
2171 instructions when no FEATURE_IGEN.
2173 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2175 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2178 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180 * configure: Regenerated to track ../common/aclocal.m4 changes.
2182 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2185 SIM_RESERVED_BITS): Delete, moved to common.
2186 (SIM_EXTRA_CFLAGS): Update.
2188 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2190 * configure.in: Configure non-strict memory alignment.
2191 * configure: Regenerated to track ../common/aclocal.m4 changes.
2193 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2195 * configure: Regenerated to track ../common/aclocal.m4 changes.
2197 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2199 * gencode.c (SDBBP,DERET): Added (3900) insns.
2200 (RFE): Turn on for 3900.
2201 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2202 (dsstate): Made global.
2203 (SUBTARGET_R3900): Added.
2204 (CANCELDELAYSLOT): New.
2205 (SignalException): Ignore SystemCall rather than ignore and
2206 terminate. Add DebugBreakPoint handling.
2207 (decode_coproc): New insns RFE, DERET; and new registers Debug
2208 and DEPC protected by SUBTARGET_R3900.
2209 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2211 * Makefile.in,configure.in: Add mips subtarget option.
2212 * configure: Update.
2214 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2216 * gencode.c: Add r3900 (tx39).
2219 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2221 * gencode.c (build_instruction): Don't need to subtract 4 for
2224 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2226 * interp.c: Correct some HASFPU problems.
2228 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2230 * configure: Regenerated to track ../common/aclocal.m4 changes.
2232 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2234 * interp.c (mips_options): Fix samples option short form, should
2237 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2239 * interp.c (sim_info): Enable info code. Was just returning.
2241 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2243 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2246 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2248 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2250 (build_instruction): Ditto for LL.
2252 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2254 * configure: Regenerated to track ../common/aclocal.m4 changes.
2256 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2258 * configure: Regenerated to track ../common/aclocal.m4 changes.
2261 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2263 * interp.c (sim_open): Add call to sim_analyze_program, update
2266 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2268 * interp.c (sim_kill): Delete.
2269 (sim_create_inferior): Add ABFD argument. Set PC from same.
2270 (sim_load): Move code initializing trap handlers from here.
2271 (sim_open): To here.
2272 (sim_load): Delete, use sim-hload.c.
2274 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2276 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2278 * configure: Regenerated to track ../common/aclocal.m4 changes.
2281 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2283 * interp.c (sim_open): Add ABFD argument.
2284 (sim_load): Move call to sim_config from here.
2285 (sim_open): To here. Check return status.
2287 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2289 * gencode.c (build_instruction): Two arg MADD should
2290 not assign result to $0.
2292 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2294 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2295 * sim/mips/configure.in: Regenerate.
2297 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2299 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2300 signed8, unsigned8 et.al. types.
2302 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2303 hosts when selecting subreg.
2305 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2307 * interp.c (sim_engine_run): Reset the ZERO register to zero
2308 regardless of FEATURE_WARN_ZERO.
2309 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2311 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2313 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2314 (SignalException): For BreakPoints ignore any mode bits and just
2316 (SignalException): Always set the CAUSE register.
2318 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2320 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2321 exception has been taken.
2323 * interp.c: Implement the ERET and mt/f sr instructions.
2325 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2327 * interp.c (SignalException): Don't bother restarting an
2330 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2332 * interp.c (SignalException): Really take an interrupt.
2333 (interrupt_event): Only deliver interrupts when enabled.
2335 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2337 * interp.c (sim_info): Only print info when verbose.
2338 (sim_info) Use sim_io_printf for output.
2340 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2342 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2345 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2347 * interp.c (sim_do_command): Check for common commands if a
2348 simulator specific command fails.
2350 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2352 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2353 and simBE when DEBUG is defined.
2355 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2357 * interp.c (interrupt_event): New function. Pass exception event
2358 onto exception handler.
2360 * configure.in: Check for stdlib.h.
2361 * configure: Regenerate.
2363 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2364 variable declaration.
2365 (build_instruction): Initialize memval1.
2366 (build_instruction): Add UNUSED attribute to byte, bigend,
2368 (build_operands): Ditto.
2370 * interp.c: Fix GCC warnings.
2371 (sim_get_quit_code): Delete.
2373 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2374 * Makefile.in: Ditto.
2375 * configure: Re-generate.
2377 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2379 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2381 * interp.c (mips_option_handler): New function parse argumes using
2383 (myname): Replace with STATE_MY_NAME.
2384 (sim_open): Delete check for host endianness - performed by
2386 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2387 (sim_open): Move much of the initialization from here.
2388 (sim_load): To here. After the image has been loaded and
2390 (sim_open): Move ColdReset from here.
2391 (sim_create_inferior): To here.
2392 (sim_open): Make FP check less dependant on host endianness.
2394 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2396 * interp.c (sim_set_callbacks): Delete.
2398 * interp.c (membank, membank_base, membank_size): Replace with
2399 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2400 (sim_open): Remove call to callback->init. gdb/run do this.
2404 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2406 * interp.c (big_endian_p): Delete, replaced by
2407 current_target_byte_order.
2409 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2411 * interp.c (host_read_long, host_read_word, host_swap_word,
2412 host_swap_long): Delete. Using common sim-endian.
2413 (sim_fetch_register, sim_store_register): Use H2T.
2414 (pipeline_ticks): Delete. Handled by sim-events.
2416 (sim_engine_run): Update.
2418 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2420 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2422 (SignalException): To here. Signal using sim_engine_halt.
2423 (sim_stop_reason): Delete, moved to common.
2425 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2427 * interp.c (sim_open): Add callback argument.
2428 (sim_set_callbacks): Delete SIM_DESC argument.
2431 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2433 * Makefile.in (SIM_OBJS): Add common modules.
2435 * interp.c (sim_set_callbacks): Also set SD callback.
2436 (set_endianness, xfer_*, swap_*): Delete.
2437 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2438 Change to functions using sim-endian macros.
2439 (control_c, sim_stop): Delete, use common version.
2440 (simulate): Convert into.
2441 (sim_engine_run): This function.
2442 (sim_resume): Delete.
2444 * interp.c (simulation): New variable - the simulator object.
2445 (sim_kind): Delete global - merged into simulation.
2446 (sim_load): Cleanup. Move PC assignment from here.
2447 (sim_create_inferior): To here.
2449 * sim-main.h: New file.
2450 * interp.c (sim-main.h): Include.
2452 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2454 * configure: Regenerated to track ../common/aclocal.m4 changes.
2456 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2458 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2460 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2462 * gencode.c (build_instruction): DIV instructions: check
2463 for division by zero and integer overflow before using
2464 host's division operation.
2466 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2468 * Makefile.in (SIM_OBJS): Add sim-load.o.
2469 * interp.c: #include bfd.h.
2470 (target_byte_order): Delete.
2471 (sim_kind, myname, big_endian_p): New static locals.
2472 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2473 after argument parsing. Recognize -E arg, set endianness accordingly.
2474 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2475 load file into simulator. Set PC from bfd.
2476 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2477 (set_endianness): Use big_endian_p instead of target_byte_order.
2479 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2481 * interp.c (sim_size): Delete prototype - conflicts with
2482 definition in remote-sim.h. Correct definition.
2484 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2486 * configure: Regenerated to track ../common/aclocal.m4 changes.
2489 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2491 * interp.c (sim_open): New arg `kind'.
2493 * configure: Regenerated to track ../common/aclocal.m4 changes.
2495 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2497 * configure: Regenerated to track ../common/aclocal.m4 changes.
2499 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2501 * interp.c (sim_open): Set optind to 0 before calling getopt.
2503 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2505 * configure: Regenerated to track ../common/aclocal.m4 changes.
2507 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2509 * interp.c : Replace uses of pr_addr with pr_uword64
2510 where the bit length is always 64 independent of SIM_ADDR.
2511 (pr_uword64) : added.
2513 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2515 * configure: Re-generate.
2517 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2519 * configure: Regenerate to track ../common/aclocal.m4 changes.
2521 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2523 * interp.c (sim_open): New SIM_DESC result. Argument is now
2525 (other sim_*): New SIM_DESC argument.
2527 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2529 * interp.c: Fix printing of addresses for non-64-bit targets.
2530 (pr_addr): Add function to print address based on size.
2532 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2534 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2536 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2538 * gencode.c (build_mips16_operands): Correct computation of base
2539 address for extended PC relative instruction.
2541 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2543 * interp.c (mips16_entry): Add support for floating point cases.
2544 (SignalException): Pass floating point cases to mips16_entry.
2545 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2547 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2549 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2550 and then set the state to fmt_uninterpreted.
2551 (COP_SW): Temporarily set the state to fmt_word while calling
2554 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2556 * gencode.c (build_instruction): The high order may be set in the
2557 comparison flags at any ISA level, not just ISA 4.
2559 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2561 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2562 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2563 * configure.in: sinclude ../common/aclocal.m4.
2564 * configure: Regenerated.
2566 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2568 * configure: Rebuild after change to aclocal.m4.
2570 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2572 * configure configure.in Makefile.in: Update to new configure
2573 scheme which is more compatible with WinGDB builds.
2574 * configure.in: Improve comment on how to run autoconf.
2575 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2576 * Makefile.in: Use autoconf substitution to install common
2579 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2581 * gencode.c (build_instruction): Use BigEndianCPU instead of
2584 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2586 * interp.c (sim_monitor): Make output to stdout visible in
2587 wingdb's I/O log window.
2589 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2591 * support.h: Undo previous change to SIGTRAP
2594 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2596 * interp.c (store_word, load_word): New static functions.
2597 (mips16_entry): New static function.
2598 (SignalException): Look for mips16 entry and exit instructions.
2599 (simulate): Use the correct index when setting fpr_state after
2600 doing a pending move.
2602 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2604 * interp.c: Fix byte-swapping code throughout to work on
2605 both little- and big-endian hosts.
2607 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2609 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2610 with gdb/config/i386/xm-windows.h.
2612 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2614 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2615 that messes up arithmetic shifts.
2617 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2619 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2620 SIGTRAP and SIGQUIT for _WIN32.
2622 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2624 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2625 force a 64 bit multiplication.
2626 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2627 destination register is 0, since that is the default mips16 nop
2630 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2632 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2633 (build_endian_shift): Don't check proc64.
2634 (build_instruction): Always set memval to uword64. Cast op2 to
2635 uword64 when shifting it left in memory instructions. Always use
2636 the same code for stores--don't special case proc64.
2638 * gencode.c (build_mips16_operands): Fix base PC value for PC
2640 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2642 * interp.c (simJALDELAYSLOT): Define.
2643 (JALDELAYSLOT): Define.
2644 (INDELAYSLOT, INJALDELAYSLOT): Define.
2645 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2647 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2649 * interp.c (sim_open): add flush_cache as a PMON routine
2650 (sim_monitor): handle flush_cache by ignoring it
2652 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2654 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2656 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2657 (BigEndianMem): Rename to ByteSwapMem and change sense.
2658 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2659 BigEndianMem references to !ByteSwapMem.
2660 (set_endianness): New function, with prototype.
2661 (sim_open): Call set_endianness.
2662 (sim_info): Use simBE instead of BigEndianMem.
2663 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2664 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2665 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2666 ifdefs, keeping the prototype declaration.
2667 (swap_word): Rewrite correctly.
2668 (ColdReset): Delete references to CONFIG. Delete endianness related
2669 code; moved to set_endianness.
2671 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2673 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2674 * interp.c (CHECKHILO): Define away.
2675 (simSIGINT): New macro.
2676 (membank_size): Increase from 1MB to 2MB.
2677 (control_c): New function.
2678 (sim_resume): Rename parameter signal to signal_number. Add local
2679 variable prev. Call signal before and after simulate.
2680 (sim_stop_reason): Add simSIGINT support.
2681 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2683 (sim_warning): Delete call to SignalException. Do call printf_filtered
2685 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2686 a call to sim_warning.
2688 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2690 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2691 16 bit instructions.
2693 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2695 Add support for mips16 (16 bit MIPS implementation):
2696 * gencode.c (inst_type): Add mips16 instruction encoding types.
2697 (GETDATASIZEINSN): Define.
2698 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2699 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2701 (MIPS16_DECODE): New table, for mips16 instructions.
2702 (bitmap_val): New static function.
2703 (struct mips16_op): Define.
2704 (mips16_op_table): New table, for mips16 operands.
2705 (build_mips16_operands): New static function.
2706 (process_instructions): If PC is odd, decode a mips16
2707 instruction. Break out instruction handling into new
2708 build_instruction function.
2709 (build_instruction): New static function, broken out of
2710 process_instructions. Check modifiers rather than flags for SHIFT
2711 bit count and m[ft]{hi,lo} direction.
2712 (usage): Pass program name to fprintf.
2713 (main): Remove unused variable this_option_optind. Change
2714 ``*loptarg++'' to ``loptarg++''.
2715 (my_strtoul): Parenthesize && within ||.
2716 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2717 (simulate): If PC is odd, fetch a 16 bit instruction, and
2718 increment PC by 2 rather than 4.
2719 * configure.in: Add case for mips16*-*-*.
2720 * configure: Rebuild.
2722 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2724 * interp.c: Allow -t to enable tracing in standalone simulator.
2725 Fix garbage output in trace file and error messages.
2727 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2729 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2730 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2731 * configure.in: Simplify using macros in ../common/aclocal.m4.
2732 * configure: Regenerated.
2733 * tconfig.in: New file.
2735 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2737 * interp.c: Fix bugs in 64-bit port.
2738 Use ansi function declarations for msvc compiler.
2739 Initialize and test file pointer in trace code.
2740 Prevent duplicate definition of LAST_EMED_REGNUM.
2742 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2744 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2746 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2748 * interp.c (SignalException): Check for explicit terminating
2750 * gencode.c: Pass instruction value through SignalException()
2751 calls for Trap, Breakpoint and Syscall.
2753 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2755 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2756 only used on those hosts that provide it.
2757 * configure.in: Add sqrt() to list of functions to be checked for.
2758 * config.in: Re-generated.
2759 * configure: Re-generated.
2761 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2763 * gencode.c (process_instructions): Call build_endian_shift when
2764 expanding STORE RIGHT, to fix swr.
2765 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2766 clear the high bits.
2767 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2768 Fix float to int conversions to produce signed values.
2770 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2772 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2773 (process_instructions): Correct handling of nor instruction.
2774 Correct shift count for 32 bit shift instructions. Correct sign
2775 extension for arithmetic shifts to not shift the number of bits in
2776 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2777 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2779 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2780 It's OK to have a mult follow a mult. What's not OK is to have a
2781 mult follow an mfhi.
2782 (Convert): Comment out incorrect rounding code.
2784 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2786 * interp.c (sim_monitor): Improved monitor printf
2787 simulation. Tidied up simulator warnings, and added "--log" option
2788 for directing warning message output.
2789 * gencode.c: Use sim_warning() rather than WARNING macro.
2791 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2793 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2794 getopt1.o, rather than on gencode.c. Link objects together.
2795 Don't link against -liberty.
2796 (gencode.o, getopt.o, getopt1.o): New targets.
2797 * gencode.c: Include <ctype.h> and "ansidecl.h".
2798 (AND): Undefine after including "ansidecl.h".
2799 (ULONG_MAX): Define if not defined.
2800 (OP_*): Don't define macros; now defined in opcode/mips.h.
2801 (main): Call my_strtoul rather than strtoul.
2802 (my_strtoul): New static function.
2804 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2806 * gencode.c (process_instructions): Generate word64 and uword64
2807 instead of `long long' and `unsigned long long' data types.
2808 * interp.c: #include sysdep.h to get signals, and define default
2810 * (Convert): Work around for Visual-C++ compiler bug with type
2812 * support.h: Make things compile under Visual-C++ by using
2813 __int64 instead of `long long'. Change many refs to long long
2814 into word64/uword64 typedefs.
2816 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2818 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2819 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2821 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2822 (AC_PROG_INSTALL): Added.
2823 (AC_PROG_CC): Moved to before configure.host call.
2824 * configure: Rebuilt.
2826 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2828 * configure.in: Define @SIMCONF@ depending on mips target.
2829 * configure: Rebuild.
2830 * Makefile.in (run): Add @SIMCONF@ to control simulator
2832 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2833 * interp.c: Remove some debugging, provide more detailed error
2834 messages, update memory accesses to use LOADDRMASK.
2836 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2838 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2839 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2841 * configure: Rebuild.
2842 * config.in: New file, generated by autoheader.
2843 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2844 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2845 HAVE_ANINT and HAVE_AINT, as appropriate.
2846 * Makefile.in (run): Use @LIBS@ rather than -lm.
2847 (interp.o): Depend upon config.h.
2848 (Makefile): Just rebuild Makefile.
2849 (clean): Remove stamp-h.
2850 (mostlyclean): Make the same as clean, not as distclean.
2851 (config.h, stamp-h): New targets.
2853 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2855 * interp.c (ColdReset): Fix boolean test. Make all simulator
2858 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2860 * interp.c (xfer_direct_word, xfer_direct_long,
2861 swap_direct_word, swap_direct_long, xfer_big_word,
2862 xfer_big_long, xfer_little_word, xfer_little_long,
2863 swap_word,swap_long): Added.
2864 * interp.c (ColdReset): Provide function indirection to
2865 host<->simulated_target transfer routines.
2866 * interp.c (sim_store_register, sim_fetch_register): Updated to
2867 make use of indirected transfer routines.
2869 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2871 * gencode.c (process_instructions): Ensure FP ABS instruction
2873 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2874 system call support.
2876 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2878 * interp.c (sim_do_command): Complain if callback structure not
2881 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2883 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2884 support for Sun hosts.
2885 * Makefile.in (gencode): Ensure the host compiler and libraries
2886 used for cross-hosted build.
2888 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2890 * interp.c, gencode.c: Some more (TODO) tidying.
2892 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2894 * gencode.c, interp.c: Replaced explicit long long references with
2895 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2896 * support.h (SET64LO, SET64HI): Macros added.
2898 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2900 * configure: Regenerate with autoconf 2.7.
2902 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2904 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2905 * support.h: Remove superfluous "1" from #if.
2906 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2908 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2910 * interp.c (StoreFPR): Control UndefinedResult() call on
2911 WARN_RESULT manifest.
2913 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2915 * gencode.c: Tidied instruction decoding, and added FP instruction
2918 * interp.c: Added dineroIII, and BSD profiling support. Also
2919 run-time FP handling.
2921 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2923 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2924 gencode.c, interp.c, support.h: created.