1 2016-01-10 Mike Frysinger <vapier@gentoo.org>
3 * configure: Regenerate.
5 2016-01-10 Mike Frysinger <vapier@gentoo.org>
7 * configure: Regenerate.
9 2016-01-09 Mike Frysinger <vapier@gentoo.org>
11 * config.in, configure: Regenerate.
13 2016-01-06 Mike Frysinger <vapier@gentoo.org>
15 * interp.c (sim_open): Mark argv const.
16 (sim_create_inferior): Mark argv and env const.
18 2016-01-04 Mike Frysinger <vapier@gentoo.org>
20 * configure: Regenerate.
22 2016-01-03 Mike Frysinger <vapier@gentoo.org>
24 * interp.c (sim_open): Update sim_parse_args comment.
26 2016-01-03 Mike Frysinger <vapier@gentoo.org>
28 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
29 * configure: Regenerate.
31 2016-01-02 Mike Frysinger <vapier@gentoo.org>
33 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
34 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
35 * configure: Regenerate.
36 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
38 2016-01-02 Mike Frysinger <vapier@gentoo.org>
40 * dv-tx3904cpu.c (CPU, SD): Delete.
42 2015-12-30 Mike Frysinger <vapier@gentoo.org>
44 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
45 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
46 (sim_store_register): Rename to ...
47 (mips_reg_store): ... this. Delete local cpu var.
48 Update sim_io_eprintf calls.
49 (sim_fetch_register): Rename to ...
50 (mips_reg_fetch): ... this. Delete local cpu var.
51 Update sim_io_eprintf calls.
53 2015-12-27 Mike Frysinger <vapier@gentoo.org>
55 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
57 2015-12-26 Mike Frysinger <vapier@gentoo.org>
59 * config.in, configure: Regenerate.
61 2015-12-26 Mike Frysinger <vapier@gentoo.org>
63 * interp.c (sim_write, sim_read): Delete.
64 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
65 (load_word): Likewise.
66 * micromips.igen (cache): Likewise.
67 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
68 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
69 do_store_left, do_store_right, do_load_double, do_store_double):
71 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
73 * sim-main.c (address_translation, prefetch): Delete.
74 (ifetch32, ifetch16): Delete call to AddressTranslation and set
76 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
77 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
78 (LoadMemory, StoreMemory): Delete CCA arg.
80 2015-12-24 Mike Frysinger <vapier@gentoo.org>
82 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
83 * configure: Regenerated.
85 2015-12-24 Mike Frysinger <vapier@gentoo.org>
87 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
90 2015-12-24 Mike Frysinger <vapier@gentoo.org>
92 * tconfig.h (SIM_HANDLES_LMA): Delete.
94 2015-12-24 Mike Frysinger <vapier@gentoo.org>
96 * sim-main.h (WITH_WATCHPOINTS): Delete.
98 2015-12-24 Mike Frysinger <vapier@gentoo.org>
100 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
102 2015-12-24 Mike Frysinger <vapier@gentoo.org>
104 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
106 2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
108 * micromips.igen (process_isa_mode): Fix left shift of negative
111 2015-11-17 Mike Frysinger <vapier@gentoo.org>
113 * sim-main.h (WITH_MODULO_MEMORY): Delete.
115 2015-11-15 Mike Frysinger <vapier@gentoo.org>
117 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
119 2015-11-14 Mike Frysinger <vapier@gentoo.org>
121 * interp.c (sim_close): Rename to ...
122 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
124 * sim-main.h (mips_sim_close): Declare.
125 (SIM_CLOSE_HOOK): Define.
127 2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
128 Ali Lown <ali.lown@imgtec.com>
130 * Makefile.in (tmp-micromips): New rule.
131 (tmp-mach-multi): Add support for micromips.
132 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
133 that works for both mips64 and micromips64.
134 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
136 Add build support for micromips.
137 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
138 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
139 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
140 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
141 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
142 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
143 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
144 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
145 Refactored instruction code to use these functions.
146 * dsp2.igen: Refactored instruction code to use the new functions.
147 * interp.c (decode_coproc): Refactored to work with any instruction
149 (isa_mode): New variable
150 (RSVD_INSTRUCTION): Changed to 0x00000039.
151 * m16.igen (BREAK16): Refactored instruction to use do_break16.
152 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
153 * micromips.dc: New file.
154 * micromips.igen: New file.
155 * micromips16.dc: New file.
156 * micromipsdsp.igen: New file.
157 * micromipsrun.c: New file.
158 * mips.igen (do_swc1): Changed to work with any instruction encoding.
159 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
160 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
161 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
162 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
163 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
164 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
165 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
166 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
167 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
168 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
169 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
170 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
171 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
172 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
173 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
174 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
175 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
176 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
178 Refactored instruction code to use these functions.
179 (RSVD): Changed to use new reserved instruction.
180 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
181 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
182 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
183 do_store_double): Added micromips32 and micromips64 models.
184 Added include for micromips.igen and micromipsdsp.igen
185 Add micromips32 and micromips64 models.
186 (DecodeCoproc): Updated to use new macro definition.
187 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
188 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
189 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
190 Refactored instruction code to use these functions.
191 * sim-main.h (CP0_operation): New enum.
192 (DecodeCoproc): Updated macro.
193 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
194 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
195 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
196 ISA_MODE_MICROMIPS): New defines.
197 (sim_state): Add isa_mode field.
199 2015-06-23 Mike Frysinger <vapier@gentoo.org>
201 * configure: Regenerate.
203 2015-06-12 Mike Frysinger <vapier@gentoo.org>
205 * configure.ac: Change configure.in to configure.ac.
206 * configure: Regenerate.
208 2015-06-12 Mike Frysinger <vapier@gentoo.org>
210 * configure: Regenerate.
212 2015-06-12 Mike Frysinger <vapier@gentoo.org>
214 * interp.c [TRACE]: Delete.
215 (TRACE): Change to WITH_TRACE_ANY_P.
216 [!WITH_TRACE_ANY_P] (open_trace): Define.
217 (mips_option_handler, open_trace, sim_close, dotrace):
218 Change defined(TRACE) to WITH_TRACE_ANY_P.
219 (sim_open): Delete TRACE ifdef check.
220 * sim-main.c (load_memory): Delete TRACE ifdef check.
221 (store_memory): Likewise.
222 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
223 [!WITH_TRACE_ANY_P] (dotrace): Define.
225 2015-04-18 Mike Frysinger <vapier@gentoo.org>
227 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
230 2015-04-18 Mike Frysinger <vapier@gentoo.org>
232 * sim-main.h (SIM_CPU): Delete.
234 2015-04-18 Mike Frysinger <vapier@gentoo.org>
236 * sim-main.h (sim_cia): Delete.
238 2015-04-17 Mike Frysinger <vapier@gentoo.org>
240 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
242 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
243 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
244 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
245 CIA_SET to CPU_PC_SET.
246 * sim-main.h (CIA_GET, CIA_SET): Delete.
248 2015-04-15 Mike Frysinger <vapier@gentoo.org>
250 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
251 * sim-main.h (STATE_CPU): Delete.
253 2015-04-13 Mike Frysinger <vapier@gentoo.org>
255 * configure: Regenerate.
257 2015-04-13 Mike Frysinger <vapier@gentoo.org>
259 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
260 * interp.c (mips_pc_get, mips_pc_set): New functions.
261 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
262 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
263 (sim_pc_get): Delete.
264 * sim-main.h (SIM_CPU): Define.
265 (struct sim_state): Change cpu to an array of pointers.
268 2015-04-13 Mike Frysinger <vapier@gentoo.org>
270 * interp.c (mips_option_handler, open_trace, sim_close,
271 sim_write, sim_read, sim_store_register, sim_fetch_register,
272 sim_create_inferior, pr_addr, pr_uword64): Convert old style
274 (sim_open): Convert old style prototype. Change casts with
275 sim_write to unsigned char *.
276 (fetch_str): Change null to unsigned char, and change cast to
278 (sim_monitor): Change c & ch to unsigned char. Change cast to
281 2015-04-12 Mike Frysinger <vapier@gentoo.org>
283 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
285 2015-04-06 Mike Frysinger <vapier@gentoo.org>
287 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
289 2015-04-01 Mike Frysinger <vapier@gentoo.org>
291 * tconfig.h (SIM_HAVE_PROFILE): Delete.
293 2015-03-31 Mike Frysinger <vapier@gentoo.org>
295 * config.in, configure: Regenerate.
297 2015-03-24 Mike Frysinger <vapier@gentoo.org>
299 * interp.c (sim_pc_get): New function.
301 2015-03-24 Mike Frysinger <vapier@gentoo.org>
303 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
304 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
306 2015-03-24 Mike Frysinger <vapier@gentoo.org>
308 * configure: Regenerate.
310 2015-03-23 Mike Frysinger <vapier@gentoo.org>
312 * configure: Regenerate.
314 2015-03-23 Mike Frysinger <vapier@gentoo.org>
316 * configure: Regenerate.
317 * configure.ac (mips_extra_objs): Delete.
318 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
319 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
321 2015-03-23 Mike Frysinger <vapier@gentoo.org>
323 * configure: Regenerate.
324 * configure.ac: Delete sim_hw checks for dv-sockser.
326 2015-03-16 Mike Frysinger <vapier@gentoo.org>
328 * config.in, configure: Regenerate.
329 * tconfig.in: Rename file ...
330 * tconfig.h: ... here.
332 2015-03-15 Mike Frysinger <vapier@gentoo.org>
334 * tconfig.in: Delete includes.
335 [HAVE_DV_SOCKSER]: Delete.
337 2015-03-14 Mike Frysinger <vapier@gentoo.org>
339 * Makefile.in (SIM_RUN_OBJS): Delete.
341 2015-03-14 Mike Frysinger <vapier@gentoo.org>
343 * configure.ac (AC_CHECK_HEADERS): Delete.
344 * aclocal.m4, configure: Regenerate.
346 2014-08-19 Alan Modra <amodra@gmail.com>
348 * configure: Regenerate.
350 2014-08-15 Roland McGrath <mcgrathr@google.com>
352 * configure: Regenerate.
353 * config.in: Regenerate.
355 2014-03-04 Mike Frysinger <vapier@gentoo.org>
357 * configure: Regenerate.
359 2013-09-23 Alan Modra <amodra@gmail.com>
361 * configure: Regenerate.
363 2013-06-03 Mike Frysinger <vapier@gentoo.org>
365 * aclocal.m4, configure: Regenerate.
367 2013-05-10 Freddie Chopin <freddie_chopin@op.pl>
369 * configure: Rebuild.
371 2013-03-26 Mike Frysinger <vapier@gentoo.org>
373 * configure: Regenerate.
375 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
377 * configure.ac: Address use of dv-sockser.o.
378 * tconfig.in: Conditionalize use of dv_sockser_install.
379 * configure: Regenerated.
380 * config.in: Regenerated.
382 2012-10-04 Chao-ying Fu <fu@mips.com>
383 Steve Ellcey <sellcey@mips.com>
385 * mips/mips3264r2.igen (rdhwr): New.
387 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
389 * configure.ac: Always link against dv-sockser.o.
390 * configure: Regenerate.
392 2012-06-15 Joel Brobecker <brobecker@adacore.com>
394 * config.in, configure: Regenerate.
396 2012-05-18 Nick Clifton <nickc@redhat.com>
399 * interp.c: Include config.h before system header files.
401 2012-03-24 Mike Frysinger <vapier@gentoo.org>
403 * aclocal.m4, config.in, configure: Regenerate.
405 2011-12-03 Mike Frysinger <vapier@gentoo.org>
407 * aclocal.m4: New file.
408 * configure: Regenerate.
410 2011-10-19 Mike Frysinger <vapier@gentoo.org>
412 * configure: Regenerate after common/acinclude.m4 update.
414 2011-10-17 Mike Frysinger <vapier@gentoo.org>
416 * configure.ac: Change include to common/acinclude.m4.
418 2011-10-17 Mike Frysinger <vapier@gentoo.org>
420 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
421 call. Replace common.m4 include with SIM_AC_COMMON.
422 * configure: Regenerate.
424 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
426 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
428 (tmp-mach-multi): Exit early when igen fails.
430 2011-07-05 Mike Frysinger <vapier@gentoo.org>
432 * interp.c (sim_do_command): Delete.
434 2011-02-14 Mike Frysinger <vapier@gentoo.org>
436 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
437 (tx3904sio_fifo_reset): Likewise.
438 * interp.c (sim_monitor): Likewise.
440 2010-04-14 Mike Frysinger <vapier@gentoo.org>
442 * interp.c (sim_write): Add const to buffer arg.
444 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
446 * interp.c: Don't include sysdep.h
448 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
450 * configure: Regenerate.
452 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
454 * config.in: Regenerate.
455 * configure: Likewise.
457 * configure: Regenerate.
459 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
461 * configure: Regenerate to track ../common/common.m4 changes.
464 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
465 Daniel Jacobowitz <dan@codesourcery.com>
466 Joseph Myers <joseph@codesourcery.com>
468 * configure: Regenerate.
470 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
472 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
473 that unconditionally allows fmt_ps.
474 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
475 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
476 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
477 filter from 64,f to 32,f.
478 (PREFX): Change filter from 64 to 32.
479 (LDXC1, LUXC1): Provide separate mips32r2 implementations
480 that use do_load_double instead of do_load. Make both LUXC1
481 versions unpredictable if SizeFGR () != 64.
482 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
483 instead of do_store. Remove unused variable. Make both SUXC1
484 versions unpredictable if SizeFGR () != 64.
486 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
488 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
489 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
490 shifts for that case.
492 2007-09-04 Nick Clifton <nickc@redhat.com>
494 * interp.c (options enum): Add OPTION_INFO_MEMORY.
495 (display_mem_info): New static variable.
496 (mips_option_handler): Handle OPTION_INFO_MEMORY.
497 (mips_options): Add info-memory and memory-info.
498 (sim_open): After processing the command line and board
499 specification, check display_mem_info. If it is set then
500 call the real handler for the --memory-info command line
503 2007-08-24 Joel Brobecker <brobecker@adacore.com>
505 * configure.ac: Change license of multi-run.c to GPL version 3.
506 * configure: Regenerate.
508 2007-06-28 Richard Sandiford <richard@codesourcery.com>
510 * configure.ac, configure: Revert last patch.
512 2007-06-26 Richard Sandiford <richard@codesourcery.com>
514 * configure.ac (sim_mipsisa3264_configs): New variable.
515 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
516 every configuration support all four targets, using the triplet to
517 determine the default.
518 * configure: Regenerate.
520 2007-06-25 Richard Sandiford <richard@codesourcery.com>
522 * Makefile.in (m16run.o): New rule.
524 2007-05-15 Thiemo Seufer <ths@mips.com>
526 * mips3264r2.igen (DSHD): Fix compile warning.
528 2007-05-14 Thiemo Seufer <ths@mips.com>
530 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
531 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
532 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
533 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
536 2007-03-01 Thiemo Seufer <ths@mips.com>
538 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
541 2007-02-20 Thiemo Seufer <ths@mips.com>
543 * dsp.igen: Update copyright notice.
544 * dsp2.igen: Fix copyright notice.
546 2007-02-20 Thiemo Seufer <ths@mips.com>
547 Chao-Ying Fu <fu@mips.com>
549 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
550 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
551 Add dsp2 to sim_igen_machine.
552 * configure: Regenerate.
553 * dsp.igen (do_ph_op): Add MUL support when op = 2.
554 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
555 (mulq_rs.ph): Use do_ph_mulq.
556 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
557 * mips.igen: Add dsp2 model and include dsp2.igen.
558 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
559 for *mips32r2, *mips64r2, *dsp.
560 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
561 for *mips32r2, *mips64r2, *dsp2.
562 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
564 2007-02-19 Thiemo Seufer <ths@mips.com>
565 Nigel Stephens <nigel@mips.com>
567 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
568 jumps with hazard barrier.
570 2007-02-19 Thiemo Seufer <ths@mips.com>
571 Nigel Stephens <nigel@mips.com>
573 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
574 after each call to sim_io_write.
576 2007-02-19 Thiemo Seufer <ths@mips.com>
577 Nigel Stephens <nigel@mips.com>
579 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
580 supported by this simulator.
581 (decode_coproc): Recognise additional CP0 Config registers
584 2007-02-19 Thiemo Seufer <ths@mips.com>
585 Nigel Stephens <nigel@mips.com>
586 David Ung <davidu@mips.com>
588 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
589 uninterpreted formats. If fmt is one of the uninterpreted types
590 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
591 fmt_word, and fmt_uninterpreted_64 like fmt_long.
592 (store_fpr): When writing an invalid odd register, set the
593 matching even register to fmt_unknown, not the following register.
594 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
595 the the memory window at offset 0 set by --memory-size command
597 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
599 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
601 (sim_monitor): When returning the memory size to the MIPS
602 application, use the value in STATE_MEM_SIZE, not an arbitrary
604 (cop_lw): Don' mess around with FPR_STATE, just pass
605 fmt_uninterpreted_32 to StoreFPR.
607 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
609 * mips.igen (not_word_value): Single version for mips32, mips64
612 2007-02-19 Thiemo Seufer <ths@mips.com>
613 Nigel Stephens <nigel@mips.com>
615 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
618 2007-02-17 Thiemo Seufer <ths@mips.com>
620 * configure.ac (mips*-sde-elf*): Move in front of generic machine
622 * configure: Regenerate.
624 2007-02-17 Thiemo Seufer <ths@mips.com>
626 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
627 Add mdmx to sim_igen_machine.
628 (mipsisa64*-*-*): Likewise. Remove dsp.
629 (mipsisa32*-*-*): Remove dsp.
630 * configure: Regenerate.
632 2007-02-13 Thiemo Seufer <ths@mips.com>
634 * configure.ac: Add mips*-sde-elf* target.
635 * configure: Regenerate.
637 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
639 * acconfig.h: Remove.
640 * config.in, configure: Regenerate.
642 2006-11-07 Thiemo Seufer <ths@mips.com>
644 * dsp.igen (do_w_op): Fix compiler warning.
646 2006-08-29 Thiemo Seufer <ths@mips.com>
647 David Ung <davidu@mips.com>
649 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
651 * configure: Regenerate.
652 * mips.igen (model): Add smartmips.
653 (MADDU): Increment ACX if carry.
654 (do_mult): Clear ACX.
655 (ROR,RORV): Add smartmips.
656 (include): Include smartmips.igen.
657 * sim-main.h (ACX): Set to REGISTERS[89].
658 * smartmips.igen: New file.
660 2006-08-29 Thiemo Seufer <ths@mips.com>
661 David Ung <davidu@mips.com>
663 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
664 mips3264r2.igen. Add missing dependency rules.
665 * m16e.igen: Support for mips16e save/restore instructions.
667 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
669 * configure: Regenerated.
671 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
673 * configure: Regenerated.
675 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
677 * configure: Regenerated.
679 2006-05-15 Chao-ying Fu <fu@mips.com>
681 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
683 2006-04-18 Nick Clifton <nickc@redhat.com>
685 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
688 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
690 * configure: Regenerate.
692 2005-12-14 Chao-ying Fu <fu@mips.com>
694 * Makefile.in (SIM_OBJS): Add dsp.o.
695 (dsp.o): New dependency.
696 (IGEN_INCLUDE): Add dsp.igen.
697 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
698 mipsisa64*-*-*): Add dsp to sim_igen_machine.
699 * configure: Regenerate.
700 * mips.igen: Add dsp model and include dsp.igen.
701 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
702 because these instructions are extended in DSP ASE.
703 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
704 adding 6 DSP accumulator registers and 1 DSP control register.
705 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
706 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
707 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
708 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
709 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
710 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
711 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
712 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
713 DSPCR_CCOND_SMASK): New define.
714 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
715 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
717 2005-07-08 Ian Lance Taylor <ian@airs.com>
719 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
721 2005-06-16 David Ung <davidu@mips.com>
722 Nigel Stephens <nigel@mips.com>
724 * mips.igen: New mips16e model and include m16e.igen.
725 (check_u64): Add mips16e tag.
726 * m16e.igen: New file for MIPS16e instructions.
727 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
728 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
730 * configure: Regenerate.
732 2005-05-26 David Ung <davidu@mips.com>
734 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
735 tags to all instructions which are applicable to the new ISAs.
736 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
738 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
740 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
742 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
743 * configure: Regenerate.
745 2005-03-23 Mark Kettenis <kettenis@gnu.org>
747 * configure: Regenerate.
749 2005-01-14 Andrew Cagney <cagney@gnu.org>
751 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
752 explicit call to AC_CONFIG_HEADER.
753 * configure: Regenerate.
755 2005-01-12 Andrew Cagney <cagney@gnu.org>
757 * configure.ac: Update to use ../common/common.m4.
758 * configure: Re-generate.
760 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
762 * configure: Regenerated to track ../common/aclocal.m4 changes.
764 2005-01-07 Andrew Cagney <cagney@gnu.org>
766 * configure.ac: Rename configure.in, require autoconf 2.59.
767 * configure: Re-generate.
769 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
771 * configure: Regenerate for ../common/aclocal.m4 update.
773 2004-09-24 Monika Chaddha <monika@acmet.com>
775 Committed by Andrew Cagney.
776 * m16.igen (CMP, CMPI): Fix assembler.
778 2004-08-18 Chris Demetriou <cgd@broadcom.com>
780 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
781 * configure: Regenerate.
783 2004-06-25 Chris Demetriou <cgd@broadcom.com>
785 * configure.in (sim_m16_machine): Include mipsIII.
786 * configure: Regenerate.
788 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
790 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
792 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
794 2004-04-10 Chris Demetriou <cgd@broadcom.com>
796 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
798 2004-04-09 Chris Demetriou <cgd@broadcom.com>
800 * mips.igen (check_fmt): Remove.
801 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
802 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
803 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
804 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
805 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
806 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
807 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
808 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
809 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
810 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
812 2004-04-09 Chris Demetriou <cgd@broadcom.com>
814 * sb1.igen (check_sbx): New function.
815 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
817 2004-03-29 Chris Demetriou <cgd@broadcom.com>
818 Richard Sandiford <rsandifo@redhat.com>
820 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
821 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
822 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
823 separate implementations for mipsIV and mipsV. Use new macros to
824 determine whether the restrictions apply.
826 2004-01-19 Chris Demetriou <cgd@broadcom.com>
828 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
829 (check_mult_hilo): Improve comments.
830 (check_div_hilo): Likewise. Also, fork off a new version
831 to handle mips32/mips64 (since there are no hazards to check
834 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
836 * mips.igen (do_dmultx): Fix check for negative operands.
838 2003-05-16 Ian Lance Taylor <ian@airs.com>
840 * Makefile.in (SHELL): Make sure this is defined.
841 (various): Use $(SHELL) whenever we invoke move-if-change.
843 2003-05-03 Chris Demetriou <cgd@broadcom.com>
845 * cp1.c: Tweak attribution slightly.
848 * mdmx.igen: Likewise.
849 * mips3d.igen: Likewise.
850 * sb1.igen: Likewise.
852 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
854 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
857 2003-02-27 Andrew Cagney <cagney@redhat.com>
859 * interp.c (sim_open): Rename _bfd to bfd.
860 (sim_create_inferior): Ditto.
862 2003-01-14 Chris Demetriou <cgd@broadcom.com>
864 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
866 2003-01-14 Chris Demetriou <cgd@broadcom.com>
868 * mips.igen (EI, DI): Remove.
870 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
872 * Makefile.in (tmp-run-multi): Fix mips16 filter.
874 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
875 Andrew Cagney <ac131313@redhat.com>
876 Gavin Romig-Koch <gavin@redhat.com>
877 Graydon Hoare <graydon@redhat.com>
878 Aldy Hernandez <aldyh@redhat.com>
879 Dave Brolley <brolley@redhat.com>
880 Chris Demetriou <cgd@broadcom.com>
882 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
883 (sim_mach_default): New variable.
884 (mips64vr-*-*, mips64vrel-*-*): New configurations.
885 Add a new simulator generator, MULTI.
886 * configure: Regenerate.
887 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
888 (multi-run.o): New dependency.
889 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
890 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
891 (tmp-multi): Combine them.
892 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
893 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
894 (distclean-extra): New rule.
895 * sim-main.h: Include bfd.h.
896 (MIPS_MACH): New macro.
897 * mips.igen (vr4120, vr5400, vr5500): New models.
898 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
899 * vr.igen: Replace with new version.
901 2003-01-04 Chris Demetriou <cgd@broadcom.com>
903 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
904 * configure: Regenerate.
906 2002-12-31 Chris Demetriou <cgd@broadcom.com>
908 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
909 * mips.igen: Remove all invocations of check_branch_bug and
912 2002-12-16 Chris Demetriou <cgd@broadcom.com>
914 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
916 2002-07-30 Chris Demetriou <cgd@broadcom.com>
918 * mips.igen (do_load_double, do_store_double): New functions.
919 (LDC1, SDC1): Rename to...
920 (LDC1b, SDC1b): respectively.
921 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
923 2002-07-29 Michael Snyder <msnyder@redhat.com>
925 * cp1.c (fp_recip2): Modify initialization expression so that
926 GCC will recognize it as constant.
928 2002-06-18 Chris Demetriou <cgd@broadcom.com>
930 * mdmx.c (SD_): Delete.
931 (Unpredictable): Re-define, for now, to directly invoke
932 unpredictable_action().
933 (mdmx_acc_op): Fix error in .ob immediate handling.
935 2002-06-18 Andrew Cagney <cagney@redhat.com>
937 * interp.c (sim_firmware_command): Initialize `address'.
939 2002-06-16 Andrew Cagney <ac131313@redhat.com>
941 * configure: Regenerated to track ../common/aclocal.m4 changes.
943 2002-06-14 Chris Demetriou <cgd@broadcom.com>
944 Ed Satterthwaite <ehs@broadcom.com>
946 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
947 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
948 * mips.igen: Include mips3d.igen.
949 (mips3d): New model name for MIPS-3D ASE instructions.
950 (CVT.W.fmt): Don't use this instruction for word (source) format
952 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
953 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
954 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
955 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
956 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
957 (RSquareRoot1, RSquareRoot2): New macros.
958 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
959 (fp_rsqrt2): New functions.
960 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
961 * configure: Regenerate.
963 2002-06-13 Chris Demetriou <cgd@broadcom.com>
964 Ed Satterthwaite <ehs@broadcom.com>
966 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
967 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
968 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
969 (convert): Note that this function is not used for paired-single
971 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
972 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
973 (check_fmt_p): Enable paired-single support.
974 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
975 (PUU.PS): New instructions.
976 (CVT.S.fmt): Don't use this instruction for paired-single format
978 * sim-main.h (FP_formats): New value 'fmt_ps.'
979 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
980 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
982 2002-06-12 Chris Demetriou <cgd@broadcom.com>
984 * mips.igen: Fix formatting of function calls in
987 2002-06-12 Chris Demetriou <cgd@broadcom.com>
989 * mips.igen (MOVN, MOVZ): Trace result.
990 (TNEI): Print "tnei" as the opcode name in traces.
991 (CEIL.W): Add disassembly string for traces.
992 (RSQRT.fmt): Make location of disassembly string consistent
993 with other instructions.
995 2002-06-12 Chris Demetriou <cgd@broadcom.com>
997 * mips.igen (X): Delete unused function.
999 2002-06-08 Andrew Cagney <cagney@redhat.com>
1001 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1003 2002-06-07 Chris Demetriou <cgd@broadcom.com>
1004 Ed Satterthwaite <ehs@broadcom.com>
1006 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1007 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1008 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1009 (fp_nmsub): New prototypes.
1010 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1011 (NegMultiplySub): New defines.
1012 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1013 (MADD.D, MADD.S): Replace with...
1014 (MADD.fmt): New instruction.
1015 (MSUB.D, MSUB.S): Replace with...
1016 (MSUB.fmt): New instruction.
1017 (NMADD.D, NMADD.S): Replace with...
1018 (NMADD.fmt): New instruction.
1019 (NMSUB.D, MSUB.S): Replace with...
1020 (NMSUB.fmt): New instruction.
1022 2002-06-07 Chris Demetriou <cgd@broadcom.com>
1023 Ed Satterthwaite <ehs@broadcom.com>
1025 * cp1.c: Fix more comment spelling and formatting.
1026 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1027 (denorm_mode): New function.
1028 (fpu_unary, fpu_binary): Round results after operation, collect
1029 status from rounding operations, and update the FCSR.
1030 (convert): Collect status from integer conversions and rounding
1031 operations, and update the FCSR. Adjust NaN values that result
1032 from conversions. Convert to use sim_io_eprintf rather than
1033 fprintf, and remove some debugging code.
1034 * cp1.h (fenr_FS): New define.
1036 2002-06-07 Chris Demetriou <cgd@broadcom.com>
1038 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1039 rounding mode to sim FP rounding mode flag conversion code into...
1040 (rounding_mode): New function.
1042 2002-06-07 Chris Demetriou <cgd@broadcom.com>
1044 * cp1.c: Clean up formatting of a few comments.
1045 (value_fpr): Reformat switch statement.
1047 2002-06-06 Chris Demetriou <cgd@broadcom.com>
1048 Ed Satterthwaite <ehs@broadcom.com>
1051 * sim-main.h: Include cp1.h.
1052 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1053 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1054 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1055 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1056 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1057 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1058 * cp1.c: Don't include sim-fpu.h; already included by
1059 sim-main.h. Clean up formatting of some comments.
1060 (NaN, Equal, Less): Remove.
1061 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1062 (fp_cmp): New functions.
1063 * mips.igen (do_c_cond_fmt): Remove.
1064 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1065 Compare. Add result tracing.
1066 (CxC1): Remove, replace with...
1067 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1068 (DMxC1): Remove, replace with...
1069 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
1070 (MxC1): Remove, replace with...
1071 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
1073 2002-06-04 Chris Demetriou <cgd@broadcom.com>
1075 * sim-main.h (FGRIDX): Remove, replace all uses with...
1076 (FGR_BASE): New macro.
1077 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1078 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1079 (NR_FGR, FGR): Likewise.
1080 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1081 * mips.igen: Likewise.
1083 2002-06-04 Chris Demetriou <cgd@broadcom.com>
1085 * cp1.c: Add an FSF Copyright notice to this file.
1087 2002-06-04 Chris Demetriou <cgd@broadcom.com>
1088 Ed Satterthwaite <ehs@broadcom.com>
1090 * cp1.c (Infinity): Remove.
1091 * sim-main.h (Infinity): Likewise.
1093 * cp1.c (fp_unary, fp_binary): New functions.
1094 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1095 (fp_sqrt): New functions, implemented in terms of the above.
1096 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1097 (Recip, SquareRoot): Remove (replaced by functions above).
1098 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1099 (fp_recip, fp_sqrt): New prototypes.
1100 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1101 (Recip, SquareRoot): Replace prototypes with #defines which
1102 invoke the functions above.
1104 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1106 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1107 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1108 file, remove PARAMS from prototypes.
1109 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1110 simulator state arguments.
1111 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1112 pass simulator state arguments.
1113 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1114 (store_fpr, convert): Remove 'sd' argument.
1115 (value_fpr): Likewise. Convert to use 'SD' instead.
1117 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1119 * cp1.c (Min, Max): Remove #if 0'd functions.
1120 * sim-main.h (Min, Max): Remove.
1122 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1124 * cp1.c: fix formatting of switch case and default labels.
1125 * interp.c: Likewise.
1126 * sim-main.c: Likewise.
1128 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1130 * cp1.c: Clean up comments which describe FP formats.
1131 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1133 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1134 Ed Satterthwaite <ehs@broadcom.com>
1136 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1137 Broadcom SiByte SB-1 processor configurations.
1138 * configure: Regenerate.
1139 * sb1.igen: New file.
1140 * mips.igen: Include sb1.igen.
1142 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1143 * mdmx.igen: Add "sb1" model to all appropriate functions and
1145 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1146 (ob_func, ob_acc): Reference the above.
1147 (qh_acc): Adjust to keep the same size as ob_acc.
1148 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1149 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1151 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1153 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1155 2002-06-02 Chris Demetriou <cgd@broadcom.com>
1156 Ed Satterthwaite <ehs@broadcom.com>
1158 * mips.igen (mdmx): New (pseudo-)model.
1159 * mdmx.c, mdmx.igen: New files.
1160 * Makefile.in (SIM_OBJS): Add mdmx.o.
1161 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1163 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1164 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1165 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1166 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1167 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1168 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1169 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1170 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1171 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1172 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1173 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1174 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1175 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1176 (qh_fmtsel): New macros.
1177 (_sim_cpu): New member "acc".
1178 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1179 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1181 2002-05-01 Chris Demetriou <cgd@broadcom.com>
1183 * interp.c: Use 'deprecated' rather than 'depreciated.'
1184 * sim-main.h: Likewise.
1186 2002-05-01 Chris Demetriou <cgd@broadcom.com>
1188 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1189 which wouldn't compile anyway.
1190 * sim-main.h (unpredictable_action): New function prototype.
1191 (Unpredictable): Define to call igen function unpredictable().
1192 (NotWordValue): New macro to call igen function not_word_value().
1193 (UndefinedResult): Remove.
1194 * interp.c (undefined_result): Remove.
1195 (unpredictable_action): New function.
1196 * mips.igen (not_word_value, unpredictable): New functions.
1197 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1198 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1199 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1200 NotWordValue() to check for unpredictable inputs, then
1201 Unpredictable() to handle them.
1203 2002-02-24 Chris Demetriou <cgd@broadcom.com>
1205 * mips.igen: Fix formatting of calls to Unpredictable().
1207 2002-04-20 Andrew Cagney <ac131313@redhat.com>
1209 * interp.c (sim_open): Revert previous change.
1211 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
1213 * interp.c (sim_open): Disable chunk of code that wrote code in
1214 vector table entries.
1216 2002-03-19 Chris Demetriou <cgd@broadcom.com>
1218 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1219 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1222 2002-03-19 Chris Demetriou <cgd@broadcom.com>
1224 * cp1.c: Fix many formatting issues.
1226 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1228 * cp1.c (fpu_format_name): New function to replace...
1229 (DOFMT): This. Delete, and update all callers.
1230 (fpu_rounding_mode_name): New function to replace...
1231 (RMMODE): This. Delete, and update all callers.
1233 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1235 * interp.c: Move FPU support routines from here to...
1236 * cp1.c: Here. New file.
1237 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1238 (cp1.o): New target.
1240 2002-03-12 Chris Demetriou <cgd@broadcom.com>
1242 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1243 * mips.igen (mips32, mips64): New models, add to all instructions
1244 and functions as appropriate.
1245 (loadstore_ea, check_u64): New variant for model mips64.
1246 (check_fmt_p): New variant for models mipsV and mips64, remove
1247 mipsV model marking fro other variant.
1250 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1251 for mips32 and mips64.
1252 (DCLO, DCLZ): New instructions for mips64.
1254 2002-03-07 Chris Demetriou <cgd@broadcom.com>
1256 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1257 immediate or code as a hex value with the "%#lx" format.
1258 (ANDI): Likewise, and fix printed instruction name.
1260 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1262 * sim-main.h (UndefinedResult, Unpredictable): New macros
1263 which currently do nothing.
1265 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1267 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1268 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1269 (status_CU3): New definitions.
1271 * sim-main.h (ExceptionCause): Add new values for MIPS32
1272 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1273 for DebugBreakPoint and NMIReset to note their status in
1275 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1276 (SignalExceptionCacheErr): New exception macros.
1278 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1280 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1281 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1283 (SignalExceptionCoProcessorUnusable): Take as argument the
1284 unusable coprocessor number.
1286 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1288 * mips.igen: Fix formatting of all SignalException calls.
1290 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1292 * sim-main.h (SIGNEXTEND): Remove.
1294 2002-03-04 Chris Demetriou <cgd@broadcom.com>
1296 * mips.igen: Remove gencode comment from top of file, fix
1297 spelling in another comment.
1299 2002-03-04 Chris Demetriou <cgd@broadcom.com>
1301 * mips.igen (check_fmt, check_fmt_p): New functions to check
1302 whether specific floating point formats are usable.
1303 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1304 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1305 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1306 Use the new functions.
1307 (do_c_cond_fmt): Remove format checks...
1308 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1310 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1312 * mips.igen: Fix formatting of check_fpu calls.
1314 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1316 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1318 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1320 * mips.igen: Remove whitespace at end of lines.
1322 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1324 * mips.igen (loadstore_ea): New function to do effective
1325 address calculations.
1326 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1327 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1328 CACHE): Use loadstore_ea to do effective address computations.
1330 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1332 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1333 * mips.igen (LL, CxC1, MxC1): Likewise.
1335 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1337 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1338 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1339 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1340 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1341 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1342 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1343 Don't split opcode fields by hand, use the opcode field values
1346 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1348 * mips.igen (do_divu): Fix spacing.
1350 * mips.igen (do_dsllv): Move to be right before DSLLV,
1351 to match the rest of the do_<shift> functions.
1353 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1355 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1356 DSRL32, do_dsrlv): Trace inputs and results.
1358 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1360 * mips.igen (CACHE): Provide instruction-printing string.
1362 * interp.c (signal_exception): Comment tokens after #endif.
1364 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1366 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1367 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1368 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1369 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1370 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1371 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1372 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1373 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1375 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1377 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1378 instruction-printing string.
1379 (LWU): Use '64' as the filter flag.
1381 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1383 * mips.igen (SDXC1): Fix instruction-printing string.
1385 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1387 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1388 filter flags "32,f".
1390 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1392 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1395 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1397 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1398 add a comma) so that it more closely match the MIPS ISA
1399 documentation opcode partitioning.
1400 (PREF): Put useful names on opcode fields, and include
1401 instruction-printing string.
1403 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1405 * mips.igen (check_u64): New function which in the future will
1406 check whether 64-bit instructions are usable and signal an
1407 exception if not. Currently a no-op.
1408 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1409 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1410 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1411 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1413 * mips.igen (check_fpu): New function which in the future will
1414 check whether FPU instructions are usable and signal an exception
1415 if not. Currently a no-op.
1416 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1417 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1418 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1419 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1420 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1421 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1422 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1423 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1425 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1427 * mips.igen (do_load_left, do_load_right): Move to be immediately
1429 (do_store_left, do_store_right): Move to be immediately following
1432 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1434 * mips.igen (mipsV): New model name. Also, add it to
1435 all instructions and functions where it is appropriate.
1437 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1439 * mips.igen: For all functions and instructions, list model
1440 names that support that instruction one per line.
1442 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1444 * mips.igen: Add some additional comments about supported
1445 models, and about which instructions go where.
1446 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1447 order as is used in the rest of the file.
1449 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1451 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1452 indicating that ALU32_END or ALU64_END are there to check
1454 (DADD): Likewise, but also remove previous comment about
1457 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1459 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1460 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1461 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1462 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1463 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1464 fields (i.e., add and move commas) so that they more closely
1465 match the MIPS ISA documentation opcode partitioning.
1467 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1469 * mips.igen (ADDI): Print immediate value.
1470 (BREAK): Print code.
1471 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1472 (SLL): Print "nop" specially, and don't run the code
1473 that does the shift for the "nop" case.
1475 2001-11-17 Fred Fish <fnf@redhat.com>
1477 * sim-main.h (float_operation): Move enum declaration outside
1478 of _sim_cpu struct declaration.
1480 2001-04-12 Jim Blandy <jimb@redhat.com>
1482 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1483 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1485 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1486 PENDING_FILL, and you can get the intended effect gracefully by
1487 calling PENDING_SCHED directly.
1489 2001-02-23 Ben Elliston <bje@redhat.com>
1491 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1492 already defined elsewhere.
1494 2001-02-19 Ben Elliston <bje@redhat.com>
1496 * sim-main.h (sim_monitor): Return an int.
1497 * interp.c (sim_monitor): Add return values.
1498 (signal_exception): Handle error conditions from sim_monitor.
1500 2001-02-08 Ben Elliston <bje@redhat.com>
1502 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1503 (store_memory): Likewise, pass cia to sim_core_write*.
1505 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1507 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1508 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1510 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1512 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1513 * Makefile.in: Don't delete *.igen when cleaning directory.
1515 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1517 * m16.igen (break): Call SignalException not sim_engine_halt.
1519 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1521 From Jason Eckhardt:
1522 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1524 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1526 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1528 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1530 * mips.igen (do_dmultx): Fix typo.
1532 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1534 * configure: Regenerated to track ../common/aclocal.m4 changes.
1536 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1538 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1540 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1542 * sim-main.h (GPR_CLEAR): Define macro.
1544 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1546 * interp.c (decode_coproc): Output long using %lx and not %s.
1548 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1550 * interp.c (sim_open): Sort & extend dummy memory regions for
1551 --board=jmr3904 for eCos.
1553 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1555 * configure: Regenerated.
1557 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1559 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1560 calls, conditional on the simulator being in verbose mode.
1562 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1564 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1565 cache don't get ReservedInstruction traps.
1567 1999-11-29 Mark Salter <msalter@cygnus.com>
1569 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1570 to clear status bits in sdisr register. This is how the hardware works.
1572 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1573 being used by cygmon.
1575 1999-11-11 Andrew Haley <aph@cygnus.com>
1577 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1580 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1582 * mips.igen (MULT): Correct previous mis-applied patch.
1584 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1586 * mips.igen (delayslot32): Handle sequence like
1587 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1588 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1589 (MULT): Actually pass the third register...
1591 1999-09-03 Mark Salter <msalter@cygnus.com>
1593 * interp.c (sim_open): Added more memory aliases for additional
1594 hardware being touched by cygmon on jmr3904 board.
1596 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1598 * configure: Regenerated to track ../common/aclocal.m4 changes.
1600 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1602 * interp.c (sim_store_register): Handle case where client - GDB -
1603 specifies that a 4 byte register is 8 bytes in size.
1604 (sim_fetch_register): Ditto.
1606 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1608 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1609 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1610 (idt_monitor_base): Base address for IDT monitor traps.
1611 (pmon_monitor_base): Ditto for PMON.
1612 (lsipmon_monitor_base): Ditto for LSI PMON.
1613 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1614 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1615 (sim_firmware_command): New function.
1616 (mips_option_handler): Call it for OPTION_FIRMWARE.
1617 (sim_open): Allocate memory for idt_monitor region. If "--board"
1618 option was given, add no monitor by default. Add BREAK hooks only if
1619 monitors are also there.
1621 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1623 * interp.c (sim_monitor): Flush output before reading input.
1625 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1627 * tconfig.in (SIM_HANDLES_LMA): Always define.
1629 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1631 From Mark Salter <msalter@cygnus.com>:
1632 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1633 (sim_open): Add setup for BSP board.
1635 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1637 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1638 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1639 them as unimplemented.
1641 1999-05-08 Felix Lee <flee@cygnus.com>
1643 * configure: Regenerated to track ../common/aclocal.m4 changes.
1645 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1647 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1649 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1651 * configure.in: Any mips64vr5*-*-* target should have
1652 -DTARGET_ENABLE_FR=1.
1653 (default_endian): Any mips64vr*el-*-* target should default to
1655 * configure: Re-generate.
1657 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1659 * mips.igen (ldl): Extend from _16_, not 32.
1661 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1663 * interp.c (sim_store_register): Force registers written to by GDB
1664 into an un-interpreted state.
1666 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1668 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1669 CPU, start periodic background I/O polls.
1670 (tx3904sio_poll): New function: periodic I/O poller.
1672 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1674 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1676 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1678 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1681 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1683 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1684 (load_word): Call SIM_CORE_SIGNAL hook on error.
1685 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1686 starting. For exception dispatching, pass PC instead of NULL_CIA.
1687 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1688 * sim-main.h (COP0_BADVADDR): Define.
1689 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1690 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1691 (_sim_cpu): Add exc_* fields to store register value snapshots.
1692 * mips.igen (*): Replace memory-related SignalException* calls
1693 with references to SIM_CORE_SIGNAL hook.
1695 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1697 * sim-main.c (*): Minor warning cleanups.
1699 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1701 * m16.igen (DADDIU5): Correct type-o.
1703 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1705 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1708 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1710 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1712 (interp.o): Add dependency on itable.h
1713 (oengine.c, gencode): Delete remaining references.
1714 (BUILT_SRC_FROM_GEN): Clean up.
1716 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1719 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1720 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1721 tmp-run-hack) : New.
1722 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1723 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1724 Drop the "64" qualifier to get the HACK generator working.
1725 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1726 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1727 qualifier to get the hack generator working.
1728 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1729 (DSLL): Use do_dsll.
1730 (DSLLV): Use do_dsllv.
1731 (DSRA): Use do_dsra.
1732 (DSRL): Use do_dsrl.
1733 (DSRLV): Use do_dsrlv.
1734 (BC1): Move *vr4100 to get the HACK generator working.
1735 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1736 get the HACK generator working.
1737 (MACC) Rename to get the HACK generator working.
1738 (DMACC,MACCS,DMACCS): Add the 64.
1740 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1742 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1743 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1745 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1747 * mips/interp.c (DEBUG): Cleanups.
1749 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1751 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1752 (tx3904sio_tickle): fflush after a stdout character output.
1754 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1756 * interp.c (sim_close): Uninstall modules.
1758 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1760 * sim-main.h, interp.c (sim_monitor): Change to global
1763 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1765 * configure.in (vr4100): Only include vr4100 instructions in
1767 * configure: Re-generate.
1768 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1770 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1772 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1773 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1776 * configure.in (sim_default_gen, sim_use_gen): Replace with
1778 (--enable-sim-igen): Delete config option. Always using IGEN.
1779 * configure: Re-generate.
1781 * Makefile.in (gencode): Kill, kill, kill.
1784 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1786 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1787 bit mips16 igen simulator.
1788 * configure: Re-generate.
1790 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1791 as part of vr4100 ISA.
1792 * vr.igen: Mark all instructions as 64 bit only.
1794 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1796 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1799 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1801 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1802 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1803 * configure: Re-generate.
1805 * m16.igen (BREAK): Define breakpoint instruction.
1806 (JALX32): Mark instruction as mips16 and not r3900.
1807 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1809 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1811 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1813 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1814 insn as a debug breakpoint.
1816 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1818 (PENDING_SCHED): Clean up trace statement.
1819 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1820 (PENDING_FILL): Delay write by only one cycle.
1821 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1823 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1825 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1827 (pending_tick): Move incrementing of index to FOR statement.
1828 (pending_tick): Only update PENDING_OUT after a write has occured.
1830 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1832 * configure: Re-generate.
1834 * interp.c (sim_engine_run OLD): Delete explicit call to
1835 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1837 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1839 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1840 interrupt level number to match changed SignalExceptionInterrupt
1843 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1845 * interp.c: #include "itable.h" if WITH_IGEN.
1846 (get_insn_name): New function.
1847 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1848 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1850 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1852 * configure: Rebuilt to inhale new common/aclocal.m4.
1854 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1856 * dv-tx3904sio.c: Include sim-assert.h.
1858 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1860 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1861 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1862 Reorganize target-specific sim-hardware checks.
1863 * configure: rebuilt.
1864 * interp.c (sim_open): For tx39 target boards, set
1865 OPERATING_ENVIRONMENT, add tx3904sio devices.
1866 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1867 ROM executables. Install dv-sockser into sim-modules list.
1869 * dv-tx3904irc.c: Compiler warning clean-up.
1870 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1871 frequent hw-trace messages.
1873 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1875 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1877 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1879 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1881 * vr.igen: New file.
1882 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1883 * mips.igen: Define vr4100 model. Include vr.igen.
1884 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1886 * mips.igen (check_mf_hilo): Correct check.
1888 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1890 * sim-main.h (interrupt_event): Add prototype.
1892 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1893 register_ptr, register_value.
1894 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1896 * sim-main.h (tracefh): Make extern.
1898 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1900 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1901 Reduce unnecessarily high timer event frequency.
1902 * dv-tx3904cpu.c: Ditto for interrupt event.
1904 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1906 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1908 (interrupt_event): Made non-static.
1910 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1911 interchange of configuration values for external vs. internal
1914 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1916 * mips.igen (BREAK): Moved code to here for
1917 simulator-reserved break instructions.
1918 * gencode.c (build_instruction): Ditto.
1919 * interp.c (signal_exception): Code moved from here. Non-
1920 reserved instructions now use exception vector, rather
1922 * sim-main.h: Moved magic constants to here.
1924 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1926 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1927 register upon non-zero interrupt event level, clear upon zero
1929 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1930 by passing zero event value.
1931 (*_io_{read,write}_buffer): Endianness fixes.
1932 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1933 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1935 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1936 serial I/O and timer module at base address 0xFFFF0000.
1938 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1940 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1943 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1945 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1947 * configure: Update.
1949 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1951 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1952 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1953 * configure.in: Include tx3904tmr in hw_device list.
1954 * configure: Rebuilt.
1955 * interp.c (sim_open): Instantiate three timer instances.
1956 Fix address typo of tx3904irc instance.
1958 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1960 * interp.c (signal_exception): SystemCall exception now uses
1961 the exception vector.
1963 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1965 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1968 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1970 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1972 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1974 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1976 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1977 sim-main.h. Declare a struct hw_descriptor instead of struct
1978 hw_device_descriptor.
1980 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1982 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1983 right bits and then re-align left hand bytes to correct byte
1984 lanes. Fix incorrect computation in do_store_left when loading
1985 bytes from second word.
1987 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1989 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1990 * interp.c (sim_open): Only create a device tree when HW is
1993 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1994 * interp.c (signal_exception): Ditto.
1996 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1998 * gencode.c: Mark BEGEZALL as LIKELY.
2000 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2002 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2003 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
2005 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2007 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2008 modules. Recognize TX39 target with "mips*tx39" pattern.
2009 * configure: Rebuilt.
2010 * sim-main.h (*): Added many macros defining bits in
2011 TX39 control registers.
2012 (SignalInterrupt): Send actual PC instead of NULL.
2013 (SignalNMIReset): New exception type.
2014 * interp.c (board): New variable for future use to identify
2015 a particular board being simulated.
2016 (mips_option_handler,mips_options): Added "--board" option.
2017 (interrupt_event): Send actual PC.
2018 (sim_open): Make memory layout conditional on board setting.
2019 (signal_exception): Initial implementation of hardware interrupt
2020 handling. Accept another break instruction variant for simulator
2022 (decode_coproc): Implement RFE instruction for TX39.
2023 (mips.igen): Decode RFE instruction as such.
2024 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2025 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2026 bbegin to implement memory map.
2027 * dv-tx3904cpu.c: New file.
2028 * dv-tx3904irc.c: New file.
2030 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2032 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2034 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2036 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2037 with calls to check_div_hilo.
2039 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2041 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2042 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
2043 Add special r3900 version of do_mult_hilo.
2044 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2045 with calls to check_mult_hilo.
2046 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2047 with calls to check_div_hilo.
2049 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2051 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2052 Document a replacement.
2054 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2056 * interp.c (sim_monitor): Make mon_printf work.
2058 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2060 * sim-main.h (INSN_NAME): New arg `cpu'.
2062 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2064 * configure: Regenerated to track ../common/aclocal.m4 changes.
2066 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2068 * configure: Regenerated to track ../common/aclocal.m4 changes.
2071 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2073 * acconfig.h: New file.
2074 * configure.in: Reverted change of Apr 24; use sinclude again.
2076 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2078 * configure: Regenerated to track ../common/aclocal.m4 changes.
2081 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2083 * configure.in: Don't call sinclude.
2085 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2087 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2089 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2091 * mips.igen (ERET): Implement.
2093 * interp.c (decode_coproc): Return sign-extended EPC.
2095 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2097 * interp.c (signal_exception): Do not ignore Trap.
2098 (signal_exception): On TRAP, restart at exception address.
2099 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2100 (signal_exception): Update.
2101 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2102 so that TRAP instructions are caught.
2104 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2106 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2107 contains HI/LO access history.
2108 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2109 (HIACCESS, LOACCESS): Delete, replace with
2110 (HIHISTORY, LOHISTORY): New macros.
2111 (CHECKHILO): Delete all, moved to mips.igen
2113 * gencode.c (build_instruction): Do not generate checks for
2114 correct HI/LO register usage.
2116 * interp.c (old_engine_run): Delete checks for correct HI/LO
2119 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2120 check_mf_cycles): New functions.
2121 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2122 do_divu, domultx, do_mult, do_multu): Use.
2124 * tx.igen ("madd", "maddu"): Use.
2126 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2128 * mips.igen (DSRAV): Use function do_dsrav.
2129 (SRAV): Use new function do_srav.
2131 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2132 (B): Sign extend 11 bit immediate.
2133 (EXT-B*): Shift 16 bit immediate left by 1.
2134 (ADDIU*): Don't sign extend immediate value.
2136 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2138 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2140 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2143 * mips.igen (delayslot32, nullify_next_insn): New functions.
2144 (m16.igen): Always include.
2145 (do_*): Add more tracing.
2147 * m16.igen (delayslot16): Add NIA argument, could be called by a
2148 32 bit MIPS16 instruction.
2150 * interp.c (ifetch16): Move function from here.
2151 * sim-main.c (ifetch16): To here.
2153 * sim-main.c (ifetch16, ifetch32): Update to match current
2154 implementations of LH, LW.
2155 (signal_exception): Don't print out incorrect hex value of illegal
2158 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2160 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2163 * m16.igen: Implement MIPS16 instructions.
2165 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2166 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2167 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2168 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2169 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2170 bodies of corresponding code from 32 bit insn to these. Also used
2171 by MIPS16 versions of functions.
2173 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2174 (IMEM16): Drop NR argument from macro.
2176 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2178 * Makefile.in (SIM_OBJS): Add sim-main.o.
2180 * sim-main.h (address_translation, load_memory, store_memory,
2181 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2183 (pr_addr, pr_uword64): Declare.
2184 (sim-main.c): Include when H_REVEALS_MODULE_P.
2186 * interp.c (address_translation, load_memory, store_memory,
2187 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2189 * sim-main.c: To here. Fix compilation problems.
2191 * configure.in: Enable inlining.
2192 * configure: Re-config.
2194 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2196 * configure: Regenerated to track ../common/aclocal.m4 changes.
2198 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2200 * mips.igen: Include tx.igen.
2201 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2202 * tx.igen: New file, contains MADD and MADDU.
2204 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2205 the hardwired constant `7'.
2206 (store_memory): Ditto.
2207 (LOADDRMASK): Move definition to sim-main.h.
2209 mips.igen (MTC0): Enable for r3900.
2212 mips.igen (do_load_byte): Delete.
2213 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2214 do_store_right): New functions.
2215 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2217 configure.in: Let the tx39 use igen again.
2220 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2222 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2223 not an address sized quantity. Return zero for cache sizes.
2225 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2227 * mips.igen (r3900): r3900 does not support 64 bit integer
2230 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2232 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2234 * configure : Rebuild.
2236 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2238 * configure: Regenerated to track ../common/aclocal.m4 changes.
2240 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2242 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2244 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2246 * configure: Regenerated to track ../common/aclocal.m4 changes.
2247 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2249 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2251 * configure: Regenerated to track ../common/aclocal.m4 changes.
2253 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2255 * interp.c (Max, Min): Comment out functions. Not yet used.
2257 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2259 * configure: Regenerated to track ../common/aclocal.m4 changes.
2261 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2263 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2264 configurable settings for stand-alone simulator.
2266 * configure.in: Added X11 search, just in case.
2268 * configure: Regenerated.
2270 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2272 * interp.c (sim_write, sim_read, load_memory, store_memory):
2273 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2275 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2277 * sim-main.h (GETFCC): Return an unsigned value.
2279 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2281 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2282 (DADD): Result destination is RD not RT.
2284 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2286 * sim-main.h (HIACCESS, LOACCESS): Always define.
2288 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2290 * interp.c (sim_info): Delete.
2292 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2294 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2295 (mips_option_handler): New argument `cpu'.
2296 (sim_open): Update call to sim_add_option_table.
2298 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2300 * mips.igen (CxC1): Add tracing.
2302 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2304 * sim-main.h (Max, Min): Declare.
2306 * interp.c (Max, Min): New functions.
2308 * mips.igen (BC1): Add tracing.
2310 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
2312 * interp.c Added memory map for stack in vr4100
2314 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2316 * interp.c (load_memory): Add missing "break"'s.
2318 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2320 * interp.c (sim_store_register, sim_fetch_register): Pass in
2321 length parameter. Return -1.
2323 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2325 * interp.c: Added hardware init hook, fixed warnings.
2327 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2329 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2331 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2333 * interp.c (ifetch16): New function.
2335 * sim-main.h (IMEM32): Rename IMEM.
2336 (IMEM16_IMMED): Define.
2338 (DELAY_SLOT): Update.
2340 * m16run.c (sim_engine_run): New file.
2342 * m16.igen: All instructions except LB.
2343 (LB): Call do_load_byte.
2344 * mips.igen (do_load_byte): New function.
2345 (LB): Call do_load_byte.
2347 * mips.igen: Move spec for insn bit size and high bit from here.
2348 * Makefile.in (tmp-igen, tmp-m16): To here.
2350 * m16.dc: New file, decode mips16 instructions.
2352 * Makefile.in (SIM_NO_ALL): Define.
2353 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2355 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2357 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2358 point unit to 32 bit registers.
2359 * configure: Re-generate.
2361 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2363 * configure.in (sim_use_gen): Make IGEN the default simulator
2364 generator for generic 32 and 64 bit mips targets.
2365 * configure: Re-generate.
2367 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2369 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2372 * interp.c (sim_fetch_register, sim_store_register): Read/write
2373 FGR from correct location.
2374 (sim_open): Set size of FGR's according to
2375 WITH_TARGET_FLOATING_POINT_BITSIZE.
2377 * sim-main.h (FGR): Store floating point registers in a separate
2380 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2382 * configure: Regenerated to track ../common/aclocal.m4 changes.
2384 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2386 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2388 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2390 * interp.c (pending_tick): New function. Deliver pending writes.
2392 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2393 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2394 it can handle mixed sized quantites and single bits.
2396 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2398 * interp.c (oengine.h): Do not include when building with IGEN.
2399 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2400 (sim_info): Ditto for PROCESSOR_64BIT.
2401 (sim_monitor): Replace ut_reg with unsigned_word.
2402 (*): Ditto for t_reg.
2403 (LOADDRMASK): Define.
2404 (sim_open): Remove defunct check that host FP is IEEE compliant,
2405 using software to emulate floating point.
2406 (value_fpr, ...): Always compile, was conditional on HASFPU.
2408 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2410 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2413 * interp.c (SD, CPU): Define.
2414 (mips_option_handler): Set flags in each CPU.
2415 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2416 (sim_close): Do not clear STATE, deleted anyway.
2417 (sim_write, sim_read): Assume CPU zero's vm should be used for
2419 (sim_create_inferior): Set the PC for all processors.
2420 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2422 (mips16_entry): Pass correct nr of args to store_word, load_word.
2423 (ColdReset): Cold reset all cpu's.
2424 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2425 (sim_monitor, load_memory, store_memory, signal_exception): Use
2426 `CPU' instead of STATE_CPU.
2429 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2432 * sim-main.h (signal_exception): Add sim_cpu arg.
2433 (SignalException*): Pass both SD and CPU to signal_exception.
2434 * interp.c (signal_exception): Update.
2436 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2438 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2439 address_translation): Ditto
2440 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2442 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2444 * configure: Regenerated to track ../common/aclocal.m4 changes.
2446 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2448 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2450 * mips.igen (model): Map processor names onto BFD name.
2452 * sim-main.h (CPU_CIA): Delete.
2453 (SET_CIA, GET_CIA): Define
2455 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2457 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2460 * configure.in (default_endian): Configure a big-endian simulator
2462 * configure: Re-generate.
2464 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2466 * configure: Regenerated to track ../common/aclocal.m4 changes.
2468 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2470 * interp.c (sim_monitor): Handle Densan monitor outbyte
2471 and inbyte functions.
2473 1997-12-29 Felix Lee <flee@cygnus.com>
2475 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2477 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2479 * Makefile.in (tmp-igen): Arrange for $zero to always be
2480 reset to zero after every instruction.
2482 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2484 * configure: Regenerated to track ../common/aclocal.m4 changes.
2487 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2489 * mips.igen (MSUB): Fix to work like MADD.
2490 * gencode.c (MSUB): Similarly.
2492 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2494 * configure: Regenerated to track ../common/aclocal.m4 changes.
2496 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2498 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2500 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2502 * sim-main.h (sim-fpu.h): Include.
2504 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2505 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2506 using host independant sim_fpu module.
2508 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2510 * interp.c (signal_exception): Report internal errors with SIGABRT
2513 * sim-main.h (C0_CONFIG): New register.
2514 (signal.h): No longer include.
2516 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2518 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2520 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2522 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2524 * mips.igen: Tag vr5000 instructions.
2525 (ANDI): Was missing mipsIV model, fix assembler syntax.
2526 (do_c_cond_fmt): New function.
2527 (C.cond.fmt): Handle mips I-III which do not support CC field
2529 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2530 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2532 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2533 vr5000 which saves LO in a GPR separatly.
2535 * configure.in (enable-sim-igen): For vr5000, select vr5000
2536 specific instructions.
2537 * configure: Re-generate.
2539 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2541 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2543 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2544 fmt_uninterpreted_64 bit cases to switch. Convert to
2547 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2549 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2550 as specified in IV3.2 spec.
2551 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2553 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2555 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2556 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2557 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2558 PENDING_FILL versions of instructions. Simplify.
2560 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2562 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2564 (MTHI, MFHI): Disable code checking HI-LO.
2566 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2568 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2570 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2572 * gencode.c (build_mips16_operands): Replace IPC with cia.
2574 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2575 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2577 (UndefinedResult): Replace function with macro/function
2579 (sim_engine_run): Don't save PC in IPC.
2581 * sim-main.h (IPC): Delete.
2584 * interp.c (signal_exception, store_word, load_word,
2585 address_translation, load_memory, store_memory, cache_op,
2586 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2587 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2588 current instruction address - cia - argument.
2589 (sim_read, sim_write): Call address_translation directly.
2590 (sim_engine_run): Rename variable vaddr to cia.
2591 (signal_exception): Pass cia to sim_monitor
2593 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2594 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2595 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2597 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2598 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2601 * interp.c (signal_exception): Pass restart address to
2604 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2605 idecode.o): Add dependency.
2607 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2609 (DELAY_SLOT): Update NIA not PC with branch address.
2610 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2612 * mips.igen: Use CIA not PC in branch calculations.
2613 (illegal): Call SignalException.
2614 (BEQ, ADDIU): Fix assembler.
2616 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2618 * m16.igen (JALX): Was missing.
2620 * configure.in (enable-sim-igen): New configuration option.
2621 * configure: Re-generate.
2623 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2625 * interp.c (load_memory, store_memory): Delete parameter RAW.
2626 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2627 bypassing {load,store}_memory.
2629 * sim-main.h (ByteSwapMem): Delete definition.
2631 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2633 * interp.c (sim_do_command, sim_commands): Delete mips specific
2634 commands. Handled by module sim-options.
2636 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2637 (WITH_MODULO_MEMORY): Define.
2639 * interp.c (sim_info): Delete code printing memory size.
2641 * interp.c (mips_size): Nee sim_size, delete function.
2643 (monitor, monitor_base, monitor_size): Delete global variables.
2644 (sim_open, sim_close): Delete code creating monitor and other
2645 memory regions. Use sim-memopts module, via sim_do_commandf, to
2646 manage memory regions.
2647 (load_memory, store_memory): Use sim-core for memory model.
2649 * interp.c (address_translation): Delete all memory map code
2650 except line forcing 32 bit addresses.
2652 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2654 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2657 * interp.c (logfh, logfile): Delete globals.
2658 (sim_open, sim_close): Delete code opening & closing log file.
2659 (mips_option_handler): Delete -l and -n options.
2660 (OPTION mips_options): Ditto.
2662 * interp.c (OPTION mips_options): Rename option trace to dinero.
2663 (mips_option_handler): Update.
2665 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2667 * interp.c (fetch_str): New function.
2668 (sim_monitor): Rewrite using sim_read & sim_write.
2669 (sim_open): Check magic number.
2670 (sim_open): Write monitor vectors into memory using sim_write.
2671 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2672 (sim_read, sim_write): Simplify - transfer data one byte at a
2674 (load_memory, store_memory): Clarify meaning of parameter RAW.
2676 * sim-main.h (isHOST): Defete definition.
2677 (isTARGET): Mark as depreciated.
2678 (address_translation): Delete parameter HOST.
2680 * interp.c (address_translation): Delete parameter HOST.
2682 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2686 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2687 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2689 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2691 * mips.igen: Add model filter field to records.
2693 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2695 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2697 interp.c (sim_engine_run): Do not compile function sim_engine_run
2698 when WITH_IGEN == 1.
2700 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2701 target architecture.
2703 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2704 igen. Replace with configuration variables sim_igen_flags /
2707 * m16.igen: New file. Copy mips16 insns here.
2708 * mips.igen: From here.
2710 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2712 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2714 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2716 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2718 * gencode.c (build_instruction): Follow sim_write's lead in using
2719 BigEndianMem instead of !ByteSwapMem.
2721 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2723 * configure.in (sim_gen): Dependent on target, select type of
2724 generator. Always select old style generator.
2726 configure: Re-generate.
2728 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2730 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2731 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2732 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2733 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2734 SIM_@sim_gen@_*, set by autoconf.
2736 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2738 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2740 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2741 CURRENT_FLOATING_POINT instead.
2743 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2744 (address_translation): Raise exception InstructionFetch when
2745 translation fails and isINSTRUCTION.
2747 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2748 sim_engine_run): Change type of of vaddr and paddr to
2750 (address_translation, prefetch, load_memory, store_memory,
2751 cache_op): Change type of vAddr and pAddr to address_word.
2753 * gencode.c (build_instruction): Change type of vaddr and paddr to
2756 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2758 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2759 macro to obtain result of ALU op.
2761 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2763 * interp.c (sim_info): Call profile_print.
2765 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2767 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2769 * sim-main.h (WITH_PROFILE): Do not define, defined in
2770 common/sim-config.h. Use sim-profile module.
2771 (simPROFILE): Delete defintion.
2773 * interp.c (PROFILE): Delete definition.
2774 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2775 (sim_close): Delete code writing profile histogram.
2776 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2778 (sim_engine_run): Delete code profiling the PC.
2780 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2782 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2784 * interp.c (sim_monitor): Make register pointers of type
2787 * sim-main.h: Make registers of type unsigned_word not
2790 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2792 * interp.c (sync_operation): Rename from SyncOperation, make
2793 global, add SD argument.
2794 (prefetch): Rename from Prefetch, make global, add SD argument.
2795 (decode_coproc): Make global.
2797 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2799 * gencode.c (build_instruction): Generate DecodeCoproc not
2800 decode_coproc calls.
2802 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2803 (SizeFGR): Move to sim-main.h
2804 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2805 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2806 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2808 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2809 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2810 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2811 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2812 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2813 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2815 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2817 (sim-alu.h): Include.
2818 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2819 (sim_cia): Typedef to instruction_address.
2821 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2823 * Makefile.in (interp.o): Rename generated file engine.c to
2828 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2830 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2832 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2834 * gencode.c (build_instruction): For "FPSQRT", output correct
2835 number of arguments to Recip.
2837 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2839 * Makefile.in (interp.o): Depends on sim-main.h
2841 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2843 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2844 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2845 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2846 STATE, DSSTATE): Define
2847 (GPR, FGRIDX, ..): Define.
2849 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2850 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2851 (GPR, FGRIDX, ...): Delete macros.
2853 * interp.c: Update names to match defines from sim-main.h
2855 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2857 * interp.c (sim_monitor): Add SD argument.
2858 (sim_warning): Delete. Replace calls with calls to
2860 (sim_error): Delete. Replace calls with sim_io_error.
2861 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2862 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2863 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2865 (mips_size): Rename from sim_size. Add SD argument.
2867 * interp.c (simulator): Delete global variable.
2868 (callback): Delete global variable.
2869 (mips_option_handler, sim_open, sim_write, sim_read,
2870 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2871 sim_size,sim_monitor): Use sim_io_* not callback->*.
2872 (sim_open): ZALLOC simulator struct.
2873 (PROFILE): Do not define.
2875 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2877 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2878 support.h with corresponding code.
2880 * sim-main.h (word64, uword64), support.h: Move definition to
2882 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2885 * Makefile.in: Update dependencies
2886 * interp.c: Do not include.
2888 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2890 * interp.c (address_translation, load_memory, store_memory,
2891 cache_op): Rename to from AddressTranslation et.al., make global,
2894 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2897 * interp.c (SignalException): Rename to signal_exception, make
2900 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2902 * sim-main.h (SignalException, SignalExceptionInterrupt,
2903 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2904 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2905 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2908 * interp.c, support.h: Use.
2910 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2912 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2913 to value_fpr / store_fpr. Add SD argument.
2914 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2915 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2917 * sim-main.h (ValueFPR, StoreFPR): Define.
2919 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2921 * interp.c (sim_engine_run): Check consistency between configure
2922 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2925 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2926 (mips_fpu): Configure WITH_FLOATING_POINT.
2927 (mips_endian): Configure WITH_TARGET_ENDIAN.
2928 * configure: Update.
2930 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2932 * configure: Regenerated to track ../common/aclocal.m4 changes.
2934 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2936 * configure: Regenerated.
2938 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2940 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2942 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2944 * gencode.c (print_igen_insn_models): Assume certain architectures
2945 include all mips* instructions.
2946 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2949 * Makefile.in (tmp.igen): Add target. Generate igen input from
2952 * gencode.c (FEATURE_IGEN): Define.
2953 (main): Add --igen option. Generate output in igen format.
2954 (process_instructions): Format output according to igen option.
2955 (print_igen_insn_format): New function.
2956 (print_igen_insn_models): New function.
2957 (process_instructions): Only issue warnings and ignore
2958 instructions when no FEATURE_IGEN.
2960 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2962 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2965 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2967 * configure: Regenerated to track ../common/aclocal.m4 changes.
2969 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2971 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2972 SIM_RESERVED_BITS): Delete, moved to common.
2973 (SIM_EXTRA_CFLAGS): Update.
2975 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2977 * configure.in: Configure non-strict memory alignment.
2978 * configure: Regenerated to track ../common/aclocal.m4 changes.
2980 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2982 * configure: Regenerated to track ../common/aclocal.m4 changes.
2984 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2986 * gencode.c (SDBBP,DERET): Added (3900) insns.
2987 (RFE): Turn on for 3900.
2988 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2989 (dsstate): Made global.
2990 (SUBTARGET_R3900): Added.
2991 (CANCELDELAYSLOT): New.
2992 (SignalException): Ignore SystemCall rather than ignore and
2993 terminate. Add DebugBreakPoint handling.
2994 (decode_coproc): New insns RFE, DERET; and new registers Debug
2995 and DEPC protected by SUBTARGET_R3900.
2996 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2998 * Makefile.in,configure.in: Add mips subtarget option.
2999 * configure: Update.
3001 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3003 * gencode.c: Add r3900 (tx39).
3006 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3008 * gencode.c (build_instruction): Don't need to subtract 4 for
3011 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3013 * interp.c: Correct some HASFPU problems.
3015 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3017 * configure: Regenerated to track ../common/aclocal.m4 changes.
3019 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3021 * interp.c (mips_options): Fix samples option short form, should
3024 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3026 * interp.c (sim_info): Enable info code. Was just returning.
3028 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3030 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3033 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3035 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3037 (build_instruction): Ditto for LL.
3039 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3041 * configure: Regenerated to track ../common/aclocal.m4 changes.
3043 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3045 * configure: Regenerated to track ../common/aclocal.m4 changes.
3048 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3050 * interp.c (sim_open): Add call to sim_analyze_program, update
3053 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3055 * interp.c (sim_kill): Delete.
3056 (sim_create_inferior): Add ABFD argument. Set PC from same.
3057 (sim_load): Move code initializing trap handlers from here.
3058 (sim_open): To here.
3059 (sim_load): Delete, use sim-hload.c.
3061 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3063 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3065 * configure: Regenerated to track ../common/aclocal.m4 changes.
3068 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3070 * interp.c (sim_open): Add ABFD argument.
3071 (sim_load): Move call to sim_config from here.
3072 (sim_open): To here. Check return status.
3074 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
3076 * gencode.c (build_instruction): Two arg MADD should
3077 not assign result to $0.
3079 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3081 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3082 * sim/mips/configure.in: Regenerate.
3084 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3086 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3087 signed8, unsigned8 et.al. types.
3089 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3090 hosts when selecting subreg.
3092 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3094 * interp.c (sim_engine_run): Reset the ZERO register to zero
3095 regardless of FEATURE_WARN_ZERO.
3096 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3098 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3100 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3101 (SignalException): For BreakPoints ignore any mode bits and just
3103 (SignalException): Always set the CAUSE register.
3105 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3107 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3108 exception has been taken.
3110 * interp.c: Implement the ERET and mt/f sr instructions.
3112 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3114 * interp.c (SignalException): Don't bother restarting an
3117 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3119 * interp.c (SignalException): Really take an interrupt.
3120 (interrupt_event): Only deliver interrupts when enabled.
3122 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3124 * interp.c (sim_info): Only print info when verbose.
3125 (sim_info) Use sim_io_printf for output.
3127 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3129 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3132 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3134 * interp.c (sim_do_command): Check for common commands if a
3135 simulator specific command fails.
3137 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3139 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3140 and simBE when DEBUG is defined.
3142 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3144 * interp.c (interrupt_event): New function. Pass exception event
3145 onto exception handler.
3147 * configure.in: Check for stdlib.h.
3148 * configure: Regenerate.
3150 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3151 variable declaration.
3152 (build_instruction): Initialize memval1.
3153 (build_instruction): Add UNUSED attribute to byte, bigend,
3155 (build_operands): Ditto.
3157 * interp.c: Fix GCC warnings.
3158 (sim_get_quit_code): Delete.
3160 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3161 * Makefile.in: Ditto.
3162 * configure: Re-generate.
3164 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3166 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3168 * interp.c (mips_option_handler): New function parse argumes using
3170 (myname): Replace with STATE_MY_NAME.
3171 (sim_open): Delete check for host endianness - performed by
3173 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3174 (sim_open): Move much of the initialization from here.
3175 (sim_load): To here. After the image has been loaded and
3177 (sim_open): Move ColdReset from here.
3178 (sim_create_inferior): To here.
3179 (sim_open): Make FP check less dependant on host endianness.
3181 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3183 * interp.c (sim_set_callbacks): Delete.
3185 * interp.c (membank, membank_base, membank_size): Replace with
3186 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3187 (sim_open): Remove call to callback->init. gdb/run do this.
3191 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3193 * interp.c (big_endian_p): Delete, replaced by
3194 current_target_byte_order.
3196 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3198 * interp.c (host_read_long, host_read_word, host_swap_word,
3199 host_swap_long): Delete. Using common sim-endian.
3200 (sim_fetch_register, sim_store_register): Use H2T.
3201 (pipeline_ticks): Delete. Handled by sim-events.
3203 (sim_engine_run): Update.
3205 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3207 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3209 (SignalException): To here. Signal using sim_engine_halt.
3210 (sim_stop_reason): Delete, moved to common.
3212 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3214 * interp.c (sim_open): Add callback argument.
3215 (sim_set_callbacks): Delete SIM_DESC argument.
3218 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3220 * Makefile.in (SIM_OBJS): Add common modules.
3222 * interp.c (sim_set_callbacks): Also set SD callback.
3223 (set_endianness, xfer_*, swap_*): Delete.
3224 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3225 Change to functions using sim-endian macros.
3226 (control_c, sim_stop): Delete, use common version.
3227 (simulate): Convert into.
3228 (sim_engine_run): This function.
3229 (sim_resume): Delete.
3231 * interp.c (simulation): New variable - the simulator object.
3232 (sim_kind): Delete global - merged into simulation.
3233 (sim_load): Cleanup. Move PC assignment from here.
3234 (sim_create_inferior): To here.
3236 * sim-main.h: New file.
3237 * interp.c (sim-main.h): Include.
3239 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3241 * configure: Regenerated to track ../common/aclocal.m4 changes.
3243 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3245 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3247 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3249 * gencode.c (build_instruction): DIV instructions: check
3250 for division by zero and integer overflow before using
3251 host's division operation.
3253 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3255 * Makefile.in (SIM_OBJS): Add sim-load.o.
3256 * interp.c: #include bfd.h.
3257 (target_byte_order): Delete.
3258 (sim_kind, myname, big_endian_p): New static locals.
3259 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3260 after argument parsing. Recognize -E arg, set endianness accordingly.
3261 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3262 load file into simulator. Set PC from bfd.
3263 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3264 (set_endianness): Use big_endian_p instead of target_byte_order.
3266 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3268 * interp.c (sim_size): Delete prototype - conflicts with
3269 definition in remote-sim.h. Correct definition.
3271 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3273 * configure: Regenerated to track ../common/aclocal.m4 changes.
3276 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3278 * interp.c (sim_open): New arg `kind'.
3280 * configure: Regenerated to track ../common/aclocal.m4 changes.
3282 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3284 * configure: Regenerated to track ../common/aclocal.m4 changes.
3286 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3288 * interp.c (sim_open): Set optind to 0 before calling getopt.
3290 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3292 * configure: Regenerated to track ../common/aclocal.m4 changes.
3294 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3296 * interp.c : Replace uses of pr_addr with pr_uword64
3297 where the bit length is always 64 independent of SIM_ADDR.
3298 (pr_uword64) : added.
3300 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3302 * configure: Re-generate.
3304 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3306 * configure: Regenerate to track ../common/aclocal.m4 changes.
3308 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3310 * interp.c (sim_open): New SIM_DESC result. Argument is now
3312 (other sim_*): New SIM_DESC argument.
3314 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3316 * interp.c: Fix printing of addresses for non-64-bit targets.
3317 (pr_addr): Add function to print address based on size.
3319 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3321 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3323 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3325 * gencode.c (build_mips16_operands): Correct computation of base
3326 address for extended PC relative instruction.
3328 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3330 * interp.c (mips16_entry): Add support for floating point cases.
3331 (SignalException): Pass floating point cases to mips16_entry.
3332 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3334 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3336 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3337 and then set the state to fmt_uninterpreted.
3338 (COP_SW): Temporarily set the state to fmt_word while calling
3341 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3343 * gencode.c (build_instruction): The high order may be set in the
3344 comparison flags at any ISA level, not just ISA 4.
3346 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3348 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3349 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3350 * configure.in: sinclude ../common/aclocal.m4.
3351 * configure: Regenerated.
3353 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3355 * configure: Rebuild after change to aclocal.m4.
3357 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3359 * configure configure.in Makefile.in: Update to new configure
3360 scheme which is more compatible with WinGDB builds.
3361 * configure.in: Improve comment on how to run autoconf.
3362 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3363 * Makefile.in: Use autoconf substitution to install common
3366 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3368 * gencode.c (build_instruction): Use BigEndianCPU instead of
3371 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3373 * interp.c (sim_monitor): Make output to stdout visible in
3374 wingdb's I/O log window.
3376 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3378 * support.h: Undo previous change to SIGTRAP
3381 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3383 * interp.c (store_word, load_word): New static functions.
3384 (mips16_entry): New static function.
3385 (SignalException): Look for mips16 entry and exit instructions.
3386 (simulate): Use the correct index when setting fpr_state after
3387 doing a pending move.
3389 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3391 * interp.c: Fix byte-swapping code throughout to work on
3392 both little- and big-endian hosts.
3394 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3396 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3397 with gdb/config/i386/xm-windows.h.
3399 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3401 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3402 that messes up arithmetic shifts.
3404 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3406 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3407 SIGTRAP and SIGQUIT for _WIN32.
3409 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3411 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3412 force a 64 bit multiplication.
3413 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3414 destination register is 0, since that is the default mips16 nop
3417 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3419 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3420 (build_endian_shift): Don't check proc64.
3421 (build_instruction): Always set memval to uword64. Cast op2 to
3422 uword64 when shifting it left in memory instructions. Always use
3423 the same code for stores--don't special case proc64.
3425 * gencode.c (build_mips16_operands): Fix base PC value for PC
3427 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3429 * interp.c (simJALDELAYSLOT): Define.
3430 (JALDELAYSLOT): Define.
3431 (INDELAYSLOT, INJALDELAYSLOT): Define.
3432 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3434 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3436 * interp.c (sim_open): add flush_cache as a PMON routine
3437 (sim_monitor): handle flush_cache by ignoring it
3439 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3441 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3443 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3444 (BigEndianMem): Rename to ByteSwapMem and change sense.
3445 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3446 BigEndianMem references to !ByteSwapMem.
3447 (set_endianness): New function, with prototype.
3448 (sim_open): Call set_endianness.
3449 (sim_info): Use simBE instead of BigEndianMem.
3450 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3451 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3452 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3453 ifdefs, keeping the prototype declaration.
3454 (swap_word): Rewrite correctly.
3455 (ColdReset): Delete references to CONFIG. Delete endianness related
3456 code; moved to set_endianness.
3458 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3460 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3461 * interp.c (CHECKHILO): Define away.
3462 (simSIGINT): New macro.
3463 (membank_size): Increase from 1MB to 2MB.
3464 (control_c): New function.
3465 (sim_resume): Rename parameter signal to signal_number. Add local
3466 variable prev. Call signal before and after simulate.
3467 (sim_stop_reason): Add simSIGINT support.
3468 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3470 (sim_warning): Delete call to SignalException. Do call printf_filtered
3472 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3473 a call to sim_warning.
3475 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3477 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3478 16 bit instructions.
3480 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3482 Add support for mips16 (16 bit MIPS implementation):
3483 * gencode.c (inst_type): Add mips16 instruction encoding types.
3484 (GETDATASIZEINSN): Define.
3485 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3486 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3488 (MIPS16_DECODE): New table, for mips16 instructions.
3489 (bitmap_val): New static function.
3490 (struct mips16_op): Define.
3491 (mips16_op_table): New table, for mips16 operands.
3492 (build_mips16_operands): New static function.
3493 (process_instructions): If PC is odd, decode a mips16
3494 instruction. Break out instruction handling into new
3495 build_instruction function.
3496 (build_instruction): New static function, broken out of
3497 process_instructions. Check modifiers rather than flags for SHIFT
3498 bit count and m[ft]{hi,lo} direction.
3499 (usage): Pass program name to fprintf.
3500 (main): Remove unused variable this_option_optind. Change
3501 ``*loptarg++'' to ``loptarg++''.
3502 (my_strtoul): Parenthesize && within ||.
3503 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3504 (simulate): If PC is odd, fetch a 16 bit instruction, and
3505 increment PC by 2 rather than 4.
3506 * configure.in: Add case for mips16*-*-*.
3507 * configure: Rebuild.
3509 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3511 * interp.c: Allow -t to enable tracing in standalone simulator.
3512 Fix garbage output in trace file and error messages.
3514 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3516 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3517 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3518 * configure.in: Simplify using macros in ../common/aclocal.m4.
3519 * configure: Regenerated.
3520 * tconfig.in: New file.
3522 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3524 * interp.c: Fix bugs in 64-bit port.
3525 Use ansi function declarations for msvc compiler.
3526 Initialize and test file pointer in trace code.
3527 Prevent duplicate definition of LAST_EMED_REGNUM.
3529 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3531 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3533 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3535 * interp.c (SignalException): Check for explicit terminating
3537 * gencode.c: Pass instruction value through SignalException()
3538 calls for Trap, Breakpoint and Syscall.
3540 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3542 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3543 only used on those hosts that provide it.
3544 * configure.in: Add sqrt() to list of functions to be checked for.
3545 * config.in: Re-generated.
3546 * configure: Re-generated.
3548 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3550 * gencode.c (process_instructions): Call build_endian_shift when
3551 expanding STORE RIGHT, to fix swr.
3552 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3553 clear the high bits.
3554 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3555 Fix float to int conversions to produce signed values.
3557 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3559 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3560 (process_instructions): Correct handling of nor instruction.
3561 Correct shift count for 32 bit shift instructions. Correct sign
3562 extension for arithmetic shifts to not shift the number of bits in
3563 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3564 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3566 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3567 It's OK to have a mult follow a mult. What's not OK is to have a
3568 mult follow an mfhi.
3569 (Convert): Comment out incorrect rounding code.
3571 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3573 * interp.c (sim_monitor): Improved monitor printf
3574 simulation. Tidied up simulator warnings, and added "--log" option
3575 for directing warning message output.
3576 * gencode.c: Use sim_warning() rather than WARNING macro.
3578 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3580 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3581 getopt1.o, rather than on gencode.c. Link objects together.
3582 Don't link against -liberty.
3583 (gencode.o, getopt.o, getopt1.o): New targets.
3584 * gencode.c: Include <ctype.h> and "ansidecl.h".
3585 (AND): Undefine after including "ansidecl.h".
3586 (ULONG_MAX): Define if not defined.
3587 (OP_*): Don't define macros; now defined in opcode/mips.h.
3588 (main): Call my_strtoul rather than strtoul.
3589 (my_strtoul): New static function.
3591 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3593 * gencode.c (process_instructions): Generate word64 and uword64
3594 instead of `long long' and `unsigned long long' data types.
3595 * interp.c: #include sysdep.h to get signals, and define default
3597 * (Convert): Work around for Visual-C++ compiler bug with type
3599 * support.h: Make things compile under Visual-C++ by using
3600 __int64 instead of `long long'. Change many refs to long long
3601 into word64/uword64 typedefs.
3603 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3605 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3606 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3608 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3609 (AC_PROG_INSTALL): Added.
3610 (AC_PROG_CC): Moved to before configure.host call.
3611 * configure: Rebuilt.
3613 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3615 * configure.in: Define @SIMCONF@ depending on mips target.
3616 * configure: Rebuild.
3617 * Makefile.in (run): Add @SIMCONF@ to control simulator
3619 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3620 * interp.c: Remove some debugging, provide more detailed error
3621 messages, update memory accesses to use LOADDRMASK.
3623 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3625 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3626 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3628 * configure: Rebuild.
3629 * config.in: New file, generated by autoheader.
3630 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3631 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3632 HAVE_ANINT and HAVE_AINT, as appropriate.
3633 * Makefile.in (run): Use @LIBS@ rather than -lm.
3634 (interp.o): Depend upon config.h.
3635 (Makefile): Just rebuild Makefile.
3636 (clean): Remove stamp-h.
3637 (mostlyclean): Make the same as clean, not as distclean.
3638 (config.h, stamp-h): New targets.
3640 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3642 * interp.c (ColdReset): Fix boolean test. Make all simulator
3645 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3647 * interp.c (xfer_direct_word, xfer_direct_long,
3648 swap_direct_word, swap_direct_long, xfer_big_word,
3649 xfer_big_long, xfer_little_word, xfer_little_long,
3650 swap_word,swap_long): Added.
3651 * interp.c (ColdReset): Provide function indirection to
3652 host<->simulated_target transfer routines.
3653 * interp.c (sim_store_register, sim_fetch_register): Updated to
3654 make use of indirected transfer routines.
3656 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3658 * gencode.c (process_instructions): Ensure FP ABS instruction
3660 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3661 system call support.
3663 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3665 * interp.c (sim_do_command): Complain if callback structure not
3668 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3670 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3671 support for Sun hosts.
3672 * Makefile.in (gencode): Ensure the host compiler and libraries
3673 used for cross-hosted build.
3675 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3677 * interp.c, gencode.c: Some more (TODO) tidying.
3679 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3681 * gencode.c, interp.c: Replaced explicit long long references with
3682 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3683 * support.h (SET64LO, SET64HI): Macros added.
3685 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3687 * configure: Regenerate with autoconf 2.7.
3689 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3691 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3692 * support.h: Remove superfluous "1" from #if.
3693 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3695 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3697 * interp.c (StoreFPR): Control UndefinedResult() call on
3698 WARN_RESULT manifest.
3700 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3702 * gencode.c: Tidied instruction decoding, and added FP instruction
3705 * interp.c: Added dineroIII, and BSD profiling support. Also
3706 run-time FP handling.
3708 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3710 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3711 gencode.c, interp.c, support.h: created.