1 2014-08-15 Roland McGrath <mcgrathr@google.com>
3 * configure: Regenerate.
4 * config.in: Regenerate.
6 2014-03-04 Mike Frysinger <vapier@gentoo.org>
8 * configure: Regenerate.
10 2013-09-23 Alan Modra <amodra@gmail.com>
12 * configure: Regenerate.
14 2013-06-03 Mike Frysinger <vapier@gentoo.org>
16 * aclocal.m4, configure: Regenerate.
18 2013-05-10 Freddie Chopin <freddie_chopin@op.pl>
22 2013-03-26 Mike Frysinger <vapier@gentoo.org>
24 * configure: Regenerate.
26 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
28 * configure.ac: Address use of dv-sockser.o.
29 * tconfig.in: Conditionalize use of dv_sockser_install.
30 * configure: Regenerated.
31 * config.in: Regenerated.
33 2012-10-04 Chao-ying Fu <fu@mips.com>
34 Steve Ellcey <sellcey@mips.com>
36 * mips/mips3264r2.igen (rdhwr): New.
38 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
40 * configure.ac: Always link against dv-sockser.o.
41 * configure: Regenerate.
43 2012-06-15 Joel Brobecker <brobecker@adacore.com>
45 * config.in, configure: Regenerate.
47 2012-05-18 Nick Clifton <nickc@redhat.com>
50 * interp.c: Include config.h before system header files.
52 2012-03-24 Mike Frysinger <vapier@gentoo.org>
54 * aclocal.m4, config.in, configure: Regenerate.
56 2011-12-03 Mike Frysinger <vapier@gentoo.org>
58 * aclocal.m4: New file.
59 * configure: Regenerate.
61 2011-10-19 Mike Frysinger <vapier@gentoo.org>
63 * configure: Regenerate after common/acinclude.m4 update.
65 2011-10-17 Mike Frysinger <vapier@gentoo.org>
67 * configure.ac: Change include to common/acinclude.m4.
69 2011-10-17 Mike Frysinger <vapier@gentoo.org>
71 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
72 call. Replace common.m4 include with SIM_AC_COMMON.
73 * configure: Regenerate.
75 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
77 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
79 (tmp-mach-multi): Exit early when igen fails.
81 2011-07-05 Mike Frysinger <vapier@gentoo.org>
83 * interp.c (sim_do_command): Delete.
85 2011-02-14 Mike Frysinger <vapier@gentoo.org>
87 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
88 (tx3904sio_fifo_reset): Likewise.
89 * interp.c (sim_monitor): Likewise.
91 2010-04-14 Mike Frysinger <vapier@gentoo.org>
93 * interp.c (sim_write): Add const to buffer arg.
95 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
97 * interp.c: Don't include sysdep.h
99 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
101 * configure: Regenerate.
103 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
105 * config.in: Regenerate.
106 * configure: Likewise.
108 * configure: Regenerate.
110 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
112 * configure: Regenerate to track ../common/common.m4 changes.
115 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
116 Daniel Jacobowitz <dan@codesourcery.com>
117 Joseph Myers <joseph@codesourcery.com>
119 * configure: Regenerate.
121 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
123 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
124 that unconditionally allows fmt_ps.
125 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
126 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
127 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
128 filter from 64,f to 32,f.
129 (PREFX): Change filter from 64 to 32.
130 (LDXC1, LUXC1): Provide separate mips32r2 implementations
131 that use do_load_double instead of do_load. Make both LUXC1
132 versions unpredictable if SizeFGR () != 64.
133 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
134 instead of do_store. Remove unused variable. Make both SUXC1
135 versions unpredictable if SizeFGR () != 64.
137 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
139 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
140 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
141 shifts for that case.
143 2007-09-04 Nick Clifton <nickc@redhat.com>
145 * interp.c (options enum): Add OPTION_INFO_MEMORY.
146 (display_mem_info): New static variable.
147 (mips_option_handler): Handle OPTION_INFO_MEMORY.
148 (mips_options): Add info-memory and memory-info.
149 (sim_open): After processing the command line and board
150 specification, check display_mem_info. If it is set then
151 call the real handler for the --memory-info command line
154 2007-08-24 Joel Brobecker <brobecker@adacore.com>
156 * configure.ac: Change license of multi-run.c to GPL version 3.
157 * configure: Regenerate.
159 2007-06-28 Richard Sandiford <richard@codesourcery.com>
161 * configure.ac, configure: Revert last patch.
163 2007-06-26 Richard Sandiford <richard@codesourcery.com>
165 * configure.ac (sim_mipsisa3264_configs): New variable.
166 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
167 every configuration support all four targets, using the triplet to
168 determine the default.
169 * configure: Regenerate.
171 2007-06-25 Richard Sandiford <richard@codesourcery.com>
173 * Makefile.in (m16run.o): New rule.
175 2007-05-15 Thiemo Seufer <ths@mips.com>
177 * mips3264r2.igen (DSHD): Fix compile warning.
179 2007-05-14 Thiemo Seufer <ths@mips.com>
181 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
182 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
183 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
184 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
187 2007-03-01 Thiemo Seufer <ths@mips.com>
189 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
192 2007-02-20 Thiemo Seufer <ths@mips.com>
194 * dsp.igen: Update copyright notice.
195 * dsp2.igen: Fix copyright notice.
197 2007-02-20 Thiemo Seufer <ths@mips.com>
198 Chao-Ying Fu <fu@mips.com>
200 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
201 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
202 Add dsp2 to sim_igen_machine.
203 * configure: Regenerate.
204 * dsp.igen (do_ph_op): Add MUL support when op = 2.
205 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
206 (mulq_rs.ph): Use do_ph_mulq.
207 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
208 * mips.igen: Add dsp2 model and include dsp2.igen.
209 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
210 for *mips32r2, *mips64r2, *dsp.
211 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
212 for *mips32r2, *mips64r2, *dsp2.
213 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
215 2007-02-19 Thiemo Seufer <ths@mips.com>
216 Nigel Stephens <nigel@mips.com>
218 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
219 jumps with hazard barrier.
221 2007-02-19 Thiemo Seufer <ths@mips.com>
222 Nigel Stephens <nigel@mips.com>
224 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
225 after each call to sim_io_write.
227 2007-02-19 Thiemo Seufer <ths@mips.com>
228 Nigel Stephens <nigel@mips.com>
230 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
231 supported by this simulator.
232 (decode_coproc): Recognise additional CP0 Config registers
235 2007-02-19 Thiemo Seufer <ths@mips.com>
236 Nigel Stephens <nigel@mips.com>
237 David Ung <davidu@mips.com>
239 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
240 uninterpreted formats. If fmt is one of the uninterpreted types
241 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
242 fmt_word, and fmt_uninterpreted_64 like fmt_long.
243 (store_fpr): When writing an invalid odd register, set the
244 matching even register to fmt_unknown, not the following register.
245 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
246 the the memory window at offset 0 set by --memory-size command
248 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
250 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
252 (sim_monitor): When returning the memory size to the MIPS
253 application, use the value in STATE_MEM_SIZE, not an arbitrary
255 (cop_lw): Don' mess around with FPR_STATE, just pass
256 fmt_uninterpreted_32 to StoreFPR.
258 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
260 * mips.igen (not_word_value): Single version for mips32, mips64
263 2007-02-19 Thiemo Seufer <ths@mips.com>
264 Nigel Stephens <nigel@mips.com>
266 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
269 2007-02-17 Thiemo Seufer <ths@mips.com>
271 * configure.ac (mips*-sde-elf*): Move in front of generic machine
273 * configure: Regenerate.
275 2007-02-17 Thiemo Seufer <ths@mips.com>
277 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
278 Add mdmx to sim_igen_machine.
279 (mipsisa64*-*-*): Likewise. Remove dsp.
280 (mipsisa32*-*-*): Remove dsp.
281 * configure: Regenerate.
283 2007-02-13 Thiemo Seufer <ths@mips.com>
285 * configure.ac: Add mips*-sde-elf* target.
286 * configure: Regenerate.
288 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
290 * acconfig.h: Remove.
291 * config.in, configure: Regenerate.
293 2006-11-07 Thiemo Seufer <ths@mips.com>
295 * dsp.igen (do_w_op): Fix compiler warning.
297 2006-08-29 Thiemo Seufer <ths@mips.com>
298 David Ung <davidu@mips.com>
300 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
302 * configure: Regenerate.
303 * mips.igen (model): Add smartmips.
304 (MADDU): Increment ACX if carry.
305 (do_mult): Clear ACX.
306 (ROR,RORV): Add smartmips.
307 (include): Include smartmips.igen.
308 * sim-main.h (ACX): Set to REGISTERS[89].
309 * smartmips.igen: New file.
311 2006-08-29 Thiemo Seufer <ths@mips.com>
312 David Ung <davidu@mips.com>
314 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
315 mips3264r2.igen. Add missing dependency rules.
316 * m16e.igen: Support for mips16e save/restore instructions.
318 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
320 * configure: Regenerated.
322 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
324 * configure: Regenerated.
326 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
328 * configure: Regenerated.
330 2006-05-15 Chao-ying Fu <fu@mips.com>
332 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
334 2006-04-18 Nick Clifton <nickc@redhat.com>
336 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
339 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
341 * configure: Regenerate.
343 2005-12-14 Chao-ying Fu <fu@mips.com>
345 * Makefile.in (SIM_OBJS): Add dsp.o.
346 (dsp.o): New dependency.
347 (IGEN_INCLUDE): Add dsp.igen.
348 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
349 mipsisa64*-*-*): Add dsp to sim_igen_machine.
350 * configure: Regenerate.
351 * mips.igen: Add dsp model and include dsp.igen.
352 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
353 because these instructions are extended in DSP ASE.
354 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
355 adding 6 DSP accumulator registers and 1 DSP control register.
356 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
357 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
358 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
359 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
360 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
361 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
362 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
363 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
364 DSPCR_CCOND_SMASK): New define.
365 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
366 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
368 2005-07-08 Ian Lance Taylor <ian@airs.com>
370 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
372 2005-06-16 David Ung <davidu@mips.com>
373 Nigel Stephens <nigel@mips.com>
375 * mips.igen: New mips16e model and include m16e.igen.
376 (check_u64): Add mips16e tag.
377 * m16e.igen: New file for MIPS16e instructions.
378 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
379 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
381 * configure: Regenerate.
383 2005-05-26 David Ung <davidu@mips.com>
385 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
386 tags to all instructions which are applicable to the new ISAs.
387 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
389 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
391 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
393 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
394 * configure: Regenerate.
396 2005-03-23 Mark Kettenis <kettenis@gnu.org>
398 * configure: Regenerate.
400 2005-01-14 Andrew Cagney <cagney@gnu.org>
402 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
403 explicit call to AC_CONFIG_HEADER.
404 * configure: Regenerate.
406 2005-01-12 Andrew Cagney <cagney@gnu.org>
408 * configure.ac: Update to use ../common/common.m4.
409 * configure: Re-generate.
411 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
413 * configure: Regenerated to track ../common/aclocal.m4 changes.
415 2005-01-07 Andrew Cagney <cagney@gnu.org>
417 * configure.ac: Rename configure.in, require autoconf 2.59.
418 * configure: Re-generate.
420 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
422 * configure: Regenerate for ../common/aclocal.m4 update.
424 2004-09-24 Monika Chaddha <monika@acmet.com>
426 Committed by Andrew Cagney.
427 * m16.igen (CMP, CMPI): Fix assembler.
429 2004-08-18 Chris Demetriou <cgd@broadcom.com>
431 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
432 * configure: Regenerate.
434 2004-06-25 Chris Demetriou <cgd@broadcom.com>
436 * configure.in (sim_m16_machine): Include mipsIII.
437 * configure: Regenerate.
439 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
441 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
443 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
445 2004-04-10 Chris Demetriou <cgd@broadcom.com>
447 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
449 2004-04-09 Chris Demetriou <cgd@broadcom.com>
451 * mips.igen (check_fmt): Remove.
452 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
453 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
454 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
455 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
456 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
457 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
458 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
459 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
460 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
461 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
463 2004-04-09 Chris Demetriou <cgd@broadcom.com>
465 * sb1.igen (check_sbx): New function.
466 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
468 2004-03-29 Chris Demetriou <cgd@broadcom.com>
469 Richard Sandiford <rsandifo@redhat.com>
471 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
472 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
473 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
474 separate implementations for mipsIV and mipsV. Use new macros to
475 determine whether the restrictions apply.
477 2004-01-19 Chris Demetriou <cgd@broadcom.com>
479 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
480 (check_mult_hilo): Improve comments.
481 (check_div_hilo): Likewise. Also, fork off a new version
482 to handle mips32/mips64 (since there are no hazards to check
485 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
487 * mips.igen (do_dmultx): Fix check for negative operands.
489 2003-05-16 Ian Lance Taylor <ian@airs.com>
491 * Makefile.in (SHELL): Make sure this is defined.
492 (various): Use $(SHELL) whenever we invoke move-if-change.
494 2003-05-03 Chris Demetriou <cgd@broadcom.com>
496 * cp1.c: Tweak attribution slightly.
499 * mdmx.igen: Likewise.
500 * mips3d.igen: Likewise.
501 * sb1.igen: Likewise.
503 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
505 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
508 2003-02-27 Andrew Cagney <cagney@redhat.com>
510 * interp.c (sim_open): Rename _bfd to bfd.
511 (sim_create_inferior): Ditto.
513 2003-01-14 Chris Demetriou <cgd@broadcom.com>
515 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
517 2003-01-14 Chris Demetriou <cgd@broadcom.com>
519 * mips.igen (EI, DI): Remove.
521 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
523 * Makefile.in (tmp-run-multi): Fix mips16 filter.
525 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
526 Andrew Cagney <ac131313@redhat.com>
527 Gavin Romig-Koch <gavin@redhat.com>
528 Graydon Hoare <graydon@redhat.com>
529 Aldy Hernandez <aldyh@redhat.com>
530 Dave Brolley <brolley@redhat.com>
531 Chris Demetriou <cgd@broadcom.com>
533 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
534 (sim_mach_default): New variable.
535 (mips64vr-*-*, mips64vrel-*-*): New configurations.
536 Add a new simulator generator, MULTI.
537 * configure: Regenerate.
538 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
539 (multi-run.o): New dependency.
540 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
541 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
542 (tmp-multi): Combine them.
543 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
544 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
545 (distclean-extra): New rule.
546 * sim-main.h: Include bfd.h.
547 (MIPS_MACH): New macro.
548 * mips.igen (vr4120, vr5400, vr5500): New models.
549 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
550 * vr.igen: Replace with new version.
552 2003-01-04 Chris Demetriou <cgd@broadcom.com>
554 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
555 * configure: Regenerate.
557 2002-12-31 Chris Demetriou <cgd@broadcom.com>
559 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
560 * mips.igen: Remove all invocations of check_branch_bug and
563 2002-12-16 Chris Demetriou <cgd@broadcom.com>
565 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
567 2002-07-30 Chris Demetriou <cgd@broadcom.com>
569 * mips.igen (do_load_double, do_store_double): New functions.
570 (LDC1, SDC1): Rename to...
571 (LDC1b, SDC1b): respectively.
572 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
574 2002-07-29 Michael Snyder <msnyder@redhat.com>
576 * cp1.c (fp_recip2): Modify initialization expression so that
577 GCC will recognize it as constant.
579 2002-06-18 Chris Demetriou <cgd@broadcom.com>
581 * mdmx.c (SD_): Delete.
582 (Unpredictable): Re-define, for now, to directly invoke
583 unpredictable_action().
584 (mdmx_acc_op): Fix error in .ob immediate handling.
586 2002-06-18 Andrew Cagney <cagney@redhat.com>
588 * interp.c (sim_firmware_command): Initialize `address'.
590 2002-06-16 Andrew Cagney <ac131313@redhat.com>
592 * configure: Regenerated to track ../common/aclocal.m4 changes.
594 2002-06-14 Chris Demetriou <cgd@broadcom.com>
595 Ed Satterthwaite <ehs@broadcom.com>
597 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
598 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
599 * mips.igen: Include mips3d.igen.
600 (mips3d): New model name for MIPS-3D ASE instructions.
601 (CVT.W.fmt): Don't use this instruction for word (source) format
603 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
604 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
605 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
606 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
607 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
608 (RSquareRoot1, RSquareRoot2): New macros.
609 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
610 (fp_rsqrt2): New functions.
611 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
612 * configure: Regenerate.
614 2002-06-13 Chris Demetriou <cgd@broadcom.com>
615 Ed Satterthwaite <ehs@broadcom.com>
617 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
618 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
619 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
620 (convert): Note that this function is not used for paired-single
622 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
623 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
624 (check_fmt_p): Enable paired-single support.
625 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
626 (PUU.PS): New instructions.
627 (CVT.S.fmt): Don't use this instruction for paired-single format
629 * sim-main.h (FP_formats): New value 'fmt_ps.'
630 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
631 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
633 2002-06-12 Chris Demetriou <cgd@broadcom.com>
635 * mips.igen: Fix formatting of function calls in
638 2002-06-12 Chris Demetriou <cgd@broadcom.com>
640 * mips.igen (MOVN, MOVZ): Trace result.
641 (TNEI): Print "tnei" as the opcode name in traces.
642 (CEIL.W): Add disassembly string for traces.
643 (RSQRT.fmt): Make location of disassembly string consistent
644 with other instructions.
646 2002-06-12 Chris Demetriou <cgd@broadcom.com>
648 * mips.igen (X): Delete unused function.
650 2002-06-08 Andrew Cagney <cagney@redhat.com>
652 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
654 2002-06-07 Chris Demetriou <cgd@broadcom.com>
655 Ed Satterthwaite <ehs@broadcom.com>
657 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
658 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
659 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
660 (fp_nmsub): New prototypes.
661 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
662 (NegMultiplySub): New defines.
663 * mips.igen (RSQRT.fmt): Use RSquareRoot().
664 (MADD.D, MADD.S): Replace with...
665 (MADD.fmt): New instruction.
666 (MSUB.D, MSUB.S): Replace with...
667 (MSUB.fmt): New instruction.
668 (NMADD.D, NMADD.S): Replace with...
669 (NMADD.fmt): New instruction.
670 (NMSUB.D, MSUB.S): Replace with...
671 (NMSUB.fmt): New instruction.
673 2002-06-07 Chris Demetriou <cgd@broadcom.com>
674 Ed Satterthwaite <ehs@broadcom.com>
676 * cp1.c: Fix more comment spelling and formatting.
677 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
678 (denorm_mode): New function.
679 (fpu_unary, fpu_binary): Round results after operation, collect
680 status from rounding operations, and update the FCSR.
681 (convert): Collect status from integer conversions and rounding
682 operations, and update the FCSR. Adjust NaN values that result
683 from conversions. Convert to use sim_io_eprintf rather than
684 fprintf, and remove some debugging code.
685 * cp1.h (fenr_FS): New define.
687 2002-06-07 Chris Demetriou <cgd@broadcom.com>
689 * cp1.c (convert): Remove unusable debugging code, and move MIPS
690 rounding mode to sim FP rounding mode flag conversion code into...
691 (rounding_mode): New function.
693 2002-06-07 Chris Demetriou <cgd@broadcom.com>
695 * cp1.c: Clean up formatting of a few comments.
696 (value_fpr): Reformat switch statement.
698 2002-06-06 Chris Demetriou <cgd@broadcom.com>
699 Ed Satterthwaite <ehs@broadcom.com>
702 * sim-main.h: Include cp1.h.
703 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
704 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
705 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
706 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
707 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
708 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
709 * cp1.c: Don't include sim-fpu.h; already included by
710 sim-main.h. Clean up formatting of some comments.
711 (NaN, Equal, Less): Remove.
712 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
713 (fp_cmp): New functions.
714 * mips.igen (do_c_cond_fmt): Remove.
715 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
716 Compare. Add result tracing.
717 (CxC1): Remove, replace with...
718 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
719 (DMxC1): Remove, replace with...
720 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
721 (MxC1): Remove, replace with...
722 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
724 2002-06-04 Chris Demetriou <cgd@broadcom.com>
726 * sim-main.h (FGRIDX): Remove, replace all uses with...
727 (FGR_BASE): New macro.
728 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
729 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
730 (NR_FGR, FGR): Likewise.
731 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
732 * mips.igen: Likewise.
734 2002-06-04 Chris Demetriou <cgd@broadcom.com>
736 * cp1.c: Add an FSF Copyright notice to this file.
738 2002-06-04 Chris Demetriou <cgd@broadcom.com>
739 Ed Satterthwaite <ehs@broadcom.com>
741 * cp1.c (Infinity): Remove.
742 * sim-main.h (Infinity): Likewise.
744 * cp1.c (fp_unary, fp_binary): New functions.
745 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
746 (fp_sqrt): New functions, implemented in terms of the above.
747 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
748 (Recip, SquareRoot): Remove (replaced by functions above).
749 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
750 (fp_recip, fp_sqrt): New prototypes.
751 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
752 (Recip, SquareRoot): Replace prototypes with #defines which
753 invoke the functions above.
755 2002-06-03 Chris Demetriou <cgd@broadcom.com>
757 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
758 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
759 file, remove PARAMS from prototypes.
760 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
761 simulator state arguments.
762 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
763 pass simulator state arguments.
764 * cp1.c (SD): Redefine as CPU_STATE(cpu).
765 (store_fpr, convert): Remove 'sd' argument.
766 (value_fpr): Likewise. Convert to use 'SD' instead.
768 2002-06-03 Chris Demetriou <cgd@broadcom.com>
770 * cp1.c (Min, Max): Remove #if 0'd functions.
771 * sim-main.h (Min, Max): Remove.
773 2002-06-03 Chris Demetriou <cgd@broadcom.com>
775 * cp1.c: fix formatting of switch case and default labels.
776 * interp.c: Likewise.
777 * sim-main.c: Likewise.
779 2002-06-03 Chris Demetriou <cgd@broadcom.com>
781 * cp1.c: Clean up comments which describe FP formats.
782 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
784 2002-06-03 Chris Demetriou <cgd@broadcom.com>
785 Ed Satterthwaite <ehs@broadcom.com>
787 * configure.in (mipsisa64sb1*-*-*): New target for supporting
788 Broadcom SiByte SB-1 processor configurations.
789 * configure: Regenerate.
790 * sb1.igen: New file.
791 * mips.igen: Include sb1.igen.
793 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
794 * mdmx.igen: Add "sb1" model to all appropriate functions and
796 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
797 (ob_func, ob_acc): Reference the above.
798 (qh_acc): Adjust to keep the same size as ob_acc.
799 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
800 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
802 2002-06-03 Chris Demetriou <cgd@broadcom.com>
804 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
806 2002-06-02 Chris Demetriou <cgd@broadcom.com>
807 Ed Satterthwaite <ehs@broadcom.com>
809 * mips.igen (mdmx): New (pseudo-)model.
810 * mdmx.c, mdmx.igen: New files.
811 * Makefile.in (SIM_OBJS): Add mdmx.o.
812 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
814 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
815 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
816 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
817 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
818 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
819 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
820 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
821 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
822 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
823 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
824 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
825 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
826 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
827 (qh_fmtsel): New macros.
828 (_sim_cpu): New member "acc".
829 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
830 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
832 2002-05-01 Chris Demetriou <cgd@broadcom.com>
834 * interp.c: Use 'deprecated' rather than 'depreciated.'
835 * sim-main.h: Likewise.
837 2002-05-01 Chris Demetriou <cgd@broadcom.com>
839 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
840 which wouldn't compile anyway.
841 * sim-main.h (unpredictable_action): New function prototype.
842 (Unpredictable): Define to call igen function unpredictable().
843 (NotWordValue): New macro to call igen function not_word_value().
844 (UndefinedResult): Remove.
845 * interp.c (undefined_result): Remove.
846 (unpredictable_action): New function.
847 * mips.igen (not_word_value, unpredictable): New functions.
848 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
849 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
850 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
851 NotWordValue() to check for unpredictable inputs, then
852 Unpredictable() to handle them.
854 2002-02-24 Chris Demetriou <cgd@broadcom.com>
856 * mips.igen: Fix formatting of calls to Unpredictable().
858 2002-04-20 Andrew Cagney <ac131313@redhat.com>
860 * interp.c (sim_open): Revert previous change.
862 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
864 * interp.c (sim_open): Disable chunk of code that wrote code in
865 vector table entries.
867 2002-03-19 Chris Demetriou <cgd@broadcom.com>
869 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
870 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
873 2002-03-19 Chris Demetriou <cgd@broadcom.com>
875 * cp1.c: Fix many formatting issues.
877 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
879 * cp1.c (fpu_format_name): New function to replace...
880 (DOFMT): This. Delete, and update all callers.
881 (fpu_rounding_mode_name): New function to replace...
882 (RMMODE): This. Delete, and update all callers.
884 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
886 * interp.c: Move FPU support routines from here to...
887 * cp1.c: Here. New file.
888 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
891 2002-03-12 Chris Demetriou <cgd@broadcom.com>
893 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
894 * mips.igen (mips32, mips64): New models, add to all instructions
895 and functions as appropriate.
896 (loadstore_ea, check_u64): New variant for model mips64.
897 (check_fmt_p): New variant for models mipsV and mips64, remove
898 mipsV model marking fro other variant.
901 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
902 for mips32 and mips64.
903 (DCLO, DCLZ): New instructions for mips64.
905 2002-03-07 Chris Demetriou <cgd@broadcom.com>
907 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
908 immediate or code as a hex value with the "%#lx" format.
909 (ANDI): Likewise, and fix printed instruction name.
911 2002-03-05 Chris Demetriou <cgd@broadcom.com>
913 * sim-main.h (UndefinedResult, Unpredictable): New macros
914 which currently do nothing.
916 2002-03-05 Chris Demetriou <cgd@broadcom.com>
918 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
919 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
920 (status_CU3): New definitions.
922 * sim-main.h (ExceptionCause): Add new values for MIPS32
923 and MIPS64: MDMX, MCheck, CacheErr. Update comments
924 for DebugBreakPoint and NMIReset to note their status in
926 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
927 (SignalExceptionCacheErr): New exception macros.
929 2002-03-05 Chris Demetriou <cgd@broadcom.com>
931 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
932 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
934 (SignalExceptionCoProcessorUnusable): Take as argument the
935 unusable coprocessor number.
937 2002-03-05 Chris Demetriou <cgd@broadcom.com>
939 * mips.igen: Fix formatting of all SignalException calls.
941 2002-03-05 Chris Demetriou <cgd@broadcom.com>
943 * sim-main.h (SIGNEXTEND): Remove.
945 2002-03-04 Chris Demetriou <cgd@broadcom.com>
947 * mips.igen: Remove gencode comment from top of file, fix
948 spelling in another comment.
950 2002-03-04 Chris Demetriou <cgd@broadcom.com>
952 * mips.igen (check_fmt, check_fmt_p): New functions to check
953 whether specific floating point formats are usable.
954 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
955 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
956 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
957 Use the new functions.
958 (do_c_cond_fmt): Remove format checks...
959 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
961 2002-03-03 Chris Demetriou <cgd@broadcom.com>
963 * mips.igen: Fix formatting of check_fpu calls.
965 2002-03-03 Chris Demetriou <cgd@broadcom.com>
967 * mips.igen (FLOOR.L.fmt): Store correct destination register.
969 2002-03-03 Chris Demetriou <cgd@broadcom.com>
971 * mips.igen: Remove whitespace at end of lines.
973 2002-03-02 Chris Demetriou <cgd@broadcom.com>
975 * mips.igen (loadstore_ea): New function to do effective
976 address calculations.
977 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
978 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
979 CACHE): Use loadstore_ea to do effective address computations.
981 2002-03-02 Chris Demetriou <cgd@broadcom.com>
983 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
984 * mips.igen (LL, CxC1, MxC1): Likewise.
986 2002-03-02 Chris Demetriou <cgd@broadcom.com>
988 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
989 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
990 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
991 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
992 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
993 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
994 Don't split opcode fields by hand, use the opcode field values
997 2002-03-01 Chris Demetriou <cgd@broadcom.com>
999 * mips.igen (do_divu): Fix spacing.
1001 * mips.igen (do_dsllv): Move to be right before DSLLV,
1002 to match the rest of the do_<shift> functions.
1004 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1006 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1007 DSRL32, do_dsrlv): Trace inputs and results.
1009 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1011 * mips.igen (CACHE): Provide instruction-printing string.
1013 * interp.c (signal_exception): Comment tokens after #endif.
1015 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1017 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1018 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1019 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1020 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1021 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1022 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1023 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1024 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1026 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1028 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1029 instruction-printing string.
1030 (LWU): Use '64' as the filter flag.
1032 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1034 * mips.igen (SDXC1): Fix instruction-printing string.
1036 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1038 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1039 filter flags "32,f".
1041 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1043 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1046 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1048 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1049 add a comma) so that it more closely match the MIPS ISA
1050 documentation opcode partitioning.
1051 (PREF): Put useful names on opcode fields, and include
1052 instruction-printing string.
1054 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1056 * mips.igen (check_u64): New function which in the future will
1057 check whether 64-bit instructions are usable and signal an
1058 exception if not. Currently a no-op.
1059 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1060 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1061 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1062 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1064 * mips.igen (check_fpu): New function which in the future will
1065 check whether FPU instructions are usable and signal an exception
1066 if not. Currently a no-op.
1067 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1068 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1069 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1070 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1071 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1072 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1073 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1074 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1076 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1078 * mips.igen (do_load_left, do_load_right): Move to be immediately
1080 (do_store_left, do_store_right): Move to be immediately following
1083 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1085 * mips.igen (mipsV): New model name. Also, add it to
1086 all instructions and functions where it is appropriate.
1088 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1090 * mips.igen: For all functions and instructions, list model
1091 names that support that instruction one per line.
1093 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1095 * mips.igen: Add some additional comments about supported
1096 models, and about which instructions go where.
1097 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1098 order as is used in the rest of the file.
1100 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1102 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1103 indicating that ALU32_END or ALU64_END are there to check
1105 (DADD): Likewise, but also remove previous comment about
1108 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1110 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1111 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1112 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1113 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1114 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1115 fields (i.e., add and move commas) so that they more closely
1116 match the MIPS ISA documentation opcode partitioning.
1118 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1120 * mips.igen (ADDI): Print immediate value.
1121 (BREAK): Print code.
1122 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1123 (SLL): Print "nop" specially, and don't run the code
1124 that does the shift for the "nop" case.
1126 2001-11-17 Fred Fish <fnf@redhat.com>
1128 * sim-main.h (float_operation): Move enum declaration outside
1129 of _sim_cpu struct declaration.
1131 2001-04-12 Jim Blandy <jimb@redhat.com>
1133 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1134 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1136 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1137 PENDING_FILL, and you can get the intended effect gracefully by
1138 calling PENDING_SCHED directly.
1140 2001-02-23 Ben Elliston <bje@redhat.com>
1142 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1143 already defined elsewhere.
1145 2001-02-19 Ben Elliston <bje@redhat.com>
1147 * sim-main.h (sim_monitor): Return an int.
1148 * interp.c (sim_monitor): Add return values.
1149 (signal_exception): Handle error conditions from sim_monitor.
1151 2001-02-08 Ben Elliston <bje@redhat.com>
1153 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1154 (store_memory): Likewise, pass cia to sim_core_write*.
1156 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1158 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1159 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1161 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1163 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1164 * Makefile.in: Don't delete *.igen when cleaning directory.
1166 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1168 * m16.igen (break): Call SignalException not sim_engine_halt.
1170 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1172 From Jason Eckhardt:
1173 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1175 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1177 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1179 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1181 * mips.igen (do_dmultx): Fix typo.
1183 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1185 * configure: Regenerated to track ../common/aclocal.m4 changes.
1187 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1189 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1191 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1193 * sim-main.h (GPR_CLEAR): Define macro.
1195 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1197 * interp.c (decode_coproc): Output long using %lx and not %s.
1199 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1201 * interp.c (sim_open): Sort & extend dummy memory regions for
1202 --board=jmr3904 for eCos.
1204 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1206 * configure: Regenerated.
1208 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1210 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1211 calls, conditional on the simulator being in verbose mode.
1213 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1215 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1216 cache don't get ReservedInstruction traps.
1218 1999-11-29 Mark Salter <msalter@cygnus.com>
1220 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1221 to clear status bits in sdisr register. This is how the hardware works.
1223 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1224 being used by cygmon.
1226 1999-11-11 Andrew Haley <aph@cygnus.com>
1228 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1231 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1233 * mips.igen (MULT): Correct previous mis-applied patch.
1235 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1237 * mips.igen (delayslot32): Handle sequence like
1238 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1239 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1240 (MULT): Actually pass the third register...
1242 1999-09-03 Mark Salter <msalter@cygnus.com>
1244 * interp.c (sim_open): Added more memory aliases for additional
1245 hardware being touched by cygmon on jmr3904 board.
1247 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1249 * configure: Regenerated to track ../common/aclocal.m4 changes.
1251 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1253 * interp.c (sim_store_register): Handle case where client - GDB -
1254 specifies that a 4 byte register is 8 bytes in size.
1255 (sim_fetch_register): Ditto.
1257 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1259 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1260 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1261 (idt_monitor_base): Base address for IDT monitor traps.
1262 (pmon_monitor_base): Ditto for PMON.
1263 (lsipmon_monitor_base): Ditto for LSI PMON.
1264 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1265 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1266 (sim_firmware_command): New function.
1267 (mips_option_handler): Call it for OPTION_FIRMWARE.
1268 (sim_open): Allocate memory for idt_monitor region. If "--board"
1269 option was given, add no monitor by default. Add BREAK hooks only if
1270 monitors are also there.
1272 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1274 * interp.c (sim_monitor): Flush output before reading input.
1276 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1278 * tconfig.in (SIM_HANDLES_LMA): Always define.
1280 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1282 From Mark Salter <msalter@cygnus.com>:
1283 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1284 (sim_open): Add setup for BSP board.
1286 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1288 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1289 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1290 them as unimplemented.
1292 1999-05-08 Felix Lee <flee@cygnus.com>
1294 * configure: Regenerated to track ../common/aclocal.m4 changes.
1296 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1298 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1300 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1302 * configure.in: Any mips64vr5*-*-* target should have
1303 -DTARGET_ENABLE_FR=1.
1304 (default_endian): Any mips64vr*el-*-* target should default to
1306 * configure: Re-generate.
1308 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1310 * mips.igen (ldl): Extend from _16_, not 32.
1312 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1314 * interp.c (sim_store_register): Force registers written to by GDB
1315 into an un-interpreted state.
1317 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1319 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1320 CPU, start periodic background I/O polls.
1321 (tx3904sio_poll): New function: periodic I/O poller.
1323 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1325 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1327 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1329 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1332 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1334 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1335 (load_word): Call SIM_CORE_SIGNAL hook on error.
1336 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1337 starting. For exception dispatching, pass PC instead of NULL_CIA.
1338 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1339 * sim-main.h (COP0_BADVADDR): Define.
1340 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1341 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1342 (_sim_cpu): Add exc_* fields to store register value snapshots.
1343 * mips.igen (*): Replace memory-related SignalException* calls
1344 with references to SIM_CORE_SIGNAL hook.
1346 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1348 * sim-main.c (*): Minor warning cleanups.
1350 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1352 * m16.igen (DADDIU5): Correct type-o.
1354 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1356 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1359 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1361 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1363 (interp.o): Add dependency on itable.h
1364 (oengine.c, gencode): Delete remaining references.
1365 (BUILT_SRC_FROM_GEN): Clean up.
1367 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1370 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1371 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1372 tmp-run-hack) : New.
1373 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1374 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1375 Drop the "64" qualifier to get the HACK generator working.
1376 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1377 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1378 qualifier to get the hack generator working.
1379 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1380 (DSLL): Use do_dsll.
1381 (DSLLV): Use do_dsllv.
1382 (DSRA): Use do_dsra.
1383 (DSRL): Use do_dsrl.
1384 (DSRLV): Use do_dsrlv.
1385 (BC1): Move *vr4100 to get the HACK generator working.
1386 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1387 get the HACK generator working.
1388 (MACC) Rename to get the HACK generator working.
1389 (DMACC,MACCS,DMACCS): Add the 64.
1391 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1393 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1394 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1396 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1398 * mips/interp.c (DEBUG): Cleanups.
1400 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1402 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1403 (tx3904sio_tickle): fflush after a stdout character output.
1405 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1407 * interp.c (sim_close): Uninstall modules.
1409 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1411 * sim-main.h, interp.c (sim_monitor): Change to global
1414 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1416 * configure.in (vr4100): Only include vr4100 instructions in
1418 * configure: Re-generate.
1419 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1421 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1423 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1424 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1427 * configure.in (sim_default_gen, sim_use_gen): Replace with
1429 (--enable-sim-igen): Delete config option. Always using IGEN.
1430 * configure: Re-generate.
1432 * Makefile.in (gencode): Kill, kill, kill.
1435 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1437 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1438 bit mips16 igen simulator.
1439 * configure: Re-generate.
1441 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1442 as part of vr4100 ISA.
1443 * vr.igen: Mark all instructions as 64 bit only.
1445 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1450 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1452 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1453 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1454 * configure: Re-generate.
1456 * m16.igen (BREAK): Define breakpoint instruction.
1457 (JALX32): Mark instruction as mips16 and not r3900.
1458 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1460 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1462 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1464 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1465 insn as a debug breakpoint.
1467 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1469 (PENDING_SCHED): Clean up trace statement.
1470 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1471 (PENDING_FILL): Delay write by only one cycle.
1472 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1474 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1476 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1478 (pending_tick): Move incrementing of index to FOR statement.
1479 (pending_tick): Only update PENDING_OUT after a write has occured.
1481 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1483 * configure: Re-generate.
1485 * interp.c (sim_engine_run OLD): Delete explicit call to
1486 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1488 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1490 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1491 interrupt level number to match changed SignalExceptionInterrupt
1494 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1496 * interp.c: #include "itable.h" if WITH_IGEN.
1497 (get_insn_name): New function.
1498 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1499 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1501 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1503 * configure: Rebuilt to inhale new common/aclocal.m4.
1505 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1507 * dv-tx3904sio.c: Include sim-assert.h.
1509 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1511 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1512 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1513 Reorganize target-specific sim-hardware checks.
1514 * configure: rebuilt.
1515 * interp.c (sim_open): For tx39 target boards, set
1516 OPERATING_ENVIRONMENT, add tx3904sio devices.
1517 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1518 ROM executables. Install dv-sockser into sim-modules list.
1520 * dv-tx3904irc.c: Compiler warning clean-up.
1521 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1522 frequent hw-trace messages.
1524 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1526 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1528 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1530 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1532 * vr.igen: New file.
1533 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1534 * mips.igen: Define vr4100 model. Include vr.igen.
1535 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1537 * mips.igen (check_mf_hilo): Correct check.
1539 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1541 * sim-main.h (interrupt_event): Add prototype.
1543 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1544 register_ptr, register_value.
1545 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1547 * sim-main.h (tracefh): Make extern.
1549 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1551 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1552 Reduce unnecessarily high timer event frequency.
1553 * dv-tx3904cpu.c: Ditto for interrupt event.
1555 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1557 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1559 (interrupt_event): Made non-static.
1561 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1562 interchange of configuration values for external vs. internal
1565 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1567 * mips.igen (BREAK): Moved code to here for
1568 simulator-reserved break instructions.
1569 * gencode.c (build_instruction): Ditto.
1570 * interp.c (signal_exception): Code moved from here. Non-
1571 reserved instructions now use exception vector, rather
1573 * sim-main.h: Moved magic constants to here.
1575 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1577 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1578 register upon non-zero interrupt event level, clear upon zero
1580 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1581 by passing zero event value.
1582 (*_io_{read,write}_buffer): Endianness fixes.
1583 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1584 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1586 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1587 serial I/O and timer module at base address 0xFFFF0000.
1589 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1591 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1594 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1596 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1598 * configure: Update.
1600 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1602 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1603 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1604 * configure.in: Include tx3904tmr in hw_device list.
1605 * configure: Rebuilt.
1606 * interp.c (sim_open): Instantiate three timer instances.
1607 Fix address typo of tx3904irc instance.
1609 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1611 * interp.c (signal_exception): SystemCall exception now uses
1612 the exception vector.
1614 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1616 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1619 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1621 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1623 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1625 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1627 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1628 sim-main.h. Declare a struct hw_descriptor instead of struct
1629 hw_device_descriptor.
1631 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1633 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1634 right bits and then re-align left hand bytes to correct byte
1635 lanes. Fix incorrect computation in do_store_left when loading
1636 bytes from second word.
1638 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1640 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1641 * interp.c (sim_open): Only create a device tree when HW is
1644 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1645 * interp.c (signal_exception): Ditto.
1647 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1649 * gencode.c: Mark BEGEZALL as LIKELY.
1651 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1653 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1654 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1656 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1658 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1659 modules. Recognize TX39 target with "mips*tx39" pattern.
1660 * configure: Rebuilt.
1661 * sim-main.h (*): Added many macros defining bits in
1662 TX39 control registers.
1663 (SignalInterrupt): Send actual PC instead of NULL.
1664 (SignalNMIReset): New exception type.
1665 * interp.c (board): New variable for future use to identify
1666 a particular board being simulated.
1667 (mips_option_handler,mips_options): Added "--board" option.
1668 (interrupt_event): Send actual PC.
1669 (sim_open): Make memory layout conditional on board setting.
1670 (signal_exception): Initial implementation of hardware interrupt
1671 handling. Accept another break instruction variant for simulator
1673 (decode_coproc): Implement RFE instruction for TX39.
1674 (mips.igen): Decode RFE instruction as such.
1675 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1676 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1677 bbegin to implement memory map.
1678 * dv-tx3904cpu.c: New file.
1679 * dv-tx3904irc.c: New file.
1681 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1683 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1685 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1687 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1688 with calls to check_div_hilo.
1690 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1692 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1693 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1694 Add special r3900 version of do_mult_hilo.
1695 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1696 with calls to check_mult_hilo.
1697 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1698 with calls to check_div_hilo.
1700 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1702 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1703 Document a replacement.
1705 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1707 * interp.c (sim_monitor): Make mon_printf work.
1709 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1711 * sim-main.h (INSN_NAME): New arg `cpu'.
1713 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1715 * configure: Regenerated to track ../common/aclocal.m4 changes.
1717 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1719 * configure: Regenerated to track ../common/aclocal.m4 changes.
1722 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1724 * acconfig.h: New file.
1725 * configure.in: Reverted change of Apr 24; use sinclude again.
1727 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1729 * configure: Regenerated to track ../common/aclocal.m4 changes.
1732 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1734 * configure.in: Don't call sinclude.
1736 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1738 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1740 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1742 * mips.igen (ERET): Implement.
1744 * interp.c (decode_coproc): Return sign-extended EPC.
1746 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1748 * interp.c (signal_exception): Do not ignore Trap.
1749 (signal_exception): On TRAP, restart at exception address.
1750 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1751 (signal_exception): Update.
1752 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1753 so that TRAP instructions are caught.
1755 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1757 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1758 contains HI/LO access history.
1759 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1760 (HIACCESS, LOACCESS): Delete, replace with
1761 (HIHISTORY, LOHISTORY): New macros.
1762 (CHECKHILO): Delete all, moved to mips.igen
1764 * gencode.c (build_instruction): Do not generate checks for
1765 correct HI/LO register usage.
1767 * interp.c (old_engine_run): Delete checks for correct HI/LO
1770 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1771 check_mf_cycles): New functions.
1772 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1773 do_divu, domultx, do_mult, do_multu): Use.
1775 * tx.igen ("madd", "maddu"): Use.
1777 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1779 * mips.igen (DSRAV): Use function do_dsrav.
1780 (SRAV): Use new function do_srav.
1782 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1783 (B): Sign extend 11 bit immediate.
1784 (EXT-B*): Shift 16 bit immediate left by 1.
1785 (ADDIU*): Don't sign extend immediate value.
1787 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1789 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1791 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1794 * mips.igen (delayslot32, nullify_next_insn): New functions.
1795 (m16.igen): Always include.
1796 (do_*): Add more tracing.
1798 * m16.igen (delayslot16): Add NIA argument, could be called by a
1799 32 bit MIPS16 instruction.
1801 * interp.c (ifetch16): Move function from here.
1802 * sim-main.c (ifetch16): To here.
1804 * sim-main.c (ifetch16, ifetch32): Update to match current
1805 implementations of LH, LW.
1806 (signal_exception): Don't print out incorrect hex value of illegal
1809 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1811 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1814 * m16.igen: Implement MIPS16 instructions.
1816 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1817 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1818 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1819 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1820 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1821 bodies of corresponding code from 32 bit insn to these. Also used
1822 by MIPS16 versions of functions.
1824 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1825 (IMEM16): Drop NR argument from macro.
1827 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1829 * Makefile.in (SIM_OBJS): Add sim-main.o.
1831 * sim-main.h (address_translation, load_memory, store_memory,
1832 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1834 (pr_addr, pr_uword64): Declare.
1835 (sim-main.c): Include when H_REVEALS_MODULE_P.
1837 * interp.c (address_translation, load_memory, store_memory,
1838 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1840 * sim-main.c: To here. Fix compilation problems.
1842 * configure.in: Enable inlining.
1843 * configure: Re-config.
1845 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1847 * configure: Regenerated to track ../common/aclocal.m4 changes.
1849 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1851 * mips.igen: Include tx.igen.
1852 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1853 * tx.igen: New file, contains MADD and MADDU.
1855 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1856 the hardwired constant `7'.
1857 (store_memory): Ditto.
1858 (LOADDRMASK): Move definition to sim-main.h.
1860 mips.igen (MTC0): Enable for r3900.
1863 mips.igen (do_load_byte): Delete.
1864 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1865 do_store_right): New functions.
1866 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1868 configure.in: Let the tx39 use igen again.
1871 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1873 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1874 not an address sized quantity. Return zero for cache sizes.
1876 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1878 * mips.igen (r3900): r3900 does not support 64 bit integer
1881 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1883 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1885 * configure : Rebuild.
1887 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1889 * configure: Regenerated to track ../common/aclocal.m4 changes.
1891 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1893 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1895 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1897 * configure: Regenerated to track ../common/aclocal.m4 changes.
1898 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1900 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1902 * configure: Regenerated to track ../common/aclocal.m4 changes.
1904 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1906 * interp.c (Max, Min): Comment out functions. Not yet used.
1908 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1910 * configure: Regenerated to track ../common/aclocal.m4 changes.
1912 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1914 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1915 configurable settings for stand-alone simulator.
1917 * configure.in: Added X11 search, just in case.
1919 * configure: Regenerated.
1921 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1923 * interp.c (sim_write, sim_read, load_memory, store_memory):
1924 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1926 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1928 * sim-main.h (GETFCC): Return an unsigned value.
1930 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1932 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1933 (DADD): Result destination is RD not RT.
1935 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1937 * sim-main.h (HIACCESS, LOACCESS): Always define.
1939 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1941 * interp.c (sim_info): Delete.
1943 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1945 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1946 (mips_option_handler): New argument `cpu'.
1947 (sim_open): Update call to sim_add_option_table.
1949 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1951 * mips.igen (CxC1): Add tracing.
1953 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1955 * sim-main.h (Max, Min): Declare.
1957 * interp.c (Max, Min): New functions.
1959 * mips.igen (BC1): Add tracing.
1961 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1963 * interp.c Added memory map for stack in vr4100
1965 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1967 * interp.c (load_memory): Add missing "break"'s.
1969 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1971 * interp.c (sim_store_register, sim_fetch_register): Pass in
1972 length parameter. Return -1.
1974 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1976 * interp.c: Added hardware init hook, fixed warnings.
1978 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1980 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1982 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1984 * interp.c (ifetch16): New function.
1986 * sim-main.h (IMEM32): Rename IMEM.
1987 (IMEM16_IMMED): Define.
1989 (DELAY_SLOT): Update.
1991 * m16run.c (sim_engine_run): New file.
1993 * m16.igen: All instructions except LB.
1994 (LB): Call do_load_byte.
1995 * mips.igen (do_load_byte): New function.
1996 (LB): Call do_load_byte.
1998 * mips.igen: Move spec for insn bit size and high bit from here.
1999 * Makefile.in (tmp-igen, tmp-m16): To here.
2001 * m16.dc: New file, decode mips16 instructions.
2003 * Makefile.in (SIM_NO_ALL): Define.
2004 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2006 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2008 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2009 point unit to 32 bit registers.
2010 * configure: Re-generate.
2012 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2014 * configure.in (sim_use_gen): Make IGEN the default simulator
2015 generator for generic 32 and 64 bit mips targets.
2016 * configure: Re-generate.
2018 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2020 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2023 * interp.c (sim_fetch_register, sim_store_register): Read/write
2024 FGR from correct location.
2025 (sim_open): Set size of FGR's according to
2026 WITH_TARGET_FLOATING_POINT_BITSIZE.
2028 * sim-main.h (FGR): Store floating point registers in a separate
2031 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2033 * configure: Regenerated to track ../common/aclocal.m4 changes.
2035 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2037 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2039 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2041 * interp.c (pending_tick): New function. Deliver pending writes.
2043 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2044 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2045 it can handle mixed sized quantites and single bits.
2047 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2049 * interp.c (oengine.h): Do not include when building with IGEN.
2050 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2051 (sim_info): Ditto for PROCESSOR_64BIT.
2052 (sim_monitor): Replace ut_reg with unsigned_word.
2053 (*): Ditto for t_reg.
2054 (LOADDRMASK): Define.
2055 (sim_open): Remove defunct check that host FP is IEEE compliant,
2056 using software to emulate floating point.
2057 (value_fpr, ...): Always compile, was conditional on HASFPU.
2059 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2061 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2064 * interp.c (SD, CPU): Define.
2065 (mips_option_handler): Set flags in each CPU.
2066 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2067 (sim_close): Do not clear STATE, deleted anyway.
2068 (sim_write, sim_read): Assume CPU zero's vm should be used for
2070 (sim_create_inferior): Set the PC for all processors.
2071 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2073 (mips16_entry): Pass correct nr of args to store_word, load_word.
2074 (ColdReset): Cold reset all cpu's.
2075 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2076 (sim_monitor, load_memory, store_memory, signal_exception): Use
2077 `CPU' instead of STATE_CPU.
2080 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2083 * sim-main.h (signal_exception): Add sim_cpu arg.
2084 (SignalException*): Pass both SD and CPU to signal_exception.
2085 * interp.c (signal_exception): Update.
2087 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2089 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2090 address_translation): Ditto
2091 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2093 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2095 * configure: Regenerated to track ../common/aclocal.m4 changes.
2097 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2099 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2101 * mips.igen (model): Map processor names onto BFD name.
2103 * sim-main.h (CPU_CIA): Delete.
2104 (SET_CIA, GET_CIA): Define
2106 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2108 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2111 * configure.in (default_endian): Configure a big-endian simulator
2113 * configure: Re-generate.
2115 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2117 * configure: Regenerated to track ../common/aclocal.m4 changes.
2119 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2121 * interp.c (sim_monitor): Handle Densan monitor outbyte
2122 and inbyte functions.
2124 1997-12-29 Felix Lee <flee@cygnus.com>
2126 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2128 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2130 * Makefile.in (tmp-igen): Arrange for $zero to always be
2131 reset to zero after every instruction.
2133 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2135 * configure: Regenerated to track ../common/aclocal.m4 changes.
2138 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2140 * mips.igen (MSUB): Fix to work like MADD.
2141 * gencode.c (MSUB): Similarly.
2143 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2145 * configure: Regenerated to track ../common/aclocal.m4 changes.
2147 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2149 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2151 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2153 * sim-main.h (sim-fpu.h): Include.
2155 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2156 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2157 using host independant sim_fpu module.
2159 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2161 * interp.c (signal_exception): Report internal errors with SIGABRT
2164 * sim-main.h (C0_CONFIG): New register.
2165 (signal.h): No longer include.
2167 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2169 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2171 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2173 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2175 * mips.igen: Tag vr5000 instructions.
2176 (ANDI): Was missing mipsIV model, fix assembler syntax.
2177 (do_c_cond_fmt): New function.
2178 (C.cond.fmt): Handle mips I-III which do not support CC field
2180 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2181 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2183 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2184 vr5000 which saves LO in a GPR separatly.
2186 * configure.in (enable-sim-igen): For vr5000, select vr5000
2187 specific instructions.
2188 * configure: Re-generate.
2190 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2192 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2194 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2195 fmt_uninterpreted_64 bit cases to switch. Convert to
2198 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2200 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2201 as specified in IV3.2 spec.
2202 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2204 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2206 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2207 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2208 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2209 PENDING_FILL versions of instructions. Simplify.
2211 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2213 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2215 (MTHI, MFHI): Disable code checking HI-LO.
2217 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2219 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2221 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2223 * gencode.c (build_mips16_operands): Replace IPC with cia.
2225 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2226 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2228 (UndefinedResult): Replace function with macro/function
2230 (sim_engine_run): Don't save PC in IPC.
2232 * sim-main.h (IPC): Delete.
2235 * interp.c (signal_exception, store_word, load_word,
2236 address_translation, load_memory, store_memory, cache_op,
2237 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2238 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2239 current instruction address - cia - argument.
2240 (sim_read, sim_write): Call address_translation directly.
2241 (sim_engine_run): Rename variable vaddr to cia.
2242 (signal_exception): Pass cia to sim_monitor
2244 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2245 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2246 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2248 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2249 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2252 * interp.c (signal_exception): Pass restart address to
2255 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2256 idecode.o): Add dependency.
2258 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2260 (DELAY_SLOT): Update NIA not PC with branch address.
2261 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2263 * mips.igen: Use CIA not PC in branch calculations.
2264 (illegal): Call SignalException.
2265 (BEQ, ADDIU): Fix assembler.
2267 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2269 * m16.igen (JALX): Was missing.
2271 * configure.in (enable-sim-igen): New configuration option.
2272 * configure: Re-generate.
2274 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2276 * interp.c (load_memory, store_memory): Delete parameter RAW.
2277 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2278 bypassing {load,store}_memory.
2280 * sim-main.h (ByteSwapMem): Delete definition.
2282 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2284 * interp.c (sim_do_command, sim_commands): Delete mips specific
2285 commands. Handled by module sim-options.
2287 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2288 (WITH_MODULO_MEMORY): Define.
2290 * interp.c (sim_info): Delete code printing memory size.
2292 * interp.c (mips_size): Nee sim_size, delete function.
2294 (monitor, monitor_base, monitor_size): Delete global variables.
2295 (sim_open, sim_close): Delete code creating monitor and other
2296 memory regions. Use sim-memopts module, via sim_do_commandf, to
2297 manage memory regions.
2298 (load_memory, store_memory): Use sim-core for memory model.
2300 * interp.c (address_translation): Delete all memory map code
2301 except line forcing 32 bit addresses.
2303 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2305 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2308 * interp.c (logfh, logfile): Delete globals.
2309 (sim_open, sim_close): Delete code opening & closing log file.
2310 (mips_option_handler): Delete -l and -n options.
2311 (OPTION mips_options): Ditto.
2313 * interp.c (OPTION mips_options): Rename option trace to dinero.
2314 (mips_option_handler): Update.
2316 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2318 * interp.c (fetch_str): New function.
2319 (sim_monitor): Rewrite using sim_read & sim_write.
2320 (sim_open): Check magic number.
2321 (sim_open): Write monitor vectors into memory using sim_write.
2322 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2323 (sim_read, sim_write): Simplify - transfer data one byte at a
2325 (load_memory, store_memory): Clarify meaning of parameter RAW.
2327 * sim-main.h (isHOST): Defete definition.
2328 (isTARGET): Mark as depreciated.
2329 (address_translation): Delete parameter HOST.
2331 * interp.c (address_translation): Delete parameter HOST.
2333 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2337 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2338 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2340 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2342 * mips.igen: Add model filter field to records.
2344 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2346 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2348 interp.c (sim_engine_run): Do not compile function sim_engine_run
2349 when WITH_IGEN == 1.
2351 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2352 target architecture.
2354 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2355 igen. Replace with configuration variables sim_igen_flags /
2358 * m16.igen: New file. Copy mips16 insns here.
2359 * mips.igen: From here.
2361 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2363 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2365 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2367 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2369 * gencode.c (build_instruction): Follow sim_write's lead in using
2370 BigEndianMem instead of !ByteSwapMem.
2372 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2374 * configure.in (sim_gen): Dependent on target, select type of
2375 generator. Always select old style generator.
2377 configure: Re-generate.
2379 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2381 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2382 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2383 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2384 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2385 SIM_@sim_gen@_*, set by autoconf.
2387 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2389 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2391 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2392 CURRENT_FLOATING_POINT instead.
2394 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2395 (address_translation): Raise exception InstructionFetch when
2396 translation fails and isINSTRUCTION.
2398 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2399 sim_engine_run): Change type of of vaddr and paddr to
2401 (address_translation, prefetch, load_memory, store_memory,
2402 cache_op): Change type of vAddr and pAddr to address_word.
2404 * gencode.c (build_instruction): Change type of vaddr and paddr to
2407 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2409 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2410 macro to obtain result of ALU op.
2412 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2414 * interp.c (sim_info): Call profile_print.
2416 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2418 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2420 * sim-main.h (WITH_PROFILE): Do not define, defined in
2421 common/sim-config.h. Use sim-profile module.
2422 (simPROFILE): Delete defintion.
2424 * interp.c (PROFILE): Delete definition.
2425 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2426 (sim_close): Delete code writing profile histogram.
2427 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2429 (sim_engine_run): Delete code profiling the PC.
2431 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2433 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2435 * interp.c (sim_monitor): Make register pointers of type
2438 * sim-main.h: Make registers of type unsigned_word not
2441 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2443 * interp.c (sync_operation): Rename from SyncOperation, make
2444 global, add SD argument.
2445 (prefetch): Rename from Prefetch, make global, add SD argument.
2446 (decode_coproc): Make global.
2448 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2450 * gencode.c (build_instruction): Generate DecodeCoproc not
2451 decode_coproc calls.
2453 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2454 (SizeFGR): Move to sim-main.h
2455 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2456 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2457 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2459 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2460 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2461 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2462 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2463 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2464 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2466 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2468 (sim-alu.h): Include.
2469 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2470 (sim_cia): Typedef to instruction_address.
2472 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2474 * Makefile.in (interp.o): Rename generated file engine.c to
2479 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2481 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2483 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2485 * gencode.c (build_instruction): For "FPSQRT", output correct
2486 number of arguments to Recip.
2488 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2490 * Makefile.in (interp.o): Depends on sim-main.h
2492 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2494 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2495 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2496 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2497 STATE, DSSTATE): Define
2498 (GPR, FGRIDX, ..): Define.
2500 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2501 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2502 (GPR, FGRIDX, ...): Delete macros.
2504 * interp.c: Update names to match defines from sim-main.h
2506 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2508 * interp.c (sim_monitor): Add SD argument.
2509 (sim_warning): Delete. Replace calls with calls to
2511 (sim_error): Delete. Replace calls with sim_io_error.
2512 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2513 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2514 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2516 (mips_size): Rename from sim_size. Add SD argument.
2518 * interp.c (simulator): Delete global variable.
2519 (callback): Delete global variable.
2520 (mips_option_handler, sim_open, sim_write, sim_read,
2521 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2522 sim_size,sim_monitor): Use sim_io_* not callback->*.
2523 (sim_open): ZALLOC simulator struct.
2524 (PROFILE): Do not define.
2526 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2528 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2529 support.h with corresponding code.
2531 * sim-main.h (word64, uword64), support.h: Move definition to
2533 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2536 * Makefile.in: Update dependencies
2537 * interp.c: Do not include.
2539 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2541 * interp.c (address_translation, load_memory, store_memory,
2542 cache_op): Rename to from AddressTranslation et.al., make global,
2545 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2548 * interp.c (SignalException): Rename to signal_exception, make
2551 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2553 * sim-main.h (SignalException, SignalExceptionInterrupt,
2554 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2555 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2556 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2559 * interp.c, support.h: Use.
2561 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2563 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2564 to value_fpr / store_fpr. Add SD argument.
2565 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2566 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2568 * sim-main.h (ValueFPR, StoreFPR): Define.
2570 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2572 * interp.c (sim_engine_run): Check consistency between configure
2573 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2576 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2577 (mips_fpu): Configure WITH_FLOATING_POINT.
2578 (mips_endian): Configure WITH_TARGET_ENDIAN.
2579 * configure: Update.
2581 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2583 * configure: Regenerated to track ../common/aclocal.m4 changes.
2585 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2587 * configure: Regenerated.
2589 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2591 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2593 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2595 * gencode.c (print_igen_insn_models): Assume certain architectures
2596 include all mips* instructions.
2597 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2600 * Makefile.in (tmp.igen): Add target. Generate igen input from
2603 * gencode.c (FEATURE_IGEN): Define.
2604 (main): Add --igen option. Generate output in igen format.
2605 (process_instructions): Format output according to igen option.
2606 (print_igen_insn_format): New function.
2607 (print_igen_insn_models): New function.
2608 (process_instructions): Only issue warnings and ignore
2609 instructions when no FEATURE_IGEN.
2611 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2613 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2616 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2618 * configure: Regenerated to track ../common/aclocal.m4 changes.
2620 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2622 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2623 SIM_RESERVED_BITS): Delete, moved to common.
2624 (SIM_EXTRA_CFLAGS): Update.
2626 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2628 * configure.in: Configure non-strict memory alignment.
2629 * configure: Regenerated to track ../common/aclocal.m4 changes.
2631 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2633 * configure: Regenerated to track ../common/aclocal.m4 changes.
2635 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2637 * gencode.c (SDBBP,DERET): Added (3900) insns.
2638 (RFE): Turn on for 3900.
2639 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2640 (dsstate): Made global.
2641 (SUBTARGET_R3900): Added.
2642 (CANCELDELAYSLOT): New.
2643 (SignalException): Ignore SystemCall rather than ignore and
2644 terminate. Add DebugBreakPoint handling.
2645 (decode_coproc): New insns RFE, DERET; and new registers Debug
2646 and DEPC protected by SUBTARGET_R3900.
2647 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2649 * Makefile.in,configure.in: Add mips subtarget option.
2650 * configure: Update.
2652 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2654 * gencode.c: Add r3900 (tx39).
2657 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2659 * gencode.c (build_instruction): Don't need to subtract 4 for
2662 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2664 * interp.c: Correct some HASFPU problems.
2666 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2668 * configure: Regenerated to track ../common/aclocal.m4 changes.
2670 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2672 * interp.c (mips_options): Fix samples option short form, should
2675 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2677 * interp.c (sim_info): Enable info code. Was just returning.
2679 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2681 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2684 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2686 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2688 (build_instruction): Ditto for LL.
2690 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2692 * configure: Regenerated to track ../common/aclocal.m4 changes.
2694 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2696 * configure: Regenerated to track ../common/aclocal.m4 changes.
2699 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2701 * interp.c (sim_open): Add call to sim_analyze_program, update
2704 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2706 * interp.c (sim_kill): Delete.
2707 (sim_create_inferior): Add ABFD argument. Set PC from same.
2708 (sim_load): Move code initializing trap handlers from here.
2709 (sim_open): To here.
2710 (sim_load): Delete, use sim-hload.c.
2712 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2714 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2716 * configure: Regenerated to track ../common/aclocal.m4 changes.
2719 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2721 * interp.c (sim_open): Add ABFD argument.
2722 (sim_load): Move call to sim_config from here.
2723 (sim_open): To here. Check return status.
2725 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2727 * gencode.c (build_instruction): Two arg MADD should
2728 not assign result to $0.
2730 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2732 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2733 * sim/mips/configure.in: Regenerate.
2735 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2737 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2738 signed8, unsigned8 et.al. types.
2740 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2741 hosts when selecting subreg.
2743 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2745 * interp.c (sim_engine_run): Reset the ZERO register to zero
2746 regardless of FEATURE_WARN_ZERO.
2747 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2749 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2751 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2752 (SignalException): For BreakPoints ignore any mode bits and just
2754 (SignalException): Always set the CAUSE register.
2756 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2758 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2759 exception has been taken.
2761 * interp.c: Implement the ERET and mt/f sr instructions.
2763 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2765 * interp.c (SignalException): Don't bother restarting an
2768 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2770 * interp.c (SignalException): Really take an interrupt.
2771 (interrupt_event): Only deliver interrupts when enabled.
2773 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2775 * interp.c (sim_info): Only print info when verbose.
2776 (sim_info) Use sim_io_printf for output.
2778 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2780 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2783 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2785 * interp.c (sim_do_command): Check for common commands if a
2786 simulator specific command fails.
2788 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2790 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2791 and simBE when DEBUG is defined.
2793 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2795 * interp.c (interrupt_event): New function. Pass exception event
2796 onto exception handler.
2798 * configure.in: Check for stdlib.h.
2799 * configure: Regenerate.
2801 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2802 variable declaration.
2803 (build_instruction): Initialize memval1.
2804 (build_instruction): Add UNUSED attribute to byte, bigend,
2806 (build_operands): Ditto.
2808 * interp.c: Fix GCC warnings.
2809 (sim_get_quit_code): Delete.
2811 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2812 * Makefile.in: Ditto.
2813 * configure: Re-generate.
2815 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2817 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2819 * interp.c (mips_option_handler): New function parse argumes using
2821 (myname): Replace with STATE_MY_NAME.
2822 (sim_open): Delete check for host endianness - performed by
2824 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2825 (sim_open): Move much of the initialization from here.
2826 (sim_load): To here. After the image has been loaded and
2828 (sim_open): Move ColdReset from here.
2829 (sim_create_inferior): To here.
2830 (sim_open): Make FP check less dependant on host endianness.
2832 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2834 * interp.c (sim_set_callbacks): Delete.
2836 * interp.c (membank, membank_base, membank_size): Replace with
2837 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2838 (sim_open): Remove call to callback->init. gdb/run do this.
2842 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2844 * interp.c (big_endian_p): Delete, replaced by
2845 current_target_byte_order.
2847 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2849 * interp.c (host_read_long, host_read_word, host_swap_word,
2850 host_swap_long): Delete. Using common sim-endian.
2851 (sim_fetch_register, sim_store_register): Use H2T.
2852 (pipeline_ticks): Delete. Handled by sim-events.
2854 (sim_engine_run): Update.
2856 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2858 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2860 (SignalException): To here. Signal using sim_engine_halt.
2861 (sim_stop_reason): Delete, moved to common.
2863 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2865 * interp.c (sim_open): Add callback argument.
2866 (sim_set_callbacks): Delete SIM_DESC argument.
2869 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2871 * Makefile.in (SIM_OBJS): Add common modules.
2873 * interp.c (sim_set_callbacks): Also set SD callback.
2874 (set_endianness, xfer_*, swap_*): Delete.
2875 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2876 Change to functions using sim-endian macros.
2877 (control_c, sim_stop): Delete, use common version.
2878 (simulate): Convert into.
2879 (sim_engine_run): This function.
2880 (sim_resume): Delete.
2882 * interp.c (simulation): New variable - the simulator object.
2883 (sim_kind): Delete global - merged into simulation.
2884 (sim_load): Cleanup. Move PC assignment from here.
2885 (sim_create_inferior): To here.
2887 * sim-main.h: New file.
2888 * interp.c (sim-main.h): Include.
2890 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2892 * configure: Regenerated to track ../common/aclocal.m4 changes.
2894 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2896 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2898 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2900 * gencode.c (build_instruction): DIV instructions: check
2901 for division by zero and integer overflow before using
2902 host's division operation.
2904 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2906 * Makefile.in (SIM_OBJS): Add sim-load.o.
2907 * interp.c: #include bfd.h.
2908 (target_byte_order): Delete.
2909 (sim_kind, myname, big_endian_p): New static locals.
2910 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2911 after argument parsing. Recognize -E arg, set endianness accordingly.
2912 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2913 load file into simulator. Set PC from bfd.
2914 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2915 (set_endianness): Use big_endian_p instead of target_byte_order.
2917 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2919 * interp.c (sim_size): Delete prototype - conflicts with
2920 definition in remote-sim.h. Correct definition.
2922 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2924 * configure: Regenerated to track ../common/aclocal.m4 changes.
2927 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2929 * interp.c (sim_open): New arg `kind'.
2931 * configure: Regenerated to track ../common/aclocal.m4 changes.
2933 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2935 * configure: Regenerated to track ../common/aclocal.m4 changes.
2937 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2939 * interp.c (sim_open): Set optind to 0 before calling getopt.
2941 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2943 * configure: Regenerated to track ../common/aclocal.m4 changes.
2945 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2947 * interp.c : Replace uses of pr_addr with pr_uword64
2948 where the bit length is always 64 independent of SIM_ADDR.
2949 (pr_uword64) : added.
2951 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2953 * configure: Re-generate.
2955 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2957 * configure: Regenerate to track ../common/aclocal.m4 changes.
2959 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2961 * interp.c (sim_open): New SIM_DESC result. Argument is now
2963 (other sim_*): New SIM_DESC argument.
2965 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2967 * interp.c: Fix printing of addresses for non-64-bit targets.
2968 (pr_addr): Add function to print address based on size.
2970 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2972 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2974 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2976 * gencode.c (build_mips16_operands): Correct computation of base
2977 address for extended PC relative instruction.
2979 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2981 * interp.c (mips16_entry): Add support for floating point cases.
2982 (SignalException): Pass floating point cases to mips16_entry.
2983 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2985 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2987 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2988 and then set the state to fmt_uninterpreted.
2989 (COP_SW): Temporarily set the state to fmt_word while calling
2992 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2994 * gencode.c (build_instruction): The high order may be set in the
2995 comparison flags at any ISA level, not just ISA 4.
2997 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2999 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3000 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3001 * configure.in: sinclude ../common/aclocal.m4.
3002 * configure: Regenerated.
3004 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3006 * configure: Rebuild after change to aclocal.m4.
3008 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3010 * configure configure.in Makefile.in: Update to new configure
3011 scheme which is more compatible with WinGDB builds.
3012 * configure.in: Improve comment on how to run autoconf.
3013 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3014 * Makefile.in: Use autoconf substitution to install common
3017 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3019 * gencode.c (build_instruction): Use BigEndianCPU instead of
3022 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3024 * interp.c (sim_monitor): Make output to stdout visible in
3025 wingdb's I/O log window.
3027 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3029 * support.h: Undo previous change to SIGTRAP
3032 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3034 * interp.c (store_word, load_word): New static functions.
3035 (mips16_entry): New static function.
3036 (SignalException): Look for mips16 entry and exit instructions.
3037 (simulate): Use the correct index when setting fpr_state after
3038 doing a pending move.
3040 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3042 * interp.c: Fix byte-swapping code throughout to work on
3043 both little- and big-endian hosts.
3045 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3047 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3048 with gdb/config/i386/xm-windows.h.
3050 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3052 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3053 that messes up arithmetic shifts.
3055 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3057 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3058 SIGTRAP and SIGQUIT for _WIN32.
3060 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3062 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3063 force a 64 bit multiplication.
3064 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3065 destination register is 0, since that is the default mips16 nop
3068 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3070 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3071 (build_endian_shift): Don't check proc64.
3072 (build_instruction): Always set memval to uword64. Cast op2 to
3073 uword64 when shifting it left in memory instructions. Always use
3074 the same code for stores--don't special case proc64.
3076 * gencode.c (build_mips16_operands): Fix base PC value for PC
3078 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3080 * interp.c (simJALDELAYSLOT): Define.
3081 (JALDELAYSLOT): Define.
3082 (INDELAYSLOT, INJALDELAYSLOT): Define.
3083 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3085 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3087 * interp.c (sim_open): add flush_cache as a PMON routine
3088 (sim_monitor): handle flush_cache by ignoring it
3090 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3092 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3094 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3095 (BigEndianMem): Rename to ByteSwapMem and change sense.
3096 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3097 BigEndianMem references to !ByteSwapMem.
3098 (set_endianness): New function, with prototype.
3099 (sim_open): Call set_endianness.
3100 (sim_info): Use simBE instead of BigEndianMem.
3101 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3102 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3103 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3104 ifdefs, keeping the prototype declaration.
3105 (swap_word): Rewrite correctly.
3106 (ColdReset): Delete references to CONFIG. Delete endianness related
3107 code; moved to set_endianness.
3109 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3111 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3112 * interp.c (CHECKHILO): Define away.
3113 (simSIGINT): New macro.
3114 (membank_size): Increase from 1MB to 2MB.
3115 (control_c): New function.
3116 (sim_resume): Rename parameter signal to signal_number. Add local
3117 variable prev. Call signal before and after simulate.
3118 (sim_stop_reason): Add simSIGINT support.
3119 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3121 (sim_warning): Delete call to SignalException. Do call printf_filtered
3123 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3124 a call to sim_warning.
3126 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3128 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3129 16 bit instructions.
3131 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3133 Add support for mips16 (16 bit MIPS implementation):
3134 * gencode.c (inst_type): Add mips16 instruction encoding types.
3135 (GETDATASIZEINSN): Define.
3136 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3137 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3139 (MIPS16_DECODE): New table, for mips16 instructions.
3140 (bitmap_val): New static function.
3141 (struct mips16_op): Define.
3142 (mips16_op_table): New table, for mips16 operands.
3143 (build_mips16_operands): New static function.
3144 (process_instructions): If PC is odd, decode a mips16
3145 instruction. Break out instruction handling into new
3146 build_instruction function.
3147 (build_instruction): New static function, broken out of
3148 process_instructions. Check modifiers rather than flags for SHIFT
3149 bit count and m[ft]{hi,lo} direction.
3150 (usage): Pass program name to fprintf.
3151 (main): Remove unused variable this_option_optind. Change
3152 ``*loptarg++'' to ``loptarg++''.
3153 (my_strtoul): Parenthesize && within ||.
3154 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3155 (simulate): If PC is odd, fetch a 16 bit instruction, and
3156 increment PC by 2 rather than 4.
3157 * configure.in: Add case for mips16*-*-*.
3158 * configure: Rebuild.
3160 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3162 * interp.c: Allow -t to enable tracing in standalone simulator.
3163 Fix garbage output in trace file and error messages.
3165 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3167 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3168 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3169 * configure.in: Simplify using macros in ../common/aclocal.m4.
3170 * configure: Regenerated.
3171 * tconfig.in: New file.
3173 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3175 * interp.c: Fix bugs in 64-bit port.
3176 Use ansi function declarations for msvc compiler.
3177 Initialize and test file pointer in trace code.
3178 Prevent duplicate definition of LAST_EMED_REGNUM.
3180 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3182 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3184 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3186 * interp.c (SignalException): Check for explicit terminating
3188 * gencode.c: Pass instruction value through SignalException()
3189 calls for Trap, Breakpoint and Syscall.
3191 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3193 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3194 only used on those hosts that provide it.
3195 * configure.in: Add sqrt() to list of functions to be checked for.
3196 * config.in: Re-generated.
3197 * configure: Re-generated.
3199 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3201 * gencode.c (process_instructions): Call build_endian_shift when
3202 expanding STORE RIGHT, to fix swr.
3203 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3204 clear the high bits.
3205 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3206 Fix float to int conversions to produce signed values.
3208 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3210 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3211 (process_instructions): Correct handling of nor instruction.
3212 Correct shift count for 32 bit shift instructions. Correct sign
3213 extension for arithmetic shifts to not shift the number of bits in
3214 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3215 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3217 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3218 It's OK to have a mult follow a mult. What's not OK is to have a
3219 mult follow an mfhi.
3220 (Convert): Comment out incorrect rounding code.
3222 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3224 * interp.c (sim_monitor): Improved monitor printf
3225 simulation. Tidied up simulator warnings, and added "--log" option
3226 for directing warning message output.
3227 * gencode.c: Use sim_warning() rather than WARNING macro.
3229 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3231 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3232 getopt1.o, rather than on gencode.c. Link objects together.
3233 Don't link against -liberty.
3234 (gencode.o, getopt.o, getopt1.o): New targets.
3235 * gencode.c: Include <ctype.h> and "ansidecl.h".
3236 (AND): Undefine after including "ansidecl.h".
3237 (ULONG_MAX): Define if not defined.
3238 (OP_*): Don't define macros; now defined in opcode/mips.h.
3239 (main): Call my_strtoul rather than strtoul.
3240 (my_strtoul): New static function.
3242 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3244 * gencode.c (process_instructions): Generate word64 and uword64
3245 instead of `long long' and `unsigned long long' data types.
3246 * interp.c: #include sysdep.h to get signals, and define default
3248 * (Convert): Work around for Visual-C++ compiler bug with type
3250 * support.h: Make things compile under Visual-C++ by using
3251 __int64 instead of `long long'. Change many refs to long long
3252 into word64/uword64 typedefs.
3254 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3256 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3257 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3259 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3260 (AC_PROG_INSTALL): Added.
3261 (AC_PROG_CC): Moved to before configure.host call.
3262 * configure: Rebuilt.
3264 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3266 * configure.in: Define @SIMCONF@ depending on mips target.
3267 * configure: Rebuild.
3268 * Makefile.in (run): Add @SIMCONF@ to control simulator
3270 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3271 * interp.c: Remove some debugging, provide more detailed error
3272 messages, update memory accesses to use LOADDRMASK.
3274 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3276 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3277 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3279 * configure: Rebuild.
3280 * config.in: New file, generated by autoheader.
3281 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3282 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3283 HAVE_ANINT and HAVE_AINT, as appropriate.
3284 * Makefile.in (run): Use @LIBS@ rather than -lm.
3285 (interp.o): Depend upon config.h.
3286 (Makefile): Just rebuild Makefile.
3287 (clean): Remove stamp-h.
3288 (mostlyclean): Make the same as clean, not as distclean.
3289 (config.h, stamp-h): New targets.
3291 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3293 * interp.c (ColdReset): Fix boolean test. Make all simulator
3296 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3298 * interp.c (xfer_direct_word, xfer_direct_long,
3299 swap_direct_word, swap_direct_long, xfer_big_word,
3300 xfer_big_long, xfer_little_word, xfer_little_long,
3301 swap_word,swap_long): Added.
3302 * interp.c (ColdReset): Provide function indirection to
3303 host<->simulated_target transfer routines.
3304 * interp.c (sim_store_register, sim_fetch_register): Updated to
3305 make use of indirected transfer routines.
3307 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3309 * gencode.c (process_instructions): Ensure FP ABS instruction
3311 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3312 system call support.
3314 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3316 * interp.c (sim_do_command): Complain if callback structure not
3319 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3321 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3322 support for Sun hosts.
3323 * Makefile.in (gencode): Ensure the host compiler and libraries
3324 used for cross-hosted build.
3326 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3328 * interp.c, gencode.c: Some more (TODO) tidying.
3330 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3332 * gencode.c, interp.c: Replaced explicit long long references with
3333 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3334 * support.h (SET64LO, SET64HI): Macros added.
3336 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3338 * configure: Regenerate with autoconf 2.7.
3340 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3342 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3343 * support.h: Remove superfluous "1" from #if.
3344 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3346 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3348 * interp.c (StoreFPR): Control UndefinedResult() call on
3349 WARN_RESULT manifest.
3351 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3353 * gencode.c: Tidied instruction decoding, and added FP instruction
3356 * interp.c: Added dineroIII, and BSD profiling support. Also
3357 run-time FP handling.
3359 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3361 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3362 gencode.c, interp.c, support.h: created.