1 2007-02-19 Thiemo Seufer <ths@mips.com>
2 Nigel Stephens <nigel@mips.com>
3 David Ung <davidu@mips.com>
5 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
6 uninterpreted formats. If fmt is one of the uninterpreted types
7 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
8 fmt_word, and fmt_uninterpreted_64 like fmt_long.
9 (store_fpr): When writing an invalid odd register, set the
10 matching even register to fmt_unknown, not the following register.
11 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
12 the the memory window at offset 0 set by --memory-size command
14 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
16 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
18 (sim_monitor): When returning the memory size to the MIPS
19 application, use the value in STATE_MEM_SIZE, not an arbitrary
21 (cop_lw): Don' mess around with FPR_STATE, just pass
22 fmt_uninterpreted_32 to StoreFPR.
24 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
26 * mips.igen (not_word_value): Single version for mips32, mips64
29 2007-02-19 Thiemo Seufer <ths@mips.com>
30 Nigel Stephens <nigel@mips.com>
32 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
35 2007-02-17 Thiemo Seufer <ths@mips.com>
37 * configure.ac (mips*-sde-elf*): Move in front of generic machine
39 * configure: Regenerate.
41 2007-02-17 Thiemo Seufer <ths@mips.com>
43 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
44 Add mdmx to sim_igen_machine.
45 (mipsisa64*-*-*): Likewise. Remove dsp.
46 (mipsisa32*-*-*): Remove dsp.
47 * configure: Regenerate.
49 2007-02-13 Thiemo Seufer <ths@mips.com>
51 * configure.ac: Add mips*-sde-elf* target.
52 * configure: Regenerate.
54 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
57 * config.in, configure: Regenerate.
59 2006-11-07 Thiemo Seufer <ths@mips.com>
61 * dsp.igen (do_w_op): Fix compiler warning.
63 2006-08-29 Thiemo Seufer <ths@mips.com>
64 David Ung <davidu@mips.com>
66 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
68 * configure: Regenerate.
69 * mips.igen (model): Add smartmips.
70 (MADDU): Increment ACX if carry.
72 (ROR,RORV): Add smartmips.
73 (include): Include smartmips.igen.
74 * sim-main.h (ACX): Set to REGISTERS[89].
75 * smartmips.igen: New file.
77 2006-08-29 Thiemo Seufer <ths@mips.com>
78 David Ung <davidu@mips.com>
80 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
81 mips3264r2.igen. Add missing dependency rules.
82 * m16e.igen: Support for mips16e save/restore instructions.
84 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
86 * configure: Regenerated.
88 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
90 * configure: Regenerated.
92 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
94 * configure: Regenerated.
96 2006-05-15 Chao-ying Fu <fu@mips.com>
98 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
100 2006-04-18 Nick Clifton <nickc@redhat.com>
102 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
105 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
107 * configure: Regenerate.
109 2005-12-14 Chao-ying Fu <fu@mips.com>
111 * Makefile.in (SIM_OBJS): Add dsp.o.
112 (dsp.o): New dependency.
113 (IGEN_INCLUDE): Add dsp.igen.
114 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
115 mipsisa64*-*-*): Add dsp to sim_igen_machine.
116 * configure: Regenerate.
117 * mips.igen: Add dsp model and include dsp.igen.
118 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
119 because these instructions are extended in DSP ASE.
120 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
121 adding 6 DSP accumulator registers and 1 DSP control register.
122 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
123 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
124 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
125 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
126 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
127 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
128 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
129 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
130 DSPCR_CCOND_SMASK): New define.
131 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
132 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
134 2005-07-08 Ian Lance Taylor <ian@airs.com>
136 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
138 2005-06-16 David Ung <davidu@mips.com>
139 Nigel Stephens <nigel@mips.com>
141 * mips.igen: New mips16e model and include m16e.igen.
142 (check_u64): Add mips16e tag.
143 * m16e.igen: New file for MIPS16e instructions.
144 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
145 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
147 * configure: Regenerate.
149 2005-05-26 David Ung <davidu@mips.com>
151 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
152 tags to all instructions which are applicable to the new ISAs.
153 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
155 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
157 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
159 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
160 * configure: Regenerate.
162 2005-03-23 Mark Kettenis <kettenis@gnu.org>
164 * configure: Regenerate.
166 2005-01-14 Andrew Cagney <cagney@gnu.org>
168 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
169 explicit call to AC_CONFIG_HEADER.
170 * configure: Regenerate.
172 2005-01-12 Andrew Cagney <cagney@gnu.org>
174 * configure.ac: Update to use ../common/common.m4.
175 * configure: Re-generate.
177 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
179 * configure: Regenerated to track ../common/aclocal.m4 changes.
181 2005-01-07 Andrew Cagney <cagney@gnu.org>
183 * configure.ac: Rename configure.in, require autoconf 2.59.
184 * configure: Re-generate.
186 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
188 * configure: Regenerate for ../common/aclocal.m4 update.
190 2004-09-24 Monika Chaddha <monika@acmet.com>
192 Committed by Andrew Cagney.
193 * m16.igen (CMP, CMPI): Fix assembler.
195 2004-08-18 Chris Demetriou <cgd@broadcom.com>
197 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
198 * configure: Regenerate.
200 2004-06-25 Chris Demetriou <cgd@broadcom.com>
202 * configure.in (sim_m16_machine): Include mipsIII.
203 * configure: Regenerate.
205 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
207 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
209 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
211 2004-04-10 Chris Demetriou <cgd@broadcom.com>
213 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
215 2004-04-09 Chris Demetriou <cgd@broadcom.com>
217 * mips.igen (check_fmt): Remove.
218 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
219 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
220 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
221 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
222 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
223 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
224 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
225 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
226 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
227 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
229 2004-04-09 Chris Demetriou <cgd@broadcom.com>
231 * sb1.igen (check_sbx): New function.
232 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
234 2004-03-29 Chris Demetriou <cgd@broadcom.com>
235 Richard Sandiford <rsandifo@redhat.com>
237 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
238 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
239 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
240 separate implementations for mipsIV and mipsV. Use new macros to
241 determine whether the restrictions apply.
243 2004-01-19 Chris Demetriou <cgd@broadcom.com>
245 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
246 (check_mult_hilo): Improve comments.
247 (check_div_hilo): Likewise. Also, fork off a new version
248 to handle mips32/mips64 (since there are no hazards to check
251 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
253 * mips.igen (do_dmultx): Fix check for negative operands.
255 2003-05-16 Ian Lance Taylor <ian@airs.com>
257 * Makefile.in (SHELL): Make sure this is defined.
258 (various): Use $(SHELL) whenever we invoke move-if-change.
260 2003-05-03 Chris Demetriou <cgd@broadcom.com>
262 * cp1.c: Tweak attribution slightly.
265 * mdmx.igen: Likewise.
266 * mips3d.igen: Likewise.
267 * sb1.igen: Likewise.
269 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
271 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
274 2003-02-27 Andrew Cagney <cagney@redhat.com>
276 * interp.c (sim_open): Rename _bfd to bfd.
277 (sim_create_inferior): Ditto.
279 2003-01-14 Chris Demetriou <cgd@broadcom.com>
281 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
283 2003-01-14 Chris Demetriou <cgd@broadcom.com>
285 * mips.igen (EI, DI): Remove.
287 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
289 * Makefile.in (tmp-run-multi): Fix mips16 filter.
291 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
292 Andrew Cagney <ac131313@redhat.com>
293 Gavin Romig-Koch <gavin@redhat.com>
294 Graydon Hoare <graydon@redhat.com>
295 Aldy Hernandez <aldyh@redhat.com>
296 Dave Brolley <brolley@redhat.com>
297 Chris Demetriou <cgd@broadcom.com>
299 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
300 (sim_mach_default): New variable.
301 (mips64vr-*-*, mips64vrel-*-*): New configurations.
302 Add a new simulator generator, MULTI.
303 * configure: Regenerate.
304 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
305 (multi-run.o): New dependency.
306 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
307 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
308 (tmp-multi): Combine them.
309 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
310 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
311 (distclean-extra): New rule.
312 * sim-main.h: Include bfd.h.
313 (MIPS_MACH): New macro.
314 * mips.igen (vr4120, vr5400, vr5500): New models.
315 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
316 * vr.igen: Replace with new version.
318 2003-01-04 Chris Demetriou <cgd@broadcom.com>
320 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
321 * configure: Regenerate.
323 2002-12-31 Chris Demetriou <cgd@broadcom.com>
325 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
326 * mips.igen: Remove all invocations of check_branch_bug and
329 2002-12-16 Chris Demetriou <cgd@broadcom.com>
331 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
333 2002-07-30 Chris Demetriou <cgd@broadcom.com>
335 * mips.igen (do_load_double, do_store_double): New functions.
336 (LDC1, SDC1): Rename to...
337 (LDC1b, SDC1b): respectively.
338 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
340 2002-07-29 Michael Snyder <msnyder@redhat.com>
342 * cp1.c (fp_recip2): Modify initialization expression so that
343 GCC will recognize it as constant.
345 2002-06-18 Chris Demetriou <cgd@broadcom.com>
347 * mdmx.c (SD_): Delete.
348 (Unpredictable): Re-define, for now, to directly invoke
349 unpredictable_action().
350 (mdmx_acc_op): Fix error in .ob immediate handling.
352 2002-06-18 Andrew Cagney <cagney@redhat.com>
354 * interp.c (sim_firmware_command): Initialize `address'.
356 2002-06-16 Andrew Cagney <ac131313@redhat.com>
358 * configure: Regenerated to track ../common/aclocal.m4 changes.
360 2002-06-14 Chris Demetriou <cgd@broadcom.com>
361 Ed Satterthwaite <ehs@broadcom.com>
363 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
364 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
365 * mips.igen: Include mips3d.igen.
366 (mips3d): New model name for MIPS-3D ASE instructions.
367 (CVT.W.fmt): Don't use this instruction for word (source) format
369 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
370 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
371 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
372 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
373 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
374 (RSquareRoot1, RSquareRoot2): New macros.
375 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
376 (fp_rsqrt2): New functions.
377 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
378 * configure: Regenerate.
380 2002-06-13 Chris Demetriou <cgd@broadcom.com>
381 Ed Satterthwaite <ehs@broadcom.com>
383 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
384 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
385 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
386 (convert): Note that this function is not used for paired-single
388 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
389 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
390 (check_fmt_p): Enable paired-single support.
391 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
392 (PUU.PS): New instructions.
393 (CVT.S.fmt): Don't use this instruction for paired-single format
395 * sim-main.h (FP_formats): New value 'fmt_ps.'
396 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
397 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
399 2002-06-12 Chris Demetriou <cgd@broadcom.com>
401 * mips.igen: Fix formatting of function calls in
404 2002-06-12 Chris Demetriou <cgd@broadcom.com>
406 * mips.igen (MOVN, MOVZ): Trace result.
407 (TNEI): Print "tnei" as the opcode name in traces.
408 (CEIL.W): Add disassembly string for traces.
409 (RSQRT.fmt): Make location of disassembly string consistent
410 with other instructions.
412 2002-06-12 Chris Demetriou <cgd@broadcom.com>
414 * mips.igen (X): Delete unused function.
416 2002-06-08 Andrew Cagney <cagney@redhat.com>
418 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
420 2002-06-07 Chris Demetriou <cgd@broadcom.com>
421 Ed Satterthwaite <ehs@broadcom.com>
423 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
424 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
425 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
426 (fp_nmsub): New prototypes.
427 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
428 (NegMultiplySub): New defines.
429 * mips.igen (RSQRT.fmt): Use RSquareRoot().
430 (MADD.D, MADD.S): Replace with...
431 (MADD.fmt): New instruction.
432 (MSUB.D, MSUB.S): Replace with...
433 (MSUB.fmt): New instruction.
434 (NMADD.D, NMADD.S): Replace with...
435 (NMADD.fmt): New instruction.
436 (NMSUB.D, MSUB.S): Replace with...
437 (NMSUB.fmt): New instruction.
439 2002-06-07 Chris Demetriou <cgd@broadcom.com>
440 Ed Satterthwaite <ehs@broadcom.com>
442 * cp1.c: Fix more comment spelling and formatting.
443 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
444 (denorm_mode): New function.
445 (fpu_unary, fpu_binary): Round results after operation, collect
446 status from rounding operations, and update the FCSR.
447 (convert): Collect status from integer conversions and rounding
448 operations, and update the FCSR. Adjust NaN values that result
449 from conversions. Convert to use sim_io_eprintf rather than
450 fprintf, and remove some debugging code.
451 * cp1.h (fenr_FS): New define.
453 2002-06-07 Chris Demetriou <cgd@broadcom.com>
455 * cp1.c (convert): Remove unusable debugging code, and move MIPS
456 rounding mode to sim FP rounding mode flag conversion code into...
457 (rounding_mode): New function.
459 2002-06-07 Chris Demetriou <cgd@broadcom.com>
461 * cp1.c: Clean up formatting of a few comments.
462 (value_fpr): Reformat switch statement.
464 2002-06-06 Chris Demetriou <cgd@broadcom.com>
465 Ed Satterthwaite <ehs@broadcom.com>
468 * sim-main.h: Include cp1.h.
469 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
470 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
471 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
472 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
473 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
474 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
475 * cp1.c: Don't include sim-fpu.h; already included by
476 sim-main.h. Clean up formatting of some comments.
477 (NaN, Equal, Less): Remove.
478 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
479 (fp_cmp): New functions.
480 * mips.igen (do_c_cond_fmt): Remove.
481 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
482 Compare. Add result tracing.
483 (CxC1): Remove, replace with...
484 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
485 (DMxC1): Remove, replace with...
486 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
487 (MxC1): Remove, replace with...
488 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
490 2002-06-04 Chris Demetriou <cgd@broadcom.com>
492 * sim-main.h (FGRIDX): Remove, replace all uses with...
493 (FGR_BASE): New macro.
494 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
495 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
496 (NR_FGR, FGR): Likewise.
497 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
498 * mips.igen: Likewise.
500 2002-06-04 Chris Demetriou <cgd@broadcom.com>
502 * cp1.c: Add an FSF Copyright notice to this file.
504 2002-06-04 Chris Demetriou <cgd@broadcom.com>
505 Ed Satterthwaite <ehs@broadcom.com>
507 * cp1.c (Infinity): Remove.
508 * sim-main.h (Infinity): Likewise.
510 * cp1.c (fp_unary, fp_binary): New functions.
511 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
512 (fp_sqrt): New functions, implemented in terms of the above.
513 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
514 (Recip, SquareRoot): Remove (replaced by functions above).
515 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
516 (fp_recip, fp_sqrt): New prototypes.
517 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
518 (Recip, SquareRoot): Replace prototypes with #defines which
519 invoke the functions above.
521 2002-06-03 Chris Demetriou <cgd@broadcom.com>
523 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
524 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
525 file, remove PARAMS from prototypes.
526 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
527 simulator state arguments.
528 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
529 pass simulator state arguments.
530 * cp1.c (SD): Redefine as CPU_STATE(cpu).
531 (store_fpr, convert): Remove 'sd' argument.
532 (value_fpr): Likewise. Convert to use 'SD' instead.
534 2002-06-03 Chris Demetriou <cgd@broadcom.com>
536 * cp1.c (Min, Max): Remove #if 0'd functions.
537 * sim-main.h (Min, Max): Remove.
539 2002-06-03 Chris Demetriou <cgd@broadcom.com>
541 * cp1.c: fix formatting of switch case and default labels.
542 * interp.c: Likewise.
543 * sim-main.c: Likewise.
545 2002-06-03 Chris Demetriou <cgd@broadcom.com>
547 * cp1.c: Clean up comments which describe FP formats.
548 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
550 2002-06-03 Chris Demetriou <cgd@broadcom.com>
551 Ed Satterthwaite <ehs@broadcom.com>
553 * configure.in (mipsisa64sb1*-*-*): New target for supporting
554 Broadcom SiByte SB-1 processor configurations.
555 * configure: Regenerate.
556 * sb1.igen: New file.
557 * mips.igen: Include sb1.igen.
559 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
560 * mdmx.igen: Add "sb1" model to all appropriate functions and
562 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
563 (ob_func, ob_acc): Reference the above.
564 (qh_acc): Adjust to keep the same size as ob_acc.
565 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
566 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
568 2002-06-03 Chris Demetriou <cgd@broadcom.com>
570 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
572 2002-06-02 Chris Demetriou <cgd@broadcom.com>
573 Ed Satterthwaite <ehs@broadcom.com>
575 * mips.igen (mdmx): New (pseudo-)model.
576 * mdmx.c, mdmx.igen: New files.
577 * Makefile.in (SIM_OBJS): Add mdmx.o.
578 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
580 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
581 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
582 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
583 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
584 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
585 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
586 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
587 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
588 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
589 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
590 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
591 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
592 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
593 (qh_fmtsel): New macros.
594 (_sim_cpu): New member "acc".
595 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
596 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
598 2002-05-01 Chris Demetriou <cgd@broadcom.com>
600 * interp.c: Use 'deprecated' rather than 'depreciated.'
601 * sim-main.h: Likewise.
603 2002-05-01 Chris Demetriou <cgd@broadcom.com>
605 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
606 which wouldn't compile anyway.
607 * sim-main.h (unpredictable_action): New function prototype.
608 (Unpredictable): Define to call igen function unpredictable().
609 (NotWordValue): New macro to call igen function not_word_value().
610 (UndefinedResult): Remove.
611 * interp.c (undefined_result): Remove.
612 (unpredictable_action): New function.
613 * mips.igen (not_word_value, unpredictable): New functions.
614 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
615 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
616 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
617 NotWordValue() to check for unpredictable inputs, then
618 Unpredictable() to handle them.
620 2002-02-24 Chris Demetriou <cgd@broadcom.com>
622 * mips.igen: Fix formatting of calls to Unpredictable().
624 2002-04-20 Andrew Cagney <ac131313@redhat.com>
626 * interp.c (sim_open): Revert previous change.
628 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
630 * interp.c (sim_open): Disable chunk of code that wrote code in
631 vector table entries.
633 2002-03-19 Chris Demetriou <cgd@broadcom.com>
635 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
636 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
639 2002-03-19 Chris Demetriou <cgd@broadcom.com>
641 * cp1.c: Fix many formatting issues.
643 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
645 * cp1.c (fpu_format_name): New function to replace...
646 (DOFMT): This. Delete, and update all callers.
647 (fpu_rounding_mode_name): New function to replace...
648 (RMMODE): This. Delete, and update all callers.
650 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
652 * interp.c: Move FPU support routines from here to...
653 * cp1.c: Here. New file.
654 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
657 2002-03-12 Chris Demetriou <cgd@broadcom.com>
659 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
660 * mips.igen (mips32, mips64): New models, add to all instructions
661 and functions as appropriate.
662 (loadstore_ea, check_u64): New variant for model mips64.
663 (check_fmt_p): New variant for models mipsV and mips64, remove
664 mipsV model marking fro other variant.
667 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
668 for mips32 and mips64.
669 (DCLO, DCLZ): New instructions for mips64.
671 2002-03-07 Chris Demetriou <cgd@broadcom.com>
673 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
674 immediate or code as a hex value with the "%#lx" format.
675 (ANDI): Likewise, and fix printed instruction name.
677 2002-03-05 Chris Demetriou <cgd@broadcom.com>
679 * sim-main.h (UndefinedResult, Unpredictable): New macros
680 which currently do nothing.
682 2002-03-05 Chris Demetriou <cgd@broadcom.com>
684 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
685 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
686 (status_CU3): New definitions.
688 * sim-main.h (ExceptionCause): Add new values for MIPS32
689 and MIPS64: MDMX, MCheck, CacheErr. Update comments
690 for DebugBreakPoint and NMIReset to note their status in
692 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
693 (SignalExceptionCacheErr): New exception macros.
695 2002-03-05 Chris Demetriou <cgd@broadcom.com>
697 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
698 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
700 (SignalExceptionCoProcessorUnusable): Take as argument the
701 unusable coprocessor number.
703 2002-03-05 Chris Demetriou <cgd@broadcom.com>
705 * mips.igen: Fix formatting of all SignalException calls.
707 2002-03-05 Chris Demetriou <cgd@broadcom.com>
709 * sim-main.h (SIGNEXTEND): Remove.
711 2002-03-04 Chris Demetriou <cgd@broadcom.com>
713 * mips.igen: Remove gencode comment from top of file, fix
714 spelling in another comment.
716 2002-03-04 Chris Demetriou <cgd@broadcom.com>
718 * mips.igen (check_fmt, check_fmt_p): New functions to check
719 whether specific floating point formats are usable.
720 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
721 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
722 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
723 Use the new functions.
724 (do_c_cond_fmt): Remove format checks...
725 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
727 2002-03-03 Chris Demetriou <cgd@broadcom.com>
729 * mips.igen: Fix formatting of check_fpu calls.
731 2002-03-03 Chris Demetriou <cgd@broadcom.com>
733 * mips.igen (FLOOR.L.fmt): Store correct destination register.
735 2002-03-03 Chris Demetriou <cgd@broadcom.com>
737 * mips.igen: Remove whitespace at end of lines.
739 2002-03-02 Chris Demetriou <cgd@broadcom.com>
741 * mips.igen (loadstore_ea): New function to do effective
742 address calculations.
743 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
744 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
745 CACHE): Use loadstore_ea to do effective address computations.
747 2002-03-02 Chris Demetriou <cgd@broadcom.com>
749 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
750 * mips.igen (LL, CxC1, MxC1): Likewise.
752 2002-03-02 Chris Demetriou <cgd@broadcom.com>
754 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
755 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
756 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
757 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
758 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
759 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
760 Don't split opcode fields by hand, use the opcode field values
763 2002-03-01 Chris Demetriou <cgd@broadcom.com>
765 * mips.igen (do_divu): Fix spacing.
767 * mips.igen (do_dsllv): Move to be right before DSLLV,
768 to match the rest of the do_<shift> functions.
770 2002-03-01 Chris Demetriou <cgd@broadcom.com>
772 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
773 DSRL32, do_dsrlv): Trace inputs and results.
775 2002-03-01 Chris Demetriou <cgd@broadcom.com>
777 * mips.igen (CACHE): Provide instruction-printing string.
779 * interp.c (signal_exception): Comment tokens after #endif.
781 2002-02-28 Chris Demetriou <cgd@broadcom.com>
783 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
784 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
785 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
786 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
787 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
788 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
789 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
790 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
792 2002-02-28 Chris Demetriou <cgd@broadcom.com>
794 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
795 instruction-printing string.
796 (LWU): Use '64' as the filter flag.
798 2002-02-28 Chris Demetriou <cgd@broadcom.com>
800 * mips.igen (SDXC1): Fix instruction-printing string.
802 2002-02-28 Chris Demetriou <cgd@broadcom.com>
804 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
807 2002-02-27 Chris Demetriou <cgd@broadcom.com>
809 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
812 2002-02-27 Chris Demetriou <cgd@broadcom.com>
814 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
815 add a comma) so that it more closely match the MIPS ISA
816 documentation opcode partitioning.
817 (PREF): Put useful names on opcode fields, and include
818 instruction-printing string.
820 2002-02-27 Chris Demetriou <cgd@broadcom.com>
822 * mips.igen (check_u64): New function which in the future will
823 check whether 64-bit instructions are usable and signal an
824 exception if not. Currently a no-op.
825 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
826 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
827 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
828 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
830 * mips.igen (check_fpu): New function which in the future will
831 check whether FPU instructions are usable and signal an exception
832 if not. Currently a no-op.
833 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
834 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
835 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
836 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
837 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
838 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
839 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
840 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
842 2002-02-27 Chris Demetriou <cgd@broadcom.com>
844 * mips.igen (do_load_left, do_load_right): Move to be immediately
846 (do_store_left, do_store_right): Move to be immediately following
849 2002-02-27 Chris Demetriou <cgd@broadcom.com>
851 * mips.igen (mipsV): New model name. Also, add it to
852 all instructions and functions where it is appropriate.
854 2002-02-18 Chris Demetriou <cgd@broadcom.com>
856 * mips.igen: For all functions and instructions, list model
857 names that support that instruction one per line.
859 2002-02-11 Chris Demetriou <cgd@broadcom.com>
861 * mips.igen: Add some additional comments about supported
862 models, and about which instructions go where.
863 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
864 order as is used in the rest of the file.
866 2002-02-11 Chris Demetriou <cgd@broadcom.com>
868 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
869 indicating that ALU32_END or ALU64_END are there to check
871 (DADD): Likewise, but also remove previous comment about
874 2002-02-10 Chris Demetriou <cgd@broadcom.com>
876 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
877 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
878 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
879 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
880 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
881 fields (i.e., add and move commas) so that they more closely
882 match the MIPS ISA documentation opcode partitioning.
884 2002-02-10 Chris Demetriou <cgd@broadcom.com>
886 * mips.igen (ADDI): Print immediate value.
888 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
889 (SLL): Print "nop" specially, and don't run the code
890 that does the shift for the "nop" case.
892 2001-11-17 Fred Fish <fnf@redhat.com>
894 * sim-main.h (float_operation): Move enum declaration outside
895 of _sim_cpu struct declaration.
897 2001-04-12 Jim Blandy <jimb@redhat.com>
899 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
900 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
902 * sim-main.h (COCIDX): Remove definition; this isn't supported by
903 PENDING_FILL, and you can get the intended effect gracefully by
904 calling PENDING_SCHED directly.
906 2001-02-23 Ben Elliston <bje@redhat.com>
908 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
909 already defined elsewhere.
911 2001-02-19 Ben Elliston <bje@redhat.com>
913 * sim-main.h (sim_monitor): Return an int.
914 * interp.c (sim_monitor): Add return values.
915 (signal_exception): Handle error conditions from sim_monitor.
917 2001-02-08 Ben Elliston <bje@redhat.com>
919 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
920 (store_memory): Likewise, pass cia to sim_core_write*.
922 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
924 On advice from Chris G. Demetriou <cgd@sibyte.com>:
925 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
927 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
929 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
930 * Makefile.in: Don't delete *.igen when cleaning directory.
932 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
934 * m16.igen (break): Call SignalException not sim_engine_halt.
936 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
939 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
941 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
943 * mips.igen (MxC1, DMxC1): Fix printf formatting.
945 2000-05-24 Michael Hayes <mhayes@cygnus.com>
947 * mips.igen (do_dmultx): Fix typo.
949 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
951 * configure: Regenerated to track ../common/aclocal.m4 changes.
953 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
955 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
957 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
959 * sim-main.h (GPR_CLEAR): Define macro.
961 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
963 * interp.c (decode_coproc): Output long using %lx and not %s.
965 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
967 * interp.c (sim_open): Sort & extend dummy memory regions for
968 --board=jmr3904 for eCos.
970 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
972 * configure: Regenerated.
974 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
976 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
977 calls, conditional on the simulator being in verbose mode.
979 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
981 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
982 cache don't get ReservedInstruction traps.
984 1999-11-29 Mark Salter <msalter@cygnus.com>
986 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
987 to clear status bits in sdisr register. This is how the hardware works.
989 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
990 being used by cygmon.
992 1999-11-11 Andrew Haley <aph@cygnus.com>
994 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
997 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
999 * mips.igen (MULT): Correct previous mis-applied patch.
1001 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1003 * mips.igen (delayslot32): Handle sequence like
1004 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1005 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1006 (MULT): Actually pass the third register...
1008 1999-09-03 Mark Salter <msalter@cygnus.com>
1010 * interp.c (sim_open): Added more memory aliases for additional
1011 hardware being touched by cygmon on jmr3904 board.
1013 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1015 * configure: Regenerated to track ../common/aclocal.m4 changes.
1017 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1019 * interp.c (sim_store_register): Handle case where client - GDB -
1020 specifies that a 4 byte register is 8 bytes in size.
1021 (sim_fetch_register): Ditto.
1023 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1025 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1026 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1027 (idt_monitor_base): Base address for IDT monitor traps.
1028 (pmon_monitor_base): Ditto for PMON.
1029 (lsipmon_monitor_base): Ditto for LSI PMON.
1030 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1031 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1032 (sim_firmware_command): New function.
1033 (mips_option_handler): Call it for OPTION_FIRMWARE.
1034 (sim_open): Allocate memory for idt_monitor region. If "--board"
1035 option was given, add no monitor by default. Add BREAK hooks only if
1036 monitors are also there.
1038 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1040 * interp.c (sim_monitor): Flush output before reading input.
1042 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1044 * tconfig.in (SIM_HANDLES_LMA): Always define.
1046 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1048 From Mark Salter <msalter@cygnus.com>:
1049 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1050 (sim_open): Add setup for BSP board.
1052 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1054 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1055 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1056 them as unimplemented.
1058 1999-05-08 Felix Lee <flee@cygnus.com>
1060 * configure: Regenerated to track ../common/aclocal.m4 changes.
1062 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1064 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1066 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1068 * configure.in: Any mips64vr5*-*-* target should have
1069 -DTARGET_ENABLE_FR=1.
1070 (default_endian): Any mips64vr*el-*-* target should default to
1072 * configure: Re-generate.
1074 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1076 * mips.igen (ldl): Extend from _16_, not 32.
1078 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1080 * interp.c (sim_store_register): Force registers written to by GDB
1081 into an un-interpreted state.
1083 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1085 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1086 CPU, start periodic background I/O polls.
1087 (tx3904sio_poll): New function: periodic I/O poller.
1089 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1091 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1093 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1095 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1098 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1100 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1101 (load_word): Call SIM_CORE_SIGNAL hook on error.
1102 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1103 starting. For exception dispatching, pass PC instead of NULL_CIA.
1104 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1105 * sim-main.h (COP0_BADVADDR): Define.
1106 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1107 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1108 (_sim_cpu): Add exc_* fields to store register value snapshots.
1109 * mips.igen (*): Replace memory-related SignalException* calls
1110 with references to SIM_CORE_SIGNAL hook.
1112 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1114 * sim-main.c (*): Minor warning cleanups.
1116 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1118 * m16.igen (DADDIU5): Correct type-o.
1120 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1122 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1125 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1127 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1129 (interp.o): Add dependency on itable.h
1130 (oengine.c, gencode): Delete remaining references.
1131 (BUILT_SRC_FROM_GEN): Clean up.
1133 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1136 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1137 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1138 tmp-run-hack) : New.
1139 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1140 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1141 Drop the "64" qualifier to get the HACK generator working.
1142 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1143 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1144 qualifier to get the hack generator working.
1145 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1146 (DSLL): Use do_dsll.
1147 (DSLLV): Use do_dsllv.
1148 (DSRA): Use do_dsra.
1149 (DSRL): Use do_dsrl.
1150 (DSRLV): Use do_dsrlv.
1151 (BC1): Move *vr4100 to get the HACK generator working.
1152 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1153 get the HACK generator working.
1154 (MACC) Rename to get the HACK generator working.
1155 (DMACC,MACCS,DMACCS): Add the 64.
1157 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1159 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1160 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1162 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1164 * mips/interp.c (DEBUG): Cleanups.
1166 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1168 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1169 (tx3904sio_tickle): fflush after a stdout character output.
1171 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1173 * interp.c (sim_close): Uninstall modules.
1175 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1177 * sim-main.h, interp.c (sim_monitor): Change to global
1180 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1182 * configure.in (vr4100): Only include vr4100 instructions in
1184 * configure: Re-generate.
1185 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1187 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1189 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1190 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1193 * configure.in (sim_default_gen, sim_use_gen): Replace with
1195 (--enable-sim-igen): Delete config option. Always using IGEN.
1196 * configure: Re-generate.
1198 * Makefile.in (gencode): Kill, kill, kill.
1201 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1203 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1204 bit mips16 igen simulator.
1205 * configure: Re-generate.
1207 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1208 as part of vr4100 ISA.
1209 * vr.igen: Mark all instructions as 64 bit only.
1211 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1213 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1216 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1218 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1219 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1220 * configure: Re-generate.
1222 * m16.igen (BREAK): Define breakpoint instruction.
1223 (JALX32): Mark instruction as mips16 and not r3900.
1224 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1226 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1228 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1230 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1231 insn as a debug breakpoint.
1233 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1235 (PENDING_SCHED): Clean up trace statement.
1236 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1237 (PENDING_FILL): Delay write by only one cycle.
1238 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1240 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1242 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1244 (pending_tick): Move incrementing of index to FOR statement.
1245 (pending_tick): Only update PENDING_OUT after a write has occured.
1247 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1249 * configure: Re-generate.
1251 * interp.c (sim_engine_run OLD): Delete explicit call to
1252 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1254 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1256 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1257 interrupt level number to match changed SignalExceptionInterrupt
1260 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1262 * interp.c: #include "itable.h" if WITH_IGEN.
1263 (get_insn_name): New function.
1264 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1265 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1267 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1269 * configure: Rebuilt to inhale new common/aclocal.m4.
1271 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1273 * dv-tx3904sio.c: Include sim-assert.h.
1275 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1277 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1278 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1279 Reorganize target-specific sim-hardware checks.
1280 * configure: rebuilt.
1281 * interp.c (sim_open): For tx39 target boards, set
1282 OPERATING_ENVIRONMENT, add tx3904sio devices.
1283 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1284 ROM executables. Install dv-sockser into sim-modules list.
1286 * dv-tx3904irc.c: Compiler warning clean-up.
1287 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1288 frequent hw-trace messages.
1290 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1292 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1294 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1296 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1298 * vr.igen: New file.
1299 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1300 * mips.igen: Define vr4100 model. Include vr.igen.
1301 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1303 * mips.igen (check_mf_hilo): Correct check.
1305 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1307 * sim-main.h (interrupt_event): Add prototype.
1309 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1310 register_ptr, register_value.
1311 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1313 * sim-main.h (tracefh): Make extern.
1315 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1317 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1318 Reduce unnecessarily high timer event frequency.
1319 * dv-tx3904cpu.c: Ditto for interrupt event.
1321 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1323 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1325 (interrupt_event): Made non-static.
1327 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1328 interchange of configuration values for external vs. internal
1331 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1333 * mips.igen (BREAK): Moved code to here for
1334 simulator-reserved break instructions.
1335 * gencode.c (build_instruction): Ditto.
1336 * interp.c (signal_exception): Code moved from here. Non-
1337 reserved instructions now use exception vector, rather
1339 * sim-main.h: Moved magic constants to here.
1341 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1343 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1344 register upon non-zero interrupt event level, clear upon zero
1346 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1347 by passing zero event value.
1348 (*_io_{read,write}_buffer): Endianness fixes.
1349 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1350 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1352 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1353 serial I/O and timer module at base address 0xFFFF0000.
1355 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1357 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1360 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1362 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1364 * configure: Update.
1366 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1368 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1369 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1370 * configure.in: Include tx3904tmr in hw_device list.
1371 * configure: Rebuilt.
1372 * interp.c (sim_open): Instantiate three timer instances.
1373 Fix address typo of tx3904irc instance.
1375 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1377 * interp.c (signal_exception): SystemCall exception now uses
1378 the exception vector.
1380 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1382 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1385 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1387 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1389 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1391 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1393 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1394 sim-main.h. Declare a struct hw_descriptor instead of struct
1395 hw_device_descriptor.
1397 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1399 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1400 right bits and then re-align left hand bytes to correct byte
1401 lanes. Fix incorrect computation in do_store_left when loading
1402 bytes from second word.
1404 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1406 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1407 * interp.c (sim_open): Only create a device tree when HW is
1410 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1411 * interp.c (signal_exception): Ditto.
1413 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1415 * gencode.c: Mark BEGEZALL as LIKELY.
1417 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1419 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1420 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1422 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1424 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1425 modules. Recognize TX39 target with "mips*tx39" pattern.
1426 * configure: Rebuilt.
1427 * sim-main.h (*): Added many macros defining bits in
1428 TX39 control registers.
1429 (SignalInterrupt): Send actual PC instead of NULL.
1430 (SignalNMIReset): New exception type.
1431 * interp.c (board): New variable for future use to identify
1432 a particular board being simulated.
1433 (mips_option_handler,mips_options): Added "--board" option.
1434 (interrupt_event): Send actual PC.
1435 (sim_open): Make memory layout conditional on board setting.
1436 (signal_exception): Initial implementation of hardware interrupt
1437 handling. Accept another break instruction variant for simulator
1439 (decode_coproc): Implement RFE instruction for TX39.
1440 (mips.igen): Decode RFE instruction as such.
1441 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1442 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1443 bbegin to implement memory map.
1444 * dv-tx3904cpu.c: New file.
1445 * dv-tx3904irc.c: New file.
1447 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1449 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1451 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1453 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1454 with calls to check_div_hilo.
1456 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1458 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1459 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1460 Add special r3900 version of do_mult_hilo.
1461 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1462 with calls to check_mult_hilo.
1463 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1464 with calls to check_div_hilo.
1466 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1468 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1469 Document a replacement.
1471 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1473 * interp.c (sim_monitor): Make mon_printf work.
1475 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1477 * sim-main.h (INSN_NAME): New arg `cpu'.
1479 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1481 * configure: Regenerated to track ../common/aclocal.m4 changes.
1483 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1485 * configure: Regenerated to track ../common/aclocal.m4 changes.
1488 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1490 * acconfig.h: New file.
1491 * configure.in: Reverted change of Apr 24; use sinclude again.
1493 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1495 * configure: Regenerated to track ../common/aclocal.m4 changes.
1498 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1500 * configure.in: Don't call sinclude.
1502 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1504 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1506 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1508 * mips.igen (ERET): Implement.
1510 * interp.c (decode_coproc): Return sign-extended EPC.
1512 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1514 * interp.c (signal_exception): Do not ignore Trap.
1515 (signal_exception): On TRAP, restart at exception address.
1516 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1517 (signal_exception): Update.
1518 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1519 so that TRAP instructions are caught.
1521 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1523 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1524 contains HI/LO access history.
1525 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1526 (HIACCESS, LOACCESS): Delete, replace with
1527 (HIHISTORY, LOHISTORY): New macros.
1528 (CHECKHILO): Delete all, moved to mips.igen
1530 * gencode.c (build_instruction): Do not generate checks for
1531 correct HI/LO register usage.
1533 * interp.c (old_engine_run): Delete checks for correct HI/LO
1536 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1537 check_mf_cycles): New functions.
1538 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1539 do_divu, domultx, do_mult, do_multu): Use.
1541 * tx.igen ("madd", "maddu"): Use.
1543 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1545 * mips.igen (DSRAV): Use function do_dsrav.
1546 (SRAV): Use new function do_srav.
1548 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1549 (B): Sign extend 11 bit immediate.
1550 (EXT-B*): Shift 16 bit immediate left by 1.
1551 (ADDIU*): Don't sign extend immediate value.
1553 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1555 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1557 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1560 * mips.igen (delayslot32, nullify_next_insn): New functions.
1561 (m16.igen): Always include.
1562 (do_*): Add more tracing.
1564 * m16.igen (delayslot16): Add NIA argument, could be called by a
1565 32 bit MIPS16 instruction.
1567 * interp.c (ifetch16): Move function from here.
1568 * sim-main.c (ifetch16): To here.
1570 * sim-main.c (ifetch16, ifetch32): Update to match current
1571 implementations of LH, LW.
1572 (signal_exception): Don't print out incorrect hex value of illegal
1575 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1577 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1580 * m16.igen: Implement MIPS16 instructions.
1582 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1583 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1584 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1585 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1586 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1587 bodies of corresponding code from 32 bit insn to these. Also used
1588 by MIPS16 versions of functions.
1590 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1591 (IMEM16): Drop NR argument from macro.
1593 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1595 * Makefile.in (SIM_OBJS): Add sim-main.o.
1597 * sim-main.h (address_translation, load_memory, store_memory,
1598 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1600 (pr_addr, pr_uword64): Declare.
1601 (sim-main.c): Include when H_REVEALS_MODULE_P.
1603 * interp.c (address_translation, load_memory, store_memory,
1604 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1606 * sim-main.c: To here. Fix compilation problems.
1608 * configure.in: Enable inlining.
1609 * configure: Re-config.
1611 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1613 * configure: Regenerated to track ../common/aclocal.m4 changes.
1615 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1617 * mips.igen: Include tx.igen.
1618 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1619 * tx.igen: New file, contains MADD and MADDU.
1621 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1622 the hardwired constant `7'.
1623 (store_memory): Ditto.
1624 (LOADDRMASK): Move definition to sim-main.h.
1626 mips.igen (MTC0): Enable for r3900.
1629 mips.igen (do_load_byte): Delete.
1630 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1631 do_store_right): New functions.
1632 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1634 configure.in: Let the tx39 use igen again.
1637 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1639 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1640 not an address sized quantity. Return zero for cache sizes.
1642 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1644 * mips.igen (r3900): r3900 does not support 64 bit integer
1647 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1649 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1651 * configure : Rebuild.
1653 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1655 * configure: Regenerated to track ../common/aclocal.m4 changes.
1657 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1659 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1661 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1663 * configure: Regenerated to track ../common/aclocal.m4 changes.
1664 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1666 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1668 * configure: Regenerated to track ../common/aclocal.m4 changes.
1670 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1672 * interp.c (Max, Min): Comment out functions. Not yet used.
1674 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1676 * configure: Regenerated to track ../common/aclocal.m4 changes.
1678 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1680 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1681 configurable settings for stand-alone simulator.
1683 * configure.in: Added X11 search, just in case.
1685 * configure: Regenerated.
1687 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1689 * interp.c (sim_write, sim_read, load_memory, store_memory):
1690 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1692 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1694 * sim-main.h (GETFCC): Return an unsigned value.
1696 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1698 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1699 (DADD): Result destination is RD not RT.
1701 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1703 * sim-main.h (HIACCESS, LOACCESS): Always define.
1705 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1707 * interp.c (sim_info): Delete.
1709 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1711 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1712 (mips_option_handler): New argument `cpu'.
1713 (sim_open): Update call to sim_add_option_table.
1715 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1717 * mips.igen (CxC1): Add tracing.
1719 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1721 * sim-main.h (Max, Min): Declare.
1723 * interp.c (Max, Min): New functions.
1725 * mips.igen (BC1): Add tracing.
1727 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1729 * interp.c Added memory map for stack in vr4100
1731 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1733 * interp.c (load_memory): Add missing "break"'s.
1735 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1737 * interp.c (sim_store_register, sim_fetch_register): Pass in
1738 length parameter. Return -1.
1740 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1742 * interp.c: Added hardware init hook, fixed warnings.
1744 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1746 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1748 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1750 * interp.c (ifetch16): New function.
1752 * sim-main.h (IMEM32): Rename IMEM.
1753 (IMEM16_IMMED): Define.
1755 (DELAY_SLOT): Update.
1757 * m16run.c (sim_engine_run): New file.
1759 * m16.igen: All instructions except LB.
1760 (LB): Call do_load_byte.
1761 * mips.igen (do_load_byte): New function.
1762 (LB): Call do_load_byte.
1764 * mips.igen: Move spec for insn bit size and high bit from here.
1765 * Makefile.in (tmp-igen, tmp-m16): To here.
1767 * m16.dc: New file, decode mips16 instructions.
1769 * Makefile.in (SIM_NO_ALL): Define.
1770 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1772 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1774 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1775 point unit to 32 bit registers.
1776 * configure: Re-generate.
1778 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1780 * configure.in (sim_use_gen): Make IGEN the default simulator
1781 generator for generic 32 and 64 bit mips targets.
1782 * configure: Re-generate.
1784 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1786 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1789 * interp.c (sim_fetch_register, sim_store_register): Read/write
1790 FGR from correct location.
1791 (sim_open): Set size of FGR's according to
1792 WITH_TARGET_FLOATING_POINT_BITSIZE.
1794 * sim-main.h (FGR): Store floating point registers in a separate
1797 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1799 * configure: Regenerated to track ../common/aclocal.m4 changes.
1801 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1803 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1805 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1807 * interp.c (pending_tick): New function. Deliver pending writes.
1809 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1810 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1811 it can handle mixed sized quantites and single bits.
1813 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1815 * interp.c (oengine.h): Do not include when building with IGEN.
1816 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1817 (sim_info): Ditto for PROCESSOR_64BIT.
1818 (sim_monitor): Replace ut_reg with unsigned_word.
1819 (*): Ditto for t_reg.
1820 (LOADDRMASK): Define.
1821 (sim_open): Remove defunct check that host FP is IEEE compliant,
1822 using software to emulate floating point.
1823 (value_fpr, ...): Always compile, was conditional on HASFPU.
1825 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1827 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1830 * interp.c (SD, CPU): Define.
1831 (mips_option_handler): Set flags in each CPU.
1832 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1833 (sim_close): Do not clear STATE, deleted anyway.
1834 (sim_write, sim_read): Assume CPU zero's vm should be used for
1836 (sim_create_inferior): Set the PC for all processors.
1837 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1839 (mips16_entry): Pass correct nr of args to store_word, load_word.
1840 (ColdReset): Cold reset all cpu's.
1841 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1842 (sim_monitor, load_memory, store_memory, signal_exception): Use
1843 `CPU' instead of STATE_CPU.
1846 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1849 * sim-main.h (signal_exception): Add sim_cpu arg.
1850 (SignalException*): Pass both SD and CPU to signal_exception.
1851 * interp.c (signal_exception): Update.
1853 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1855 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1856 address_translation): Ditto
1857 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1859 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1861 * configure: Regenerated to track ../common/aclocal.m4 changes.
1863 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1865 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1867 * mips.igen (model): Map processor names onto BFD name.
1869 * sim-main.h (CPU_CIA): Delete.
1870 (SET_CIA, GET_CIA): Define
1872 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1874 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1877 * configure.in (default_endian): Configure a big-endian simulator
1879 * configure: Re-generate.
1881 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1883 * configure: Regenerated to track ../common/aclocal.m4 changes.
1885 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1887 * interp.c (sim_monitor): Handle Densan monitor outbyte
1888 and inbyte functions.
1890 1997-12-29 Felix Lee <flee@cygnus.com>
1892 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1894 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1896 * Makefile.in (tmp-igen): Arrange for $zero to always be
1897 reset to zero after every instruction.
1899 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1901 * configure: Regenerated to track ../common/aclocal.m4 changes.
1904 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1906 * mips.igen (MSUB): Fix to work like MADD.
1907 * gencode.c (MSUB): Similarly.
1909 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1911 * configure: Regenerated to track ../common/aclocal.m4 changes.
1913 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1917 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1919 * sim-main.h (sim-fpu.h): Include.
1921 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1922 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1923 using host independant sim_fpu module.
1925 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1927 * interp.c (signal_exception): Report internal errors with SIGABRT
1930 * sim-main.h (C0_CONFIG): New register.
1931 (signal.h): No longer include.
1933 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1935 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1937 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1939 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1941 * mips.igen: Tag vr5000 instructions.
1942 (ANDI): Was missing mipsIV model, fix assembler syntax.
1943 (do_c_cond_fmt): New function.
1944 (C.cond.fmt): Handle mips I-III which do not support CC field
1946 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1947 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1949 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1950 vr5000 which saves LO in a GPR separatly.
1952 * configure.in (enable-sim-igen): For vr5000, select vr5000
1953 specific instructions.
1954 * configure: Re-generate.
1956 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1958 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1960 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1961 fmt_uninterpreted_64 bit cases to switch. Convert to
1964 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1966 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1967 as specified in IV3.2 spec.
1968 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1970 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1972 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1973 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1974 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1975 PENDING_FILL versions of instructions. Simplify.
1977 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1979 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1981 (MTHI, MFHI): Disable code checking HI-LO.
1983 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1985 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1987 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1989 * gencode.c (build_mips16_operands): Replace IPC with cia.
1991 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1992 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1994 (UndefinedResult): Replace function with macro/function
1996 (sim_engine_run): Don't save PC in IPC.
1998 * sim-main.h (IPC): Delete.
2001 * interp.c (signal_exception, store_word, load_word,
2002 address_translation, load_memory, store_memory, cache_op,
2003 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2004 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2005 current instruction address - cia - argument.
2006 (sim_read, sim_write): Call address_translation directly.
2007 (sim_engine_run): Rename variable vaddr to cia.
2008 (signal_exception): Pass cia to sim_monitor
2010 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2011 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2012 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2014 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2015 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2018 * interp.c (signal_exception): Pass restart address to
2021 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2022 idecode.o): Add dependency.
2024 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2026 (DELAY_SLOT): Update NIA not PC with branch address.
2027 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2029 * mips.igen: Use CIA not PC in branch calculations.
2030 (illegal): Call SignalException.
2031 (BEQ, ADDIU): Fix assembler.
2033 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2035 * m16.igen (JALX): Was missing.
2037 * configure.in (enable-sim-igen): New configuration option.
2038 * configure: Re-generate.
2040 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2042 * interp.c (load_memory, store_memory): Delete parameter RAW.
2043 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2044 bypassing {load,store}_memory.
2046 * sim-main.h (ByteSwapMem): Delete definition.
2048 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2050 * interp.c (sim_do_command, sim_commands): Delete mips specific
2051 commands. Handled by module sim-options.
2053 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2054 (WITH_MODULO_MEMORY): Define.
2056 * interp.c (sim_info): Delete code printing memory size.
2058 * interp.c (mips_size): Nee sim_size, delete function.
2060 (monitor, monitor_base, monitor_size): Delete global variables.
2061 (sim_open, sim_close): Delete code creating monitor and other
2062 memory regions. Use sim-memopts module, via sim_do_commandf, to
2063 manage memory regions.
2064 (load_memory, store_memory): Use sim-core for memory model.
2066 * interp.c (address_translation): Delete all memory map code
2067 except line forcing 32 bit addresses.
2069 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2071 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2074 * interp.c (logfh, logfile): Delete globals.
2075 (sim_open, sim_close): Delete code opening & closing log file.
2076 (mips_option_handler): Delete -l and -n options.
2077 (OPTION mips_options): Ditto.
2079 * interp.c (OPTION mips_options): Rename option trace to dinero.
2080 (mips_option_handler): Update.
2082 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2084 * interp.c (fetch_str): New function.
2085 (sim_monitor): Rewrite using sim_read & sim_write.
2086 (sim_open): Check magic number.
2087 (sim_open): Write monitor vectors into memory using sim_write.
2088 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2089 (sim_read, sim_write): Simplify - transfer data one byte at a
2091 (load_memory, store_memory): Clarify meaning of parameter RAW.
2093 * sim-main.h (isHOST): Defete definition.
2094 (isTARGET): Mark as depreciated.
2095 (address_translation): Delete parameter HOST.
2097 * interp.c (address_translation): Delete parameter HOST.
2099 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2103 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2104 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2106 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2108 * mips.igen: Add model filter field to records.
2110 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2112 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2114 interp.c (sim_engine_run): Do not compile function sim_engine_run
2115 when WITH_IGEN == 1.
2117 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2118 target architecture.
2120 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2121 igen. Replace with configuration variables sim_igen_flags /
2124 * m16.igen: New file. Copy mips16 insns here.
2125 * mips.igen: From here.
2127 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2129 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2131 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2133 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2135 * gencode.c (build_instruction): Follow sim_write's lead in using
2136 BigEndianMem instead of !ByteSwapMem.
2138 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2140 * configure.in (sim_gen): Dependent on target, select type of
2141 generator. Always select old style generator.
2143 configure: Re-generate.
2145 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2147 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2148 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2149 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2150 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2151 SIM_@sim_gen@_*, set by autoconf.
2153 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2155 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2157 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2158 CURRENT_FLOATING_POINT instead.
2160 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2161 (address_translation): Raise exception InstructionFetch when
2162 translation fails and isINSTRUCTION.
2164 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2165 sim_engine_run): Change type of of vaddr and paddr to
2167 (address_translation, prefetch, load_memory, store_memory,
2168 cache_op): Change type of vAddr and pAddr to address_word.
2170 * gencode.c (build_instruction): Change type of vaddr and paddr to
2173 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2175 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2176 macro to obtain result of ALU op.
2178 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180 * interp.c (sim_info): Call profile_print.
2182 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2186 * sim-main.h (WITH_PROFILE): Do not define, defined in
2187 common/sim-config.h. Use sim-profile module.
2188 (simPROFILE): Delete defintion.
2190 * interp.c (PROFILE): Delete definition.
2191 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2192 (sim_close): Delete code writing profile histogram.
2193 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2195 (sim_engine_run): Delete code profiling the PC.
2197 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2199 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2201 * interp.c (sim_monitor): Make register pointers of type
2204 * sim-main.h: Make registers of type unsigned_word not
2207 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2209 * interp.c (sync_operation): Rename from SyncOperation, make
2210 global, add SD argument.
2211 (prefetch): Rename from Prefetch, make global, add SD argument.
2212 (decode_coproc): Make global.
2214 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2216 * gencode.c (build_instruction): Generate DecodeCoproc not
2217 decode_coproc calls.
2219 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2220 (SizeFGR): Move to sim-main.h
2221 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2222 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2223 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2225 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2226 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2227 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2228 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2229 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2230 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2232 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2234 (sim-alu.h): Include.
2235 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2236 (sim_cia): Typedef to instruction_address.
2238 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2240 * Makefile.in (interp.o): Rename generated file engine.c to
2245 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2247 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2249 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2251 * gencode.c (build_instruction): For "FPSQRT", output correct
2252 number of arguments to Recip.
2254 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2256 * Makefile.in (interp.o): Depends on sim-main.h
2258 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2260 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2261 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2262 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2263 STATE, DSSTATE): Define
2264 (GPR, FGRIDX, ..): Define.
2266 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2267 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2268 (GPR, FGRIDX, ...): Delete macros.
2270 * interp.c: Update names to match defines from sim-main.h
2272 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2274 * interp.c (sim_monitor): Add SD argument.
2275 (sim_warning): Delete. Replace calls with calls to
2277 (sim_error): Delete. Replace calls with sim_io_error.
2278 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2279 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2280 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2282 (mips_size): Rename from sim_size. Add SD argument.
2284 * interp.c (simulator): Delete global variable.
2285 (callback): Delete global variable.
2286 (mips_option_handler, sim_open, sim_write, sim_read,
2287 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2288 sim_size,sim_monitor): Use sim_io_* not callback->*.
2289 (sim_open): ZALLOC simulator struct.
2290 (PROFILE): Do not define.
2292 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2294 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2295 support.h with corresponding code.
2297 * sim-main.h (word64, uword64), support.h: Move definition to
2299 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2302 * Makefile.in: Update dependencies
2303 * interp.c: Do not include.
2305 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2307 * interp.c (address_translation, load_memory, store_memory,
2308 cache_op): Rename to from AddressTranslation et.al., make global,
2311 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2314 * interp.c (SignalException): Rename to signal_exception, make
2317 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2319 * sim-main.h (SignalException, SignalExceptionInterrupt,
2320 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2321 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2322 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2325 * interp.c, support.h: Use.
2327 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2329 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2330 to value_fpr / store_fpr. Add SD argument.
2331 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2332 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2334 * sim-main.h (ValueFPR, StoreFPR): Define.
2336 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2338 * interp.c (sim_engine_run): Check consistency between configure
2339 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2342 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2343 (mips_fpu): Configure WITH_FLOATING_POINT.
2344 (mips_endian): Configure WITH_TARGET_ENDIAN.
2345 * configure: Update.
2347 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2349 * configure: Regenerated to track ../common/aclocal.m4 changes.
2351 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2353 * configure: Regenerated.
2355 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2357 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2359 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2361 * gencode.c (print_igen_insn_models): Assume certain architectures
2362 include all mips* instructions.
2363 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2366 * Makefile.in (tmp.igen): Add target. Generate igen input from
2369 * gencode.c (FEATURE_IGEN): Define.
2370 (main): Add --igen option. Generate output in igen format.
2371 (process_instructions): Format output according to igen option.
2372 (print_igen_insn_format): New function.
2373 (print_igen_insn_models): New function.
2374 (process_instructions): Only issue warnings and ignore
2375 instructions when no FEATURE_IGEN.
2377 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2379 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2382 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2384 * configure: Regenerated to track ../common/aclocal.m4 changes.
2386 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2388 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2389 SIM_RESERVED_BITS): Delete, moved to common.
2390 (SIM_EXTRA_CFLAGS): Update.
2392 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2394 * configure.in: Configure non-strict memory alignment.
2395 * configure: Regenerated to track ../common/aclocal.m4 changes.
2397 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2399 * configure: Regenerated to track ../common/aclocal.m4 changes.
2401 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2403 * gencode.c (SDBBP,DERET): Added (3900) insns.
2404 (RFE): Turn on for 3900.
2405 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2406 (dsstate): Made global.
2407 (SUBTARGET_R3900): Added.
2408 (CANCELDELAYSLOT): New.
2409 (SignalException): Ignore SystemCall rather than ignore and
2410 terminate. Add DebugBreakPoint handling.
2411 (decode_coproc): New insns RFE, DERET; and new registers Debug
2412 and DEPC protected by SUBTARGET_R3900.
2413 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2415 * Makefile.in,configure.in: Add mips subtarget option.
2416 * configure: Update.
2418 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2420 * gencode.c: Add r3900 (tx39).
2423 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2425 * gencode.c (build_instruction): Don't need to subtract 4 for
2428 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2430 * interp.c: Correct some HASFPU problems.
2432 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2434 * configure: Regenerated to track ../common/aclocal.m4 changes.
2436 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2438 * interp.c (mips_options): Fix samples option short form, should
2441 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2443 * interp.c (sim_info): Enable info code. Was just returning.
2445 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2447 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2450 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2452 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2454 (build_instruction): Ditto for LL.
2456 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2458 * configure: Regenerated to track ../common/aclocal.m4 changes.
2460 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2462 * configure: Regenerated to track ../common/aclocal.m4 changes.
2465 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2467 * interp.c (sim_open): Add call to sim_analyze_program, update
2470 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2472 * interp.c (sim_kill): Delete.
2473 (sim_create_inferior): Add ABFD argument. Set PC from same.
2474 (sim_load): Move code initializing trap handlers from here.
2475 (sim_open): To here.
2476 (sim_load): Delete, use sim-hload.c.
2478 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2480 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2482 * configure: Regenerated to track ../common/aclocal.m4 changes.
2485 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2487 * interp.c (sim_open): Add ABFD argument.
2488 (sim_load): Move call to sim_config from here.
2489 (sim_open): To here. Check return status.
2491 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2493 * gencode.c (build_instruction): Two arg MADD should
2494 not assign result to $0.
2496 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2498 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2499 * sim/mips/configure.in: Regenerate.
2501 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2503 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2504 signed8, unsigned8 et.al. types.
2506 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2507 hosts when selecting subreg.
2509 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2511 * interp.c (sim_engine_run): Reset the ZERO register to zero
2512 regardless of FEATURE_WARN_ZERO.
2513 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2515 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2517 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2518 (SignalException): For BreakPoints ignore any mode bits and just
2520 (SignalException): Always set the CAUSE register.
2522 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2524 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2525 exception has been taken.
2527 * interp.c: Implement the ERET and mt/f sr instructions.
2529 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2531 * interp.c (SignalException): Don't bother restarting an
2534 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2536 * interp.c (SignalException): Really take an interrupt.
2537 (interrupt_event): Only deliver interrupts when enabled.
2539 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2541 * interp.c (sim_info): Only print info when verbose.
2542 (sim_info) Use sim_io_printf for output.
2544 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2546 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2549 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2551 * interp.c (sim_do_command): Check for common commands if a
2552 simulator specific command fails.
2554 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2556 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2557 and simBE when DEBUG is defined.
2559 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2561 * interp.c (interrupt_event): New function. Pass exception event
2562 onto exception handler.
2564 * configure.in: Check for stdlib.h.
2565 * configure: Regenerate.
2567 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2568 variable declaration.
2569 (build_instruction): Initialize memval1.
2570 (build_instruction): Add UNUSED attribute to byte, bigend,
2572 (build_operands): Ditto.
2574 * interp.c: Fix GCC warnings.
2575 (sim_get_quit_code): Delete.
2577 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2578 * Makefile.in: Ditto.
2579 * configure: Re-generate.
2581 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2583 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2585 * interp.c (mips_option_handler): New function parse argumes using
2587 (myname): Replace with STATE_MY_NAME.
2588 (sim_open): Delete check for host endianness - performed by
2590 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2591 (sim_open): Move much of the initialization from here.
2592 (sim_load): To here. After the image has been loaded and
2594 (sim_open): Move ColdReset from here.
2595 (sim_create_inferior): To here.
2596 (sim_open): Make FP check less dependant on host endianness.
2598 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2600 * interp.c (sim_set_callbacks): Delete.
2602 * interp.c (membank, membank_base, membank_size): Replace with
2603 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2604 (sim_open): Remove call to callback->init. gdb/run do this.
2608 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2610 * interp.c (big_endian_p): Delete, replaced by
2611 current_target_byte_order.
2613 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2615 * interp.c (host_read_long, host_read_word, host_swap_word,
2616 host_swap_long): Delete. Using common sim-endian.
2617 (sim_fetch_register, sim_store_register): Use H2T.
2618 (pipeline_ticks): Delete. Handled by sim-events.
2620 (sim_engine_run): Update.
2622 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2624 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2626 (SignalException): To here. Signal using sim_engine_halt.
2627 (sim_stop_reason): Delete, moved to common.
2629 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2631 * interp.c (sim_open): Add callback argument.
2632 (sim_set_callbacks): Delete SIM_DESC argument.
2635 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2637 * Makefile.in (SIM_OBJS): Add common modules.
2639 * interp.c (sim_set_callbacks): Also set SD callback.
2640 (set_endianness, xfer_*, swap_*): Delete.
2641 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2642 Change to functions using sim-endian macros.
2643 (control_c, sim_stop): Delete, use common version.
2644 (simulate): Convert into.
2645 (sim_engine_run): This function.
2646 (sim_resume): Delete.
2648 * interp.c (simulation): New variable - the simulator object.
2649 (sim_kind): Delete global - merged into simulation.
2650 (sim_load): Cleanup. Move PC assignment from here.
2651 (sim_create_inferior): To here.
2653 * sim-main.h: New file.
2654 * interp.c (sim-main.h): Include.
2656 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2658 * configure: Regenerated to track ../common/aclocal.m4 changes.
2660 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2662 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2664 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2666 * gencode.c (build_instruction): DIV instructions: check
2667 for division by zero and integer overflow before using
2668 host's division operation.
2670 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2672 * Makefile.in (SIM_OBJS): Add sim-load.o.
2673 * interp.c: #include bfd.h.
2674 (target_byte_order): Delete.
2675 (sim_kind, myname, big_endian_p): New static locals.
2676 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2677 after argument parsing. Recognize -E arg, set endianness accordingly.
2678 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2679 load file into simulator. Set PC from bfd.
2680 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2681 (set_endianness): Use big_endian_p instead of target_byte_order.
2683 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2685 * interp.c (sim_size): Delete prototype - conflicts with
2686 definition in remote-sim.h. Correct definition.
2688 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2690 * configure: Regenerated to track ../common/aclocal.m4 changes.
2693 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2695 * interp.c (sim_open): New arg `kind'.
2697 * configure: Regenerated to track ../common/aclocal.m4 changes.
2699 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2701 * configure: Regenerated to track ../common/aclocal.m4 changes.
2703 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2705 * interp.c (sim_open): Set optind to 0 before calling getopt.
2707 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2709 * configure: Regenerated to track ../common/aclocal.m4 changes.
2711 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2713 * interp.c : Replace uses of pr_addr with pr_uword64
2714 where the bit length is always 64 independent of SIM_ADDR.
2715 (pr_uword64) : added.
2717 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2719 * configure: Re-generate.
2721 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2723 * configure: Regenerate to track ../common/aclocal.m4 changes.
2725 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2727 * interp.c (sim_open): New SIM_DESC result. Argument is now
2729 (other sim_*): New SIM_DESC argument.
2731 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2733 * interp.c: Fix printing of addresses for non-64-bit targets.
2734 (pr_addr): Add function to print address based on size.
2736 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2738 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2740 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2742 * gencode.c (build_mips16_operands): Correct computation of base
2743 address for extended PC relative instruction.
2745 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2747 * interp.c (mips16_entry): Add support for floating point cases.
2748 (SignalException): Pass floating point cases to mips16_entry.
2749 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2751 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2753 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2754 and then set the state to fmt_uninterpreted.
2755 (COP_SW): Temporarily set the state to fmt_word while calling
2758 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2760 * gencode.c (build_instruction): The high order may be set in the
2761 comparison flags at any ISA level, not just ISA 4.
2763 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2765 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2766 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2767 * configure.in: sinclude ../common/aclocal.m4.
2768 * configure: Regenerated.
2770 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2772 * configure: Rebuild after change to aclocal.m4.
2774 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2776 * configure configure.in Makefile.in: Update to new configure
2777 scheme which is more compatible with WinGDB builds.
2778 * configure.in: Improve comment on how to run autoconf.
2779 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2780 * Makefile.in: Use autoconf substitution to install common
2783 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2785 * gencode.c (build_instruction): Use BigEndianCPU instead of
2788 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2790 * interp.c (sim_monitor): Make output to stdout visible in
2791 wingdb's I/O log window.
2793 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2795 * support.h: Undo previous change to SIGTRAP
2798 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2800 * interp.c (store_word, load_word): New static functions.
2801 (mips16_entry): New static function.
2802 (SignalException): Look for mips16 entry and exit instructions.
2803 (simulate): Use the correct index when setting fpr_state after
2804 doing a pending move.
2806 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2808 * interp.c: Fix byte-swapping code throughout to work on
2809 both little- and big-endian hosts.
2811 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2813 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2814 with gdb/config/i386/xm-windows.h.
2816 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2818 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2819 that messes up arithmetic shifts.
2821 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2823 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2824 SIGTRAP and SIGQUIT for _WIN32.
2826 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2828 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2829 force a 64 bit multiplication.
2830 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2831 destination register is 0, since that is the default mips16 nop
2834 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2836 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2837 (build_endian_shift): Don't check proc64.
2838 (build_instruction): Always set memval to uword64. Cast op2 to
2839 uword64 when shifting it left in memory instructions. Always use
2840 the same code for stores--don't special case proc64.
2842 * gencode.c (build_mips16_operands): Fix base PC value for PC
2844 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2846 * interp.c (simJALDELAYSLOT): Define.
2847 (JALDELAYSLOT): Define.
2848 (INDELAYSLOT, INJALDELAYSLOT): Define.
2849 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2851 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2853 * interp.c (sim_open): add flush_cache as a PMON routine
2854 (sim_monitor): handle flush_cache by ignoring it
2856 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2858 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2860 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2861 (BigEndianMem): Rename to ByteSwapMem and change sense.
2862 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2863 BigEndianMem references to !ByteSwapMem.
2864 (set_endianness): New function, with prototype.
2865 (sim_open): Call set_endianness.
2866 (sim_info): Use simBE instead of BigEndianMem.
2867 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2868 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2869 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2870 ifdefs, keeping the prototype declaration.
2871 (swap_word): Rewrite correctly.
2872 (ColdReset): Delete references to CONFIG. Delete endianness related
2873 code; moved to set_endianness.
2875 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2877 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2878 * interp.c (CHECKHILO): Define away.
2879 (simSIGINT): New macro.
2880 (membank_size): Increase from 1MB to 2MB.
2881 (control_c): New function.
2882 (sim_resume): Rename parameter signal to signal_number. Add local
2883 variable prev. Call signal before and after simulate.
2884 (sim_stop_reason): Add simSIGINT support.
2885 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2887 (sim_warning): Delete call to SignalException. Do call printf_filtered
2889 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2890 a call to sim_warning.
2892 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2894 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2895 16 bit instructions.
2897 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2899 Add support for mips16 (16 bit MIPS implementation):
2900 * gencode.c (inst_type): Add mips16 instruction encoding types.
2901 (GETDATASIZEINSN): Define.
2902 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2903 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2905 (MIPS16_DECODE): New table, for mips16 instructions.
2906 (bitmap_val): New static function.
2907 (struct mips16_op): Define.
2908 (mips16_op_table): New table, for mips16 operands.
2909 (build_mips16_operands): New static function.
2910 (process_instructions): If PC is odd, decode a mips16
2911 instruction. Break out instruction handling into new
2912 build_instruction function.
2913 (build_instruction): New static function, broken out of
2914 process_instructions. Check modifiers rather than flags for SHIFT
2915 bit count and m[ft]{hi,lo} direction.
2916 (usage): Pass program name to fprintf.
2917 (main): Remove unused variable this_option_optind. Change
2918 ``*loptarg++'' to ``loptarg++''.
2919 (my_strtoul): Parenthesize && within ||.
2920 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2921 (simulate): If PC is odd, fetch a 16 bit instruction, and
2922 increment PC by 2 rather than 4.
2923 * configure.in: Add case for mips16*-*-*.
2924 * configure: Rebuild.
2926 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2928 * interp.c: Allow -t to enable tracing in standalone simulator.
2929 Fix garbage output in trace file and error messages.
2931 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2933 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2934 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2935 * configure.in: Simplify using macros in ../common/aclocal.m4.
2936 * configure: Regenerated.
2937 * tconfig.in: New file.
2939 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2941 * interp.c: Fix bugs in 64-bit port.
2942 Use ansi function declarations for msvc compiler.
2943 Initialize and test file pointer in trace code.
2944 Prevent duplicate definition of LAST_EMED_REGNUM.
2946 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2948 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2950 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2952 * interp.c (SignalException): Check for explicit terminating
2954 * gencode.c: Pass instruction value through SignalException()
2955 calls for Trap, Breakpoint and Syscall.
2957 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2959 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2960 only used on those hosts that provide it.
2961 * configure.in: Add sqrt() to list of functions to be checked for.
2962 * config.in: Re-generated.
2963 * configure: Re-generated.
2965 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2967 * gencode.c (process_instructions): Call build_endian_shift when
2968 expanding STORE RIGHT, to fix swr.
2969 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2970 clear the high bits.
2971 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2972 Fix float to int conversions to produce signed values.
2974 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2976 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2977 (process_instructions): Correct handling of nor instruction.
2978 Correct shift count for 32 bit shift instructions. Correct sign
2979 extension for arithmetic shifts to not shift the number of bits in
2980 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2981 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2983 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2984 It's OK to have a mult follow a mult. What's not OK is to have a
2985 mult follow an mfhi.
2986 (Convert): Comment out incorrect rounding code.
2988 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2990 * interp.c (sim_monitor): Improved monitor printf
2991 simulation. Tidied up simulator warnings, and added "--log" option
2992 for directing warning message output.
2993 * gencode.c: Use sim_warning() rather than WARNING macro.
2995 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2997 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2998 getopt1.o, rather than on gencode.c. Link objects together.
2999 Don't link against -liberty.
3000 (gencode.o, getopt.o, getopt1.o): New targets.
3001 * gencode.c: Include <ctype.h> and "ansidecl.h".
3002 (AND): Undefine after including "ansidecl.h".
3003 (ULONG_MAX): Define if not defined.
3004 (OP_*): Don't define macros; now defined in opcode/mips.h.
3005 (main): Call my_strtoul rather than strtoul.
3006 (my_strtoul): New static function.
3008 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3010 * gencode.c (process_instructions): Generate word64 and uword64
3011 instead of `long long' and `unsigned long long' data types.
3012 * interp.c: #include sysdep.h to get signals, and define default
3014 * (Convert): Work around for Visual-C++ compiler bug with type
3016 * support.h: Make things compile under Visual-C++ by using
3017 __int64 instead of `long long'. Change many refs to long long
3018 into word64/uword64 typedefs.
3020 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3022 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3023 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3025 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3026 (AC_PROG_INSTALL): Added.
3027 (AC_PROG_CC): Moved to before configure.host call.
3028 * configure: Rebuilt.
3030 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3032 * configure.in: Define @SIMCONF@ depending on mips target.
3033 * configure: Rebuild.
3034 * Makefile.in (run): Add @SIMCONF@ to control simulator
3036 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3037 * interp.c: Remove some debugging, provide more detailed error
3038 messages, update memory accesses to use LOADDRMASK.
3040 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3042 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3043 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3045 * configure: Rebuild.
3046 * config.in: New file, generated by autoheader.
3047 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3048 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3049 HAVE_ANINT and HAVE_AINT, as appropriate.
3050 * Makefile.in (run): Use @LIBS@ rather than -lm.
3051 (interp.o): Depend upon config.h.
3052 (Makefile): Just rebuild Makefile.
3053 (clean): Remove stamp-h.
3054 (mostlyclean): Make the same as clean, not as distclean.
3055 (config.h, stamp-h): New targets.
3057 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3059 * interp.c (ColdReset): Fix boolean test. Make all simulator
3062 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3064 * interp.c (xfer_direct_word, xfer_direct_long,
3065 swap_direct_word, swap_direct_long, xfer_big_word,
3066 xfer_big_long, xfer_little_word, xfer_little_long,
3067 swap_word,swap_long): Added.
3068 * interp.c (ColdReset): Provide function indirection to
3069 host<->simulated_target transfer routines.
3070 * interp.c (sim_store_register, sim_fetch_register): Updated to
3071 make use of indirected transfer routines.
3073 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3075 * gencode.c (process_instructions): Ensure FP ABS instruction
3077 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3078 system call support.
3080 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3082 * interp.c (sim_do_command): Complain if callback structure not
3085 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3087 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3088 support for Sun hosts.
3089 * Makefile.in (gencode): Ensure the host compiler and libraries
3090 used for cross-hosted build.
3092 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3094 * interp.c, gencode.c: Some more (TODO) tidying.
3096 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3098 * gencode.c, interp.c: Replaced explicit long long references with
3099 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3100 * support.h (SET64LO, SET64HI): Macros added.
3102 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3104 * configure: Regenerate with autoconf 2.7.
3106 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3108 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3109 * support.h: Remove superfluous "1" from #if.
3110 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3112 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3114 * interp.c (StoreFPR): Control UndefinedResult() call on
3115 WARN_RESULT manifest.
3117 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3119 * gencode.c: Tidied instruction decoding, and added FP instruction
3122 * interp.c: Added dineroIII, and BSD profiling support. Also
3123 run-time FP handling.
3125 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3127 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3128 gencode.c, interp.c, support.h: created.