1 2002-06-18 Chris Demetriou <cgd@broadcom.com>
3 * mdmx.c (SD_): Delete.
4 (Unpredictable): Re-define, for now, to directly invoke
5 unpredictable_action().
6 (mdmx_acc_op): Fix error in .ob immediate handling.
8 2002-06-18 Andrew Cagney <cagney@redhat.com>
10 * interp.c (sim_firmware_command): Initialize `address'.
12 2002-06-16 Andrew Cagney <ac131313@redhat.com>
14 * configure: Regenerated to track ../common/aclocal.m4 changes.
16 2002-06-14 Chris Demetriou <cgd@broadcom.com>
17 Ed Satterthwaite <ehs@broadcom.com>
19 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
20 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
21 * mips.igen: Include mips3d.igen.
22 (mips3d): New model name for MIPS-3D ASE instructions.
23 (CVT.W.fmt): Don't use this instruction for word (source) format
25 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
26 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
27 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
28 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
29 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
30 (RSquareRoot1, RSquareRoot2): New macros.
31 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
32 (fp_rsqrt2): New functions.
33 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
34 * configure: Regenerate.
36 2002-06-13 Chris Demetriou <cgd@broadcom.com>
37 Ed Satterthwaite <ehs@broadcom.com>
39 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
40 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
41 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
42 (convert): Note that this function is not used for paired-single
44 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
45 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
46 (check_fmt_p): Enable paired-single support.
47 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
48 (PUU.PS): New instructions.
49 (CVT.S.fmt): Don't use this instruction for paired-single format
51 * sim-main.h (FP_formats): New value 'fmt_ps.'
52 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
53 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
55 2002-06-12 Chris Demetriou <cgd@broadcom.com>
57 * mips.igen: Fix formatting of function calls in
60 2002-06-12 Chris Demetriou <cgd@broadcom.com>
62 * mips.igen (MOVN, MOVZ): Trace result.
63 (TNEI): Print "tnei" as the opcode name in traces.
64 (CEIL.W): Add disassembly string for traces.
65 (RSQRT.fmt): Make location of disassembly string consistent
66 with other instructions.
68 2002-06-12 Chris Demetriou <cgd@broadcom.com>
70 * mips.igen (X): Delete unused function.
72 2002-06-08 Andrew Cagney <cagney@redhat.com>
74 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
76 2002-06-07 Chris Demetriou <cgd@broadcom.com>
77 Ed Satterthwaite <ehs@broadcom.com>
79 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
80 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
81 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
82 (fp_nmsub): New prototypes.
83 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
84 (NegMultiplySub): New defines.
85 * mips.igen (RSQRT.fmt): Use RSquareRoot().
86 (MADD.D, MADD.S): Replace with...
87 (MADD.fmt): New instruction.
88 (MSUB.D, MSUB.S): Replace with...
89 (MSUB.fmt): New instruction.
90 (NMADD.D, NMADD.S): Replace with...
91 (NMADD.fmt): New instruction.
92 (NMSUB.D, MSUB.S): Replace with...
93 (NMSUB.fmt): New instruction.
95 2002-06-07 Chris Demetriou <cgd@broadcom.com>
96 Ed Satterthwaite <ehs@broadcom.com>
98 * cp1.c: Fix more comment spelling and formatting.
99 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
100 (denorm_mode): New function.
101 (fpu_unary, fpu_binary): Round results after operation, collect
102 status from rounding operations, and update the FCSR.
103 (convert): Collect status from integer conversions and rounding
104 operations, and update the FCSR. Adjust NaN values that result
105 from conversions. Convert to use sim_io_eprintf rather than
106 fprintf, and remove some debugging code.
107 * cp1.h (fenr_FS): New define.
109 2002-06-07 Chris Demetriou <cgd@broadcom.com>
111 * cp1.c (convert): Remove unusable debugging code, and move MIPS
112 rounding mode to sim FP rounding mode flag conversion code into...
113 (rounding_mode): New function.
115 2002-06-07 Chris Demetriou <cgd@broadcom.com>
117 * cp1.c: Clean up formatting of a few comments.
118 (value_fpr): Reformat switch statement.
120 2002-06-06 Chris Demetriou <cgd@broadcom.com>
121 Ed Satterthwaite <ehs@broadcom.com>
124 * sim-main.h: Include cp1.h.
125 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
126 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
127 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
128 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
129 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
130 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
131 * cp1.c: Don't include sim-fpu.h; already included by
132 sim-main.h. Clean up formatting of some comments.
133 (NaN, Equal, Less): Remove.
134 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
135 (fp_cmp): New functions.
136 * mips.igen (do_c_cond_fmt): Remove.
137 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
138 Compare. Add result tracing.
139 (CxC1): Remove, replace with...
140 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
141 (DMxC1): Remove, replace with...
142 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
143 (MxC1): Remove, replace with...
144 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
146 2002-06-04 Chris Demetriou <cgd@broadcom.com>
148 * sim-main.h (FGRIDX): Remove, replace all uses with...
149 (FGR_BASE): New macro.
150 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
151 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
152 (NR_FGR, FGR): Likewise.
153 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
154 * mips.igen: Likewise.
156 2002-06-04 Chris Demetriou <cgd@broadcom.com>
158 * cp1.c: Add an FSF Copyright notice to this file.
160 2002-06-04 Chris Demetriou <cgd@broadcom.com>
161 Ed Satterthwaite <ehs@broadcom.com>
163 * cp1.c (Infinity): Remove.
164 * sim-main.h (Infinity): Likewise.
166 * cp1.c (fp_unary, fp_binary): New functions.
167 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
168 (fp_sqrt): New functions, implemented in terms of the above.
169 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
170 (Recip, SquareRoot): Remove (replaced by functions above).
171 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
172 (fp_recip, fp_sqrt): New prototypes.
173 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
174 (Recip, SquareRoot): Replace prototypes with #defines which
175 invoke the functions above.
177 2002-06-03 Chris Demetriou <cgd@broadcom.com>
179 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
180 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
181 file, remove PARAMS from prototypes.
182 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
183 simulator state arguments.
184 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
185 pass simulator state arguments.
186 * cp1.c (SD): Redefine as CPU_STATE(cpu).
187 (store_fpr, convert): Remove 'sd' argument.
188 (value_fpr): Likewise. Convert to use 'SD' instead.
190 2002-06-03 Chris Demetriou <cgd@broadcom.com>
192 * cp1.c (Min, Max): Remove #if 0'd functions.
193 * sim-main.h (Min, Max): Remove.
195 2002-06-03 Chris Demetriou <cgd@broadcom.com>
197 * cp1.c: fix formatting of switch case and default labels.
198 * interp.c: Likewise.
199 * sim-main.c: Likewise.
201 2002-06-03 Chris Demetriou <cgd@broadcom.com>
203 * cp1.c: Clean up comments which describe FP formats.
204 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
206 2002-06-03 Chris Demetriou <cgd@broadcom.com>
207 Ed Satterthwaite <ehs@broadcom.com>
209 * configure.in (mipsisa64sb1*-*-*): New target for supporting
210 Broadcom SiByte SB-1 processor configurations.
211 * configure: Regenerate.
212 * sb1.igen: New file.
213 * mips.igen: Include sb1.igen.
215 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
216 * mdmx.igen: Add "sb1" model to all appropriate functions and
218 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
219 (ob_func, ob_acc): Reference the above.
220 (qh_acc): Adjust to keep the same size as ob_acc.
221 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
222 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
224 2002-06-03 Chris Demetriou <cgd@broadcom.com>
226 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
228 2002-06-02 Chris Demetriou <cgd@broadcom.com>
229 Ed Satterthwaite <ehs@broadcom.com>
231 * mips.igen (mdmx): New (pseudo-)model.
232 * mdmx.c, mdmx.igen: New files.
233 * Makefile.in (SIM_OBJS): Add mdmx.o.
234 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
236 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
237 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
238 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
239 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
240 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
241 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
242 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
243 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
244 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
245 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
246 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
247 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
248 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
249 (qh_fmtsel): New macros.
250 (_sim_cpu): New member "acc".
251 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
252 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
254 2002-05-01 Chris Demetriou <cgd@broadcom.com>
256 * interp.c: Use 'deprecated' rather than 'depreciated.'
257 * sim-main.h: Likewise.
259 2002-05-01 Chris Demetriou <cgd@broadcom.com>
261 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
262 which wouldn't compile anyway.
263 * sim-main.h (unpredictable_action): New function prototype.
264 (Unpredictable): Define to call igen function unpredictable().
265 (NotWordValue): New macro to call igen function not_word_value().
266 (UndefinedResult): Remove.
267 * interp.c (undefined_result): Remove.
268 (unpredictable_action): New function.
269 * mips.igen (not_word_value, unpredictable): New functions.
270 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
271 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
272 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
273 NotWordValue() to check for unpredictable inputs, then
274 Unpredictable() to handle them.
276 2002-02-24 Chris Demetriou <cgd@broadcom.com>
278 * mips.igen: Fix formatting of calls to Unpredictable().
280 2002-04-20 Andrew Cagney <ac131313@redhat.com>
282 * interp.c (sim_open): Revert previous change.
284 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
286 * interp.c (sim_open): Disable chunk of code that wrote code in
287 vector table entries.
289 2002-03-19 Chris Demetriou <cgd@broadcom.com>
291 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
292 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
295 2002-03-19 Chris Demetriou <cgd@broadcom.com>
297 * cp1.c: Fix many formatting issues.
299 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
301 * cp1.c (fpu_format_name): New function to replace...
302 (DOFMT): This. Delete, and update all callers.
303 (fpu_rounding_mode_name): New function to replace...
304 (RMMODE): This. Delete, and update all callers.
306 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
308 * interp.c: Move FPU support routines from here to...
309 * cp1.c: Here. New file.
310 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
313 2002-03-12 Chris Demetriou <cgd@broadcom.com>
315 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
316 * mips.igen (mips32, mips64): New models, add to all instructions
317 and functions as appropriate.
318 (loadstore_ea, check_u64): New variant for model mips64.
319 (check_fmt_p): New variant for models mipsV and mips64, remove
320 mipsV model marking fro other variant.
323 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
324 for mips32 and mips64.
325 (DCLO, DCLZ): New instructions for mips64.
327 2002-03-07 Chris Demetriou <cgd@broadcom.com>
329 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
330 immediate or code as a hex value with the "%#lx" format.
331 (ANDI): Likewise, and fix printed instruction name.
333 2002-03-05 Chris Demetriou <cgd@broadcom.com>
335 * sim-main.h (UndefinedResult, Unpredictable): New macros
336 which currently do nothing.
338 2002-03-05 Chris Demetriou <cgd@broadcom.com>
340 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
341 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
342 (status_CU3): New definitions.
344 * sim-main.h (ExceptionCause): Add new values for MIPS32
345 and MIPS64: MDMX, MCheck, CacheErr. Update comments
346 for DebugBreakPoint and NMIReset to note their status in
348 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
349 (SignalExceptionCacheErr): New exception macros.
351 2002-03-05 Chris Demetriou <cgd@broadcom.com>
353 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
354 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
356 (SignalExceptionCoProcessorUnusable): Take as argument the
357 unusable coprocessor number.
359 2002-03-05 Chris Demetriou <cgd@broadcom.com>
361 * mips.igen: Fix formatting of all SignalException calls.
363 2002-03-05 Chris Demetriou <cgd@broadcom.com>
365 * sim-main.h (SIGNEXTEND): Remove.
367 2002-03-04 Chris Demetriou <cgd@broadcom.com>
369 * mips.igen: Remove gencode comment from top of file, fix
370 spelling in another comment.
372 2002-03-04 Chris Demetriou <cgd@broadcom.com>
374 * mips.igen (check_fmt, check_fmt_p): New functions to check
375 whether specific floating point formats are usable.
376 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
377 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
378 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
379 Use the new functions.
380 (do_c_cond_fmt): Remove format checks...
381 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
383 2002-03-03 Chris Demetriou <cgd@broadcom.com>
385 * mips.igen: Fix formatting of check_fpu calls.
387 2002-03-03 Chris Demetriou <cgd@broadcom.com>
389 * mips.igen (FLOOR.L.fmt): Store correct destination register.
391 2002-03-03 Chris Demetriou <cgd@broadcom.com>
393 * mips.igen: Remove whitespace at end of lines.
395 2002-03-02 Chris Demetriou <cgd@broadcom.com>
397 * mips.igen (loadstore_ea): New function to do effective
398 address calculations.
399 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
400 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
401 CACHE): Use loadstore_ea to do effective address computations.
403 2002-03-02 Chris Demetriou <cgd@broadcom.com>
405 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
406 * mips.igen (LL, CxC1, MxC1): Likewise.
408 2002-03-02 Chris Demetriou <cgd@broadcom.com>
410 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
411 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
412 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
413 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
414 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
415 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
416 Don't split opcode fields by hand, use the opcode field values
419 2002-03-01 Chris Demetriou <cgd@broadcom.com>
421 * mips.igen (do_divu): Fix spacing.
423 * mips.igen (do_dsllv): Move to be right before DSLLV,
424 to match the rest of the do_<shift> functions.
426 2002-03-01 Chris Demetriou <cgd@broadcom.com>
428 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
429 DSRL32, do_dsrlv): Trace inputs and results.
431 2002-03-01 Chris Demetriou <cgd@broadcom.com>
433 * mips.igen (CACHE): Provide instruction-printing string.
435 * interp.c (signal_exception): Comment tokens after #endif.
437 2002-02-28 Chris Demetriou <cgd@broadcom.com>
439 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
440 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
441 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
442 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
443 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
444 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
445 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
446 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
448 2002-02-28 Chris Demetriou <cgd@broadcom.com>
450 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
451 instruction-printing string.
452 (LWU): Use '64' as the filter flag.
454 2002-02-28 Chris Demetriou <cgd@broadcom.com>
456 * mips.igen (SDXC1): Fix instruction-printing string.
458 2002-02-28 Chris Demetriou <cgd@broadcom.com>
460 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
463 2002-02-27 Chris Demetriou <cgd@broadcom.com>
465 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
468 2002-02-27 Chris Demetriou <cgd@broadcom.com>
470 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
471 add a comma) so that it more closely match the MIPS ISA
472 documentation opcode partitioning.
473 (PREF): Put useful names on opcode fields, and include
474 instruction-printing string.
476 2002-02-27 Chris Demetriou <cgd@broadcom.com>
478 * mips.igen (check_u64): New function which in the future will
479 check whether 64-bit instructions are usable and signal an
480 exception if not. Currently a no-op.
481 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
482 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
483 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
484 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
486 * mips.igen (check_fpu): New function which in the future will
487 check whether FPU instructions are usable and signal an exception
488 if not. Currently a no-op.
489 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
490 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
491 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
492 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
493 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
494 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
495 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
496 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
498 2002-02-27 Chris Demetriou <cgd@broadcom.com>
500 * mips.igen (do_load_left, do_load_right): Move to be immediately
502 (do_store_left, do_store_right): Move to be immediately following
505 2002-02-27 Chris Demetriou <cgd@broadcom.com>
507 * mips.igen (mipsV): New model name. Also, add it to
508 all instructions and functions where it is appropriate.
510 2002-02-18 Chris Demetriou <cgd@broadcom.com>
512 * mips.igen: For all functions and instructions, list model
513 names that support that instruction one per line.
515 2002-02-11 Chris Demetriou <cgd@broadcom.com>
517 * mips.igen: Add some additional comments about supported
518 models, and about which instructions go where.
519 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
520 order as is used in the rest of the file.
522 2002-02-11 Chris Demetriou <cgd@broadcom.com>
524 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
525 indicating that ALU32_END or ALU64_END are there to check
527 (DADD): Likewise, but also remove previous comment about
530 2002-02-10 Chris Demetriou <cgd@broadcom.com>
532 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
533 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
534 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
535 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
536 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
537 fields (i.e., add and move commas) so that they more closely
538 match the MIPS ISA documentation opcode partitioning.
540 2002-02-10 Chris Demetriou <cgd@broadcom.com>
542 * mips.igen (ADDI): Print immediate value.
544 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
545 (SLL): Print "nop" specially, and don't run the code
546 that does the shift for the "nop" case.
548 2001-11-17 Fred Fish <fnf@redhat.com>
550 * sim-main.h (float_operation): Move enum declaration outside
551 of _sim_cpu struct declaration.
553 2001-04-12 Jim Blandy <jimb@redhat.com>
555 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
556 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
558 * sim-main.h (COCIDX): Remove definition; this isn't supported by
559 PENDING_FILL, and you can get the intended effect gracefully by
560 calling PENDING_SCHED directly.
562 2001-02-23 Ben Elliston <bje@redhat.com>
564 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
565 already defined elsewhere.
567 2001-02-19 Ben Elliston <bje@redhat.com>
569 * sim-main.h (sim_monitor): Return an int.
570 * interp.c (sim_monitor): Add return values.
571 (signal_exception): Handle error conditions from sim_monitor.
573 2001-02-08 Ben Elliston <bje@redhat.com>
575 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
576 (store_memory): Likewise, pass cia to sim_core_write*.
578 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
580 On advice from Chris G. Demetriou <cgd@sibyte.com>:
581 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
583 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
585 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
586 * Makefile.in: Don't delete *.igen when cleaning directory.
588 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
590 * m16.igen (break): Call SignalException not sim_engine_halt.
592 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
595 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
597 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
599 * mips.igen (MxC1, DMxC1): Fix printf formatting.
601 2000-05-24 Michael Hayes <mhayes@cygnus.com>
603 * mips.igen (do_dmultx): Fix typo.
605 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
607 * configure: Regenerated to track ../common/aclocal.m4 changes.
609 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
611 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
613 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
615 * sim-main.h (GPR_CLEAR): Define macro.
617 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
619 * interp.c (decode_coproc): Output long using %lx and not %s.
621 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
623 * interp.c (sim_open): Sort & extend dummy memory regions for
624 --board=jmr3904 for eCos.
626 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
628 * configure: Regenerated.
630 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
632 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
633 calls, conditional on the simulator being in verbose mode.
635 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
637 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
638 cache don't get ReservedInstruction traps.
640 1999-11-29 Mark Salter <msalter@cygnus.com>
642 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
643 to clear status bits in sdisr register. This is how the hardware works.
645 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
646 being used by cygmon.
648 1999-11-11 Andrew Haley <aph@cygnus.com>
650 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
653 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
655 * mips.igen (MULT): Correct previous mis-applied patch.
657 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
659 * mips.igen (delayslot32): Handle sequence like
660 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
661 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
662 (MULT): Actually pass the third register...
664 1999-09-03 Mark Salter <msalter@cygnus.com>
666 * interp.c (sim_open): Added more memory aliases for additional
667 hardware being touched by cygmon on jmr3904 board.
669 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
671 * configure: Regenerated to track ../common/aclocal.m4 changes.
673 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
675 * interp.c (sim_store_register): Handle case where client - GDB -
676 specifies that a 4 byte register is 8 bytes in size.
677 (sim_fetch_register): Ditto.
679 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
681 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
682 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
683 (idt_monitor_base): Base address for IDT monitor traps.
684 (pmon_monitor_base): Ditto for PMON.
685 (lsipmon_monitor_base): Ditto for LSI PMON.
686 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
687 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
688 (sim_firmware_command): New function.
689 (mips_option_handler): Call it for OPTION_FIRMWARE.
690 (sim_open): Allocate memory for idt_monitor region. If "--board"
691 option was given, add no monitor by default. Add BREAK hooks only if
692 monitors are also there.
694 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
696 * interp.c (sim_monitor): Flush output before reading input.
698 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
700 * tconfig.in (SIM_HANDLES_LMA): Always define.
702 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
704 From Mark Salter <msalter@cygnus.com>:
705 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
706 (sim_open): Add setup for BSP board.
708 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
710 * mips.igen (MULT, MULTU): Add syntax for two operand version.
711 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
712 them as unimplemented.
714 1999-05-08 Felix Lee <flee@cygnus.com>
716 * configure: Regenerated to track ../common/aclocal.m4 changes.
718 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
720 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
722 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
724 * configure.in: Any mips64vr5*-*-* target should have
725 -DTARGET_ENABLE_FR=1.
726 (default_endian): Any mips64vr*el-*-* target should default to
728 * configure: Re-generate.
730 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
732 * mips.igen (ldl): Extend from _16_, not 32.
734 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
736 * interp.c (sim_store_register): Force registers written to by GDB
737 into an un-interpreted state.
739 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
741 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
742 CPU, start periodic background I/O polls.
743 (tx3904sio_poll): New function: periodic I/O poller.
745 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
747 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
749 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
751 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
754 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
756 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
757 (load_word): Call SIM_CORE_SIGNAL hook on error.
758 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
759 starting. For exception dispatching, pass PC instead of NULL_CIA.
760 (decode_coproc): Use COP0_BADVADDR to store faulting address.
761 * sim-main.h (COP0_BADVADDR): Define.
762 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
763 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
764 (_sim_cpu): Add exc_* fields to store register value snapshots.
765 * mips.igen (*): Replace memory-related SignalException* calls
766 with references to SIM_CORE_SIGNAL hook.
768 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
770 * sim-main.c (*): Minor warning cleanups.
772 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
774 * m16.igen (DADDIU5): Correct type-o.
776 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
778 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
781 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
783 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
785 (interp.o): Add dependency on itable.h
786 (oengine.c, gencode): Delete remaining references.
787 (BUILT_SRC_FROM_GEN): Clean up.
789 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
792 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
793 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
795 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
796 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
797 Drop the "64" qualifier to get the HACK generator working.
798 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
799 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
800 qualifier to get the hack generator working.
801 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
803 (DSLLV): Use do_dsllv.
806 (DSRLV): Use do_dsrlv.
807 (BC1): Move *vr4100 to get the HACK generator working.
808 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
809 get the HACK generator working.
810 (MACC) Rename to get the HACK generator working.
811 (DMACC,MACCS,DMACCS): Add the 64.
813 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
815 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
816 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
818 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
820 * mips/interp.c (DEBUG): Cleanups.
822 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
824 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
825 (tx3904sio_tickle): fflush after a stdout character output.
827 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
829 * interp.c (sim_close): Uninstall modules.
831 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
833 * sim-main.h, interp.c (sim_monitor): Change to global
836 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
838 * configure.in (vr4100): Only include vr4100 instructions in
840 * configure: Re-generate.
841 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
843 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
845 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
846 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
849 * configure.in (sim_default_gen, sim_use_gen): Replace with
851 (--enable-sim-igen): Delete config option. Always using IGEN.
852 * configure: Re-generate.
854 * Makefile.in (gencode): Kill, kill, kill.
857 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
859 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
860 bit mips16 igen simulator.
861 * configure: Re-generate.
863 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
864 as part of vr4100 ISA.
865 * vr.igen: Mark all instructions as 64 bit only.
867 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
869 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
872 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
874 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
875 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
876 * configure: Re-generate.
878 * m16.igen (BREAK): Define breakpoint instruction.
879 (JALX32): Mark instruction as mips16 and not r3900.
880 * mips.igen (C.cond.fmt): Fix typo in instruction format.
882 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
884 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
886 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
887 insn as a debug breakpoint.
889 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
891 (PENDING_SCHED): Clean up trace statement.
892 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
893 (PENDING_FILL): Delay write by only one cycle.
894 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
896 * sim-main.c (pending_tick): Clean up trace statements. Add trace
898 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
900 (pending_tick): Move incrementing of index to FOR statement.
901 (pending_tick): Only update PENDING_OUT after a write has occured.
903 * configure.in: Add explicit mips-lsi-* target. Use gencode to
905 * configure: Re-generate.
907 * interp.c (sim_engine_run OLD): Delete explicit call to
908 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
910 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
912 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
913 interrupt level number to match changed SignalExceptionInterrupt
916 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
918 * interp.c: #include "itable.h" if WITH_IGEN.
919 (get_insn_name): New function.
920 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
921 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
923 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
925 * configure: Rebuilt to inhale new common/aclocal.m4.
927 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
929 * dv-tx3904sio.c: Include sim-assert.h.
931 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
933 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
934 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
935 Reorganize target-specific sim-hardware checks.
936 * configure: rebuilt.
937 * interp.c (sim_open): For tx39 target boards, set
938 OPERATING_ENVIRONMENT, add tx3904sio devices.
939 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
940 ROM executables. Install dv-sockser into sim-modules list.
942 * dv-tx3904irc.c: Compiler warning clean-up.
943 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
944 frequent hw-trace messages.
946 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
948 * vr.igen (MulAcc): Identify as a vr4100 specific function.
950 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
952 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
955 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
956 * mips.igen: Define vr4100 model. Include vr.igen.
957 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
959 * mips.igen (check_mf_hilo): Correct check.
961 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
963 * sim-main.h (interrupt_event): Add prototype.
965 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
966 register_ptr, register_value.
967 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
969 * sim-main.h (tracefh): Make extern.
971 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
973 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
974 Reduce unnecessarily high timer event frequency.
975 * dv-tx3904cpu.c: Ditto for interrupt event.
977 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
979 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
981 (interrupt_event): Made non-static.
983 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
984 interchange of configuration values for external vs. internal
987 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
989 * mips.igen (BREAK): Moved code to here for
990 simulator-reserved break instructions.
991 * gencode.c (build_instruction): Ditto.
992 * interp.c (signal_exception): Code moved from here. Non-
993 reserved instructions now use exception vector, rather
995 * sim-main.h: Moved magic constants to here.
997 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
999 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1000 register upon non-zero interrupt event level, clear upon zero
1002 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1003 by passing zero event value.
1004 (*_io_{read,write}_buffer): Endianness fixes.
1005 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1006 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1008 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1009 serial I/O and timer module at base address 0xFFFF0000.
1011 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1013 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1016 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1018 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1020 * configure: Update.
1022 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1024 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1025 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1026 * configure.in: Include tx3904tmr in hw_device list.
1027 * configure: Rebuilt.
1028 * interp.c (sim_open): Instantiate three timer instances.
1029 Fix address typo of tx3904irc instance.
1031 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1033 * interp.c (signal_exception): SystemCall exception now uses
1034 the exception vector.
1036 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1038 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1041 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1043 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1045 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1047 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1049 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1050 sim-main.h. Declare a struct hw_descriptor instead of struct
1051 hw_device_descriptor.
1053 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1055 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1056 right bits and then re-align left hand bytes to correct byte
1057 lanes. Fix incorrect computation in do_store_left when loading
1058 bytes from second word.
1060 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1062 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1063 * interp.c (sim_open): Only create a device tree when HW is
1066 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1067 * interp.c (signal_exception): Ditto.
1069 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1071 * gencode.c: Mark BEGEZALL as LIKELY.
1073 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1075 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1076 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1078 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1080 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1081 modules. Recognize TX39 target with "mips*tx39" pattern.
1082 * configure: Rebuilt.
1083 * sim-main.h (*): Added many macros defining bits in
1084 TX39 control registers.
1085 (SignalInterrupt): Send actual PC instead of NULL.
1086 (SignalNMIReset): New exception type.
1087 * interp.c (board): New variable for future use to identify
1088 a particular board being simulated.
1089 (mips_option_handler,mips_options): Added "--board" option.
1090 (interrupt_event): Send actual PC.
1091 (sim_open): Make memory layout conditional on board setting.
1092 (signal_exception): Initial implementation of hardware interrupt
1093 handling. Accept another break instruction variant for simulator
1095 (decode_coproc): Implement RFE instruction for TX39.
1096 (mips.igen): Decode RFE instruction as such.
1097 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1098 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1099 bbegin to implement memory map.
1100 * dv-tx3904cpu.c: New file.
1101 * dv-tx3904irc.c: New file.
1103 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1105 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1107 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1109 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1110 with calls to check_div_hilo.
1112 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1114 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1115 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1116 Add special r3900 version of do_mult_hilo.
1117 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1118 with calls to check_mult_hilo.
1119 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1120 with calls to check_div_hilo.
1122 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1124 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1125 Document a replacement.
1127 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1129 * interp.c (sim_monitor): Make mon_printf work.
1131 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1133 * sim-main.h (INSN_NAME): New arg `cpu'.
1135 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1137 * configure: Regenerated to track ../common/aclocal.m4 changes.
1139 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1141 * configure: Regenerated to track ../common/aclocal.m4 changes.
1144 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1146 * acconfig.h: New file.
1147 * configure.in: Reverted change of Apr 24; use sinclude again.
1149 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1151 * configure: Regenerated to track ../common/aclocal.m4 changes.
1154 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1156 * configure.in: Don't call sinclude.
1158 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1160 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1162 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1164 * mips.igen (ERET): Implement.
1166 * interp.c (decode_coproc): Return sign-extended EPC.
1168 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1170 * interp.c (signal_exception): Do not ignore Trap.
1171 (signal_exception): On TRAP, restart at exception address.
1172 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1173 (signal_exception): Update.
1174 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1175 so that TRAP instructions are caught.
1177 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1179 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1180 contains HI/LO access history.
1181 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1182 (HIACCESS, LOACCESS): Delete, replace with
1183 (HIHISTORY, LOHISTORY): New macros.
1184 (CHECKHILO): Delete all, moved to mips.igen
1186 * gencode.c (build_instruction): Do not generate checks for
1187 correct HI/LO register usage.
1189 * interp.c (old_engine_run): Delete checks for correct HI/LO
1192 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1193 check_mf_cycles): New functions.
1194 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1195 do_divu, domultx, do_mult, do_multu): Use.
1197 * tx.igen ("madd", "maddu"): Use.
1199 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1201 * mips.igen (DSRAV): Use function do_dsrav.
1202 (SRAV): Use new function do_srav.
1204 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1205 (B): Sign extend 11 bit immediate.
1206 (EXT-B*): Shift 16 bit immediate left by 1.
1207 (ADDIU*): Don't sign extend immediate value.
1209 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1211 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1213 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1216 * mips.igen (delayslot32, nullify_next_insn): New functions.
1217 (m16.igen): Always include.
1218 (do_*): Add more tracing.
1220 * m16.igen (delayslot16): Add NIA argument, could be called by a
1221 32 bit MIPS16 instruction.
1223 * interp.c (ifetch16): Move function from here.
1224 * sim-main.c (ifetch16): To here.
1226 * sim-main.c (ifetch16, ifetch32): Update to match current
1227 implementations of LH, LW.
1228 (signal_exception): Don't print out incorrect hex value of illegal
1231 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1233 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1236 * m16.igen: Implement MIPS16 instructions.
1238 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1239 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1240 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1241 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1242 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1243 bodies of corresponding code from 32 bit insn to these. Also used
1244 by MIPS16 versions of functions.
1246 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1247 (IMEM16): Drop NR argument from macro.
1249 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1251 * Makefile.in (SIM_OBJS): Add sim-main.o.
1253 * sim-main.h (address_translation, load_memory, store_memory,
1254 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1256 (pr_addr, pr_uword64): Declare.
1257 (sim-main.c): Include when H_REVEALS_MODULE_P.
1259 * interp.c (address_translation, load_memory, store_memory,
1260 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1262 * sim-main.c: To here. Fix compilation problems.
1264 * configure.in: Enable inlining.
1265 * configure: Re-config.
1267 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1269 * configure: Regenerated to track ../common/aclocal.m4 changes.
1271 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1273 * mips.igen: Include tx.igen.
1274 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1275 * tx.igen: New file, contains MADD and MADDU.
1277 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1278 the hardwired constant `7'.
1279 (store_memory): Ditto.
1280 (LOADDRMASK): Move definition to sim-main.h.
1282 mips.igen (MTC0): Enable for r3900.
1285 mips.igen (do_load_byte): Delete.
1286 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1287 do_store_right): New functions.
1288 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1290 configure.in: Let the tx39 use igen again.
1293 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1295 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1296 not an address sized quantity. Return zero for cache sizes.
1298 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1300 * mips.igen (r3900): r3900 does not support 64 bit integer
1303 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1305 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1307 * configure : Rebuild.
1309 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1311 * configure: Regenerated to track ../common/aclocal.m4 changes.
1313 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1315 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1317 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1319 * configure: Regenerated to track ../common/aclocal.m4 changes.
1320 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1322 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1324 * configure: Regenerated to track ../common/aclocal.m4 changes.
1326 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1328 * interp.c (Max, Min): Comment out functions. Not yet used.
1330 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1332 * configure: Regenerated to track ../common/aclocal.m4 changes.
1334 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1336 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1337 configurable settings for stand-alone simulator.
1339 * configure.in: Added X11 search, just in case.
1341 * configure: Regenerated.
1343 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1345 * interp.c (sim_write, sim_read, load_memory, store_memory):
1346 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1348 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1350 * sim-main.h (GETFCC): Return an unsigned value.
1352 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1354 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1355 (DADD): Result destination is RD not RT.
1357 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1359 * sim-main.h (HIACCESS, LOACCESS): Always define.
1361 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1363 * interp.c (sim_info): Delete.
1365 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1367 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1368 (mips_option_handler): New argument `cpu'.
1369 (sim_open): Update call to sim_add_option_table.
1371 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1373 * mips.igen (CxC1): Add tracing.
1375 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1377 * sim-main.h (Max, Min): Declare.
1379 * interp.c (Max, Min): New functions.
1381 * mips.igen (BC1): Add tracing.
1383 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1385 * interp.c Added memory map for stack in vr4100
1387 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1389 * interp.c (load_memory): Add missing "break"'s.
1391 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1393 * interp.c (sim_store_register, sim_fetch_register): Pass in
1394 length parameter. Return -1.
1396 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1398 * interp.c: Added hardware init hook, fixed warnings.
1400 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1402 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1404 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1406 * interp.c (ifetch16): New function.
1408 * sim-main.h (IMEM32): Rename IMEM.
1409 (IMEM16_IMMED): Define.
1411 (DELAY_SLOT): Update.
1413 * m16run.c (sim_engine_run): New file.
1415 * m16.igen: All instructions except LB.
1416 (LB): Call do_load_byte.
1417 * mips.igen (do_load_byte): New function.
1418 (LB): Call do_load_byte.
1420 * mips.igen: Move spec for insn bit size and high bit from here.
1421 * Makefile.in (tmp-igen, tmp-m16): To here.
1423 * m16.dc: New file, decode mips16 instructions.
1425 * Makefile.in (SIM_NO_ALL): Define.
1426 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1428 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1430 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1431 point unit to 32 bit registers.
1432 * configure: Re-generate.
1434 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1436 * configure.in (sim_use_gen): Make IGEN the default simulator
1437 generator for generic 32 and 64 bit mips targets.
1438 * configure: Re-generate.
1440 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1442 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1445 * interp.c (sim_fetch_register, sim_store_register): Read/write
1446 FGR from correct location.
1447 (sim_open): Set size of FGR's according to
1448 WITH_TARGET_FLOATING_POINT_BITSIZE.
1450 * sim-main.h (FGR): Store floating point registers in a separate
1453 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1455 * configure: Regenerated to track ../common/aclocal.m4 changes.
1457 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1459 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1461 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1463 * interp.c (pending_tick): New function. Deliver pending writes.
1465 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1466 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1467 it can handle mixed sized quantites and single bits.
1469 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1471 * interp.c (oengine.h): Do not include when building with IGEN.
1472 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1473 (sim_info): Ditto for PROCESSOR_64BIT.
1474 (sim_monitor): Replace ut_reg with unsigned_word.
1475 (*): Ditto for t_reg.
1476 (LOADDRMASK): Define.
1477 (sim_open): Remove defunct check that host FP is IEEE compliant,
1478 using software to emulate floating point.
1479 (value_fpr, ...): Always compile, was conditional on HASFPU.
1481 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1483 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1486 * interp.c (SD, CPU): Define.
1487 (mips_option_handler): Set flags in each CPU.
1488 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1489 (sim_close): Do not clear STATE, deleted anyway.
1490 (sim_write, sim_read): Assume CPU zero's vm should be used for
1492 (sim_create_inferior): Set the PC for all processors.
1493 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1495 (mips16_entry): Pass correct nr of args to store_word, load_word.
1496 (ColdReset): Cold reset all cpu's.
1497 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1498 (sim_monitor, load_memory, store_memory, signal_exception): Use
1499 `CPU' instead of STATE_CPU.
1502 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1505 * sim-main.h (signal_exception): Add sim_cpu arg.
1506 (SignalException*): Pass both SD and CPU to signal_exception.
1507 * interp.c (signal_exception): Update.
1509 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1511 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1512 address_translation): Ditto
1513 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1515 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1517 * configure: Regenerated to track ../common/aclocal.m4 changes.
1519 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1521 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1523 * mips.igen (model): Map processor names onto BFD name.
1525 * sim-main.h (CPU_CIA): Delete.
1526 (SET_CIA, GET_CIA): Define
1528 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1530 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1533 * configure.in (default_endian): Configure a big-endian simulator
1535 * configure: Re-generate.
1537 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1539 * configure: Regenerated to track ../common/aclocal.m4 changes.
1541 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1543 * interp.c (sim_monitor): Handle Densan monitor outbyte
1544 and inbyte functions.
1546 1997-12-29 Felix Lee <flee@cygnus.com>
1548 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1550 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1552 * Makefile.in (tmp-igen): Arrange for $zero to always be
1553 reset to zero after every instruction.
1555 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1557 * configure: Regenerated to track ../common/aclocal.m4 changes.
1560 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1562 * mips.igen (MSUB): Fix to work like MADD.
1563 * gencode.c (MSUB): Similarly.
1565 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1567 * configure: Regenerated to track ../common/aclocal.m4 changes.
1569 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1571 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1573 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1575 * sim-main.h (sim-fpu.h): Include.
1577 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1578 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1579 using host independant sim_fpu module.
1581 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1583 * interp.c (signal_exception): Report internal errors with SIGABRT
1586 * sim-main.h (C0_CONFIG): New register.
1587 (signal.h): No longer include.
1589 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1591 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1593 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1595 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1597 * mips.igen: Tag vr5000 instructions.
1598 (ANDI): Was missing mipsIV model, fix assembler syntax.
1599 (do_c_cond_fmt): New function.
1600 (C.cond.fmt): Handle mips I-III which do not support CC field
1602 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1603 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1605 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1606 vr5000 which saves LO in a GPR separatly.
1608 * configure.in (enable-sim-igen): For vr5000, select vr5000
1609 specific instructions.
1610 * configure: Re-generate.
1612 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1616 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1617 fmt_uninterpreted_64 bit cases to switch. Convert to
1620 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1622 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1623 as specified in IV3.2 spec.
1624 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1626 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1628 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1629 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1630 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1631 PENDING_FILL versions of instructions. Simplify.
1633 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1635 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1637 (MTHI, MFHI): Disable code checking HI-LO.
1639 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1641 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1643 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1645 * gencode.c (build_mips16_operands): Replace IPC with cia.
1647 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1648 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1650 (UndefinedResult): Replace function with macro/function
1652 (sim_engine_run): Don't save PC in IPC.
1654 * sim-main.h (IPC): Delete.
1657 * interp.c (signal_exception, store_word, load_word,
1658 address_translation, load_memory, store_memory, cache_op,
1659 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1660 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1661 current instruction address - cia - argument.
1662 (sim_read, sim_write): Call address_translation directly.
1663 (sim_engine_run): Rename variable vaddr to cia.
1664 (signal_exception): Pass cia to sim_monitor
1666 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1667 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1668 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1670 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1671 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1674 * interp.c (signal_exception): Pass restart address to
1677 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1678 idecode.o): Add dependency.
1680 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1682 (DELAY_SLOT): Update NIA not PC with branch address.
1683 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1685 * mips.igen: Use CIA not PC in branch calculations.
1686 (illegal): Call SignalException.
1687 (BEQ, ADDIU): Fix assembler.
1689 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1691 * m16.igen (JALX): Was missing.
1693 * configure.in (enable-sim-igen): New configuration option.
1694 * configure: Re-generate.
1696 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1698 * interp.c (load_memory, store_memory): Delete parameter RAW.
1699 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1700 bypassing {load,store}_memory.
1702 * sim-main.h (ByteSwapMem): Delete definition.
1704 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1706 * interp.c (sim_do_command, sim_commands): Delete mips specific
1707 commands. Handled by module sim-options.
1709 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1710 (WITH_MODULO_MEMORY): Define.
1712 * interp.c (sim_info): Delete code printing memory size.
1714 * interp.c (mips_size): Nee sim_size, delete function.
1716 (monitor, monitor_base, monitor_size): Delete global variables.
1717 (sim_open, sim_close): Delete code creating monitor and other
1718 memory regions. Use sim-memopts module, via sim_do_commandf, to
1719 manage memory regions.
1720 (load_memory, store_memory): Use sim-core for memory model.
1722 * interp.c (address_translation): Delete all memory map code
1723 except line forcing 32 bit addresses.
1725 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1727 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1730 * interp.c (logfh, logfile): Delete globals.
1731 (sim_open, sim_close): Delete code opening & closing log file.
1732 (mips_option_handler): Delete -l and -n options.
1733 (OPTION mips_options): Ditto.
1735 * interp.c (OPTION mips_options): Rename option trace to dinero.
1736 (mips_option_handler): Update.
1738 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740 * interp.c (fetch_str): New function.
1741 (sim_monitor): Rewrite using sim_read & sim_write.
1742 (sim_open): Check magic number.
1743 (sim_open): Write monitor vectors into memory using sim_write.
1744 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1745 (sim_read, sim_write): Simplify - transfer data one byte at a
1747 (load_memory, store_memory): Clarify meaning of parameter RAW.
1749 * sim-main.h (isHOST): Defete definition.
1750 (isTARGET): Mark as depreciated.
1751 (address_translation): Delete parameter HOST.
1753 * interp.c (address_translation): Delete parameter HOST.
1755 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1759 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1760 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1762 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1764 * mips.igen: Add model filter field to records.
1766 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1768 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1770 interp.c (sim_engine_run): Do not compile function sim_engine_run
1771 when WITH_IGEN == 1.
1773 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1774 target architecture.
1776 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1777 igen. Replace with configuration variables sim_igen_flags /
1780 * m16.igen: New file. Copy mips16 insns here.
1781 * mips.igen: From here.
1783 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1785 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1787 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1789 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1791 * gencode.c (build_instruction): Follow sim_write's lead in using
1792 BigEndianMem instead of !ByteSwapMem.
1794 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1796 * configure.in (sim_gen): Dependent on target, select type of
1797 generator. Always select old style generator.
1799 configure: Re-generate.
1801 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1803 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1804 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1805 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1806 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1807 SIM_@sim_gen@_*, set by autoconf.
1809 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1811 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1813 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1814 CURRENT_FLOATING_POINT instead.
1816 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1817 (address_translation): Raise exception InstructionFetch when
1818 translation fails and isINSTRUCTION.
1820 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1821 sim_engine_run): Change type of of vaddr and paddr to
1823 (address_translation, prefetch, load_memory, store_memory,
1824 cache_op): Change type of vAddr and pAddr to address_word.
1826 * gencode.c (build_instruction): Change type of vaddr and paddr to
1829 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1831 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1832 macro to obtain result of ALU op.
1834 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1836 * interp.c (sim_info): Call profile_print.
1838 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1842 * sim-main.h (WITH_PROFILE): Do not define, defined in
1843 common/sim-config.h. Use sim-profile module.
1844 (simPROFILE): Delete defintion.
1846 * interp.c (PROFILE): Delete definition.
1847 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1848 (sim_close): Delete code writing profile histogram.
1849 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1851 (sim_engine_run): Delete code profiling the PC.
1853 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1855 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1857 * interp.c (sim_monitor): Make register pointers of type
1860 * sim-main.h: Make registers of type unsigned_word not
1863 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1865 * interp.c (sync_operation): Rename from SyncOperation, make
1866 global, add SD argument.
1867 (prefetch): Rename from Prefetch, make global, add SD argument.
1868 (decode_coproc): Make global.
1870 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1872 * gencode.c (build_instruction): Generate DecodeCoproc not
1873 decode_coproc calls.
1875 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1876 (SizeFGR): Move to sim-main.h
1877 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1878 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1879 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1881 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1882 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1883 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1884 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1885 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1886 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1888 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1890 (sim-alu.h): Include.
1891 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1892 (sim_cia): Typedef to instruction_address.
1894 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1896 * Makefile.in (interp.o): Rename generated file engine.c to
1901 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1903 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1905 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1907 * gencode.c (build_instruction): For "FPSQRT", output correct
1908 number of arguments to Recip.
1910 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1912 * Makefile.in (interp.o): Depends on sim-main.h
1914 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1916 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1917 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1918 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1919 STATE, DSSTATE): Define
1920 (GPR, FGRIDX, ..): Define.
1922 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1923 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1924 (GPR, FGRIDX, ...): Delete macros.
1926 * interp.c: Update names to match defines from sim-main.h
1928 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1930 * interp.c (sim_monitor): Add SD argument.
1931 (sim_warning): Delete. Replace calls with calls to
1933 (sim_error): Delete. Replace calls with sim_io_error.
1934 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1935 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1936 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1938 (mips_size): Rename from sim_size. Add SD argument.
1940 * interp.c (simulator): Delete global variable.
1941 (callback): Delete global variable.
1942 (mips_option_handler, sim_open, sim_write, sim_read,
1943 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1944 sim_size,sim_monitor): Use sim_io_* not callback->*.
1945 (sim_open): ZALLOC simulator struct.
1946 (PROFILE): Do not define.
1948 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1950 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1951 support.h with corresponding code.
1953 * sim-main.h (word64, uword64), support.h: Move definition to
1955 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1958 * Makefile.in: Update dependencies
1959 * interp.c: Do not include.
1961 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1963 * interp.c (address_translation, load_memory, store_memory,
1964 cache_op): Rename to from AddressTranslation et.al., make global,
1967 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1970 * interp.c (SignalException): Rename to signal_exception, make
1973 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1975 * sim-main.h (SignalException, SignalExceptionInterrupt,
1976 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1977 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1978 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1981 * interp.c, support.h: Use.
1983 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1985 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1986 to value_fpr / store_fpr. Add SD argument.
1987 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1988 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1990 * sim-main.h (ValueFPR, StoreFPR): Define.
1992 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1994 * interp.c (sim_engine_run): Check consistency between configure
1995 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1998 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1999 (mips_fpu): Configure WITH_FLOATING_POINT.
2000 (mips_endian): Configure WITH_TARGET_ENDIAN.
2001 * configure: Update.
2003 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2005 * configure: Regenerated to track ../common/aclocal.m4 changes.
2007 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2009 * configure: Regenerated.
2011 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2013 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2015 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2017 * gencode.c (print_igen_insn_models): Assume certain architectures
2018 include all mips* instructions.
2019 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2022 * Makefile.in (tmp.igen): Add target. Generate igen input from
2025 * gencode.c (FEATURE_IGEN): Define.
2026 (main): Add --igen option. Generate output in igen format.
2027 (process_instructions): Format output according to igen option.
2028 (print_igen_insn_format): New function.
2029 (print_igen_insn_models): New function.
2030 (process_instructions): Only issue warnings and ignore
2031 instructions when no FEATURE_IGEN.
2033 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2035 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2038 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2040 * configure: Regenerated to track ../common/aclocal.m4 changes.
2042 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2044 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2045 SIM_RESERVED_BITS): Delete, moved to common.
2046 (SIM_EXTRA_CFLAGS): Update.
2048 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2050 * configure.in: Configure non-strict memory alignment.
2051 * configure: Regenerated to track ../common/aclocal.m4 changes.
2053 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2055 * configure: Regenerated to track ../common/aclocal.m4 changes.
2057 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2059 * gencode.c (SDBBP,DERET): Added (3900) insns.
2060 (RFE): Turn on for 3900.
2061 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2062 (dsstate): Made global.
2063 (SUBTARGET_R3900): Added.
2064 (CANCELDELAYSLOT): New.
2065 (SignalException): Ignore SystemCall rather than ignore and
2066 terminate. Add DebugBreakPoint handling.
2067 (decode_coproc): New insns RFE, DERET; and new registers Debug
2068 and DEPC protected by SUBTARGET_R3900.
2069 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2071 * Makefile.in,configure.in: Add mips subtarget option.
2072 * configure: Update.
2074 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2076 * gencode.c: Add r3900 (tx39).
2079 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2081 * gencode.c (build_instruction): Don't need to subtract 4 for
2084 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2086 * interp.c: Correct some HASFPU problems.
2088 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2090 * configure: Regenerated to track ../common/aclocal.m4 changes.
2092 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2094 * interp.c (mips_options): Fix samples option short form, should
2097 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2099 * interp.c (sim_info): Enable info code. Was just returning.
2101 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2103 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2106 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2108 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2110 (build_instruction): Ditto for LL.
2112 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2114 * configure: Regenerated to track ../common/aclocal.m4 changes.
2116 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2118 * configure: Regenerated to track ../common/aclocal.m4 changes.
2121 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2123 * interp.c (sim_open): Add call to sim_analyze_program, update
2126 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2128 * interp.c (sim_kill): Delete.
2129 (sim_create_inferior): Add ABFD argument. Set PC from same.
2130 (sim_load): Move code initializing trap handlers from here.
2131 (sim_open): To here.
2132 (sim_load): Delete, use sim-hload.c.
2134 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2136 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2138 * configure: Regenerated to track ../common/aclocal.m4 changes.
2141 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2143 * interp.c (sim_open): Add ABFD argument.
2144 (sim_load): Move call to sim_config from here.
2145 (sim_open): To here. Check return status.
2147 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2149 * gencode.c (build_instruction): Two arg MADD should
2150 not assign result to $0.
2152 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2154 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2155 * sim/mips/configure.in: Regenerate.
2157 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2159 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2160 signed8, unsigned8 et.al. types.
2162 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2163 hosts when selecting subreg.
2165 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2167 * interp.c (sim_engine_run): Reset the ZERO register to zero
2168 regardless of FEATURE_WARN_ZERO.
2169 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2171 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2173 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2174 (SignalException): For BreakPoints ignore any mode bits and just
2176 (SignalException): Always set the CAUSE register.
2178 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2181 exception has been taken.
2183 * interp.c: Implement the ERET and mt/f sr instructions.
2185 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2187 * interp.c (SignalException): Don't bother restarting an
2190 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2192 * interp.c (SignalException): Really take an interrupt.
2193 (interrupt_event): Only deliver interrupts when enabled.
2195 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2197 * interp.c (sim_info): Only print info when verbose.
2198 (sim_info) Use sim_io_printf for output.
2200 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2202 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2205 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2207 * interp.c (sim_do_command): Check for common commands if a
2208 simulator specific command fails.
2210 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2212 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2213 and simBE when DEBUG is defined.
2215 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2217 * interp.c (interrupt_event): New function. Pass exception event
2218 onto exception handler.
2220 * configure.in: Check for stdlib.h.
2221 * configure: Regenerate.
2223 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2224 variable declaration.
2225 (build_instruction): Initialize memval1.
2226 (build_instruction): Add UNUSED attribute to byte, bigend,
2228 (build_operands): Ditto.
2230 * interp.c: Fix GCC warnings.
2231 (sim_get_quit_code): Delete.
2233 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2234 * Makefile.in: Ditto.
2235 * configure: Re-generate.
2237 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2239 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2241 * interp.c (mips_option_handler): New function parse argumes using
2243 (myname): Replace with STATE_MY_NAME.
2244 (sim_open): Delete check for host endianness - performed by
2246 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2247 (sim_open): Move much of the initialization from here.
2248 (sim_load): To here. After the image has been loaded and
2250 (sim_open): Move ColdReset from here.
2251 (sim_create_inferior): To here.
2252 (sim_open): Make FP check less dependant on host endianness.
2254 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2256 * interp.c (sim_set_callbacks): Delete.
2258 * interp.c (membank, membank_base, membank_size): Replace with
2259 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2260 (sim_open): Remove call to callback->init. gdb/run do this.
2264 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2266 * interp.c (big_endian_p): Delete, replaced by
2267 current_target_byte_order.
2269 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2271 * interp.c (host_read_long, host_read_word, host_swap_word,
2272 host_swap_long): Delete. Using common sim-endian.
2273 (sim_fetch_register, sim_store_register): Use H2T.
2274 (pipeline_ticks): Delete. Handled by sim-events.
2276 (sim_engine_run): Update.
2278 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2280 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2282 (SignalException): To here. Signal using sim_engine_halt.
2283 (sim_stop_reason): Delete, moved to common.
2285 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2287 * interp.c (sim_open): Add callback argument.
2288 (sim_set_callbacks): Delete SIM_DESC argument.
2291 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2293 * Makefile.in (SIM_OBJS): Add common modules.
2295 * interp.c (sim_set_callbacks): Also set SD callback.
2296 (set_endianness, xfer_*, swap_*): Delete.
2297 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2298 Change to functions using sim-endian macros.
2299 (control_c, sim_stop): Delete, use common version.
2300 (simulate): Convert into.
2301 (sim_engine_run): This function.
2302 (sim_resume): Delete.
2304 * interp.c (simulation): New variable - the simulator object.
2305 (sim_kind): Delete global - merged into simulation.
2306 (sim_load): Cleanup. Move PC assignment from here.
2307 (sim_create_inferior): To here.
2309 * sim-main.h: New file.
2310 * interp.c (sim-main.h): Include.
2312 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2314 * configure: Regenerated to track ../common/aclocal.m4 changes.
2316 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2318 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2320 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2322 * gencode.c (build_instruction): DIV instructions: check
2323 for division by zero and integer overflow before using
2324 host's division operation.
2326 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2328 * Makefile.in (SIM_OBJS): Add sim-load.o.
2329 * interp.c: #include bfd.h.
2330 (target_byte_order): Delete.
2331 (sim_kind, myname, big_endian_p): New static locals.
2332 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2333 after argument parsing. Recognize -E arg, set endianness accordingly.
2334 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2335 load file into simulator. Set PC from bfd.
2336 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2337 (set_endianness): Use big_endian_p instead of target_byte_order.
2339 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2341 * interp.c (sim_size): Delete prototype - conflicts with
2342 definition in remote-sim.h. Correct definition.
2344 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2346 * configure: Regenerated to track ../common/aclocal.m4 changes.
2349 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2351 * interp.c (sim_open): New arg `kind'.
2353 * configure: Regenerated to track ../common/aclocal.m4 changes.
2355 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2357 * configure: Regenerated to track ../common/aclocal.m4 changes.
2359 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2361 * interp.c (sim_open): Set optind to 0 before calling getopt.
2363 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2365 * configure: Regenerated to track ../common/aclocal.m4 changes.
2367 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2369 * interp.c : Replace uses of pr_addr with pr_uword64
2370 where the bit length is always 64 independent of SIM_ADDR.
2371 (pr_uword64) : added.
2373 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2375 * configure: Re-generate.
2377 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2379 * configure: Regenerate to track ../common/aclocal.m4 changes.
2381 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2383 * interp.c (sim_open): New SIM_DESC result. Argument is now
2385 (other sim_*): New SIM_DESC argument.
2387 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2389 * interp.c: Fix printing of addresses for non-64-bit targets.
2390 (pr_addr): Add function to print address based on size.
2392 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2394 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2396 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2398 * gencode.c (build_mips16_operands): Correct computation of base
2399 address for extended PC relative instruction.
2401 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2403 * interp.c (mips16_entry): Add support for floating point cases.
2404 (SignalException): Pass floating point cases to mips16_entry.
2405 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2407 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2409 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2410 and then set the state to fmt_uninterpreted.
2411 (COP_SW): Temporarily set the state to fmt_word while calling
2414 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2416 * gencode.c (build_instruction): The high order may be set in the
2417 comparison flags at any ISA level, not just ISA 4.
2419 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2421 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2422 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2423 * configure.in: sinclude ../common/aclocal.m4.
2424 * configure: Regenerated.
2426 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2428 * configure: Rebuild after change to aclocal.m4.
2430 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2432 * configure configure.in Makefile.in: Update to new configure
2433 scheme which is more compatible with WinGDB builds.
2434 * configure.in: Improve comment on how to run autoconf.
2435 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2436 * Makefile.in: Use autoconf substitution to install common
2439 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2441 * gencode.c (build_instruction): Use BigEndianCPU instead of
2444 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2446 * interp.c (sim_monitor): Make output to stdout visible in
2447 wingdb's I/O log window.
2449 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2451 * support.h: Undo previous change to SIGTRAP
2454 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2456 * interp.c (store_word, load_word): New static functions.
2457 (mips16_entry): New static function.
2458 (SignalException): Look for mips16 entry and exit instructions.
2459 (simulate): Use the correct index when setting fpr_state after
2460 doing a pending move.
2462 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2464 * interp.c: Fix byte-swapping code throughout to work on
2465 both little- and big-endian hosts.
2467 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2469 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2470 with gdb/config/i386/xm-windows.h.
2472 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2474 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2475 that messes up arithmetic shifts.
2477 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2479 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2480 SIGTRAP and SIGQUIT for _WIN32.
2482 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2484 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2485 force a 64 bit multiplication.
2486 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2487 destination register is 0, since that is the default mips16 nop
2490 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2492 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2493 (build_endian_shift): Don't check proc64.
2494 (build_instruction): Always set memval to uword64. Cast op2 to
2495 uword64 when shifting it left in memory instructions. Always use
2496 the same code for stores--don't special case proc64.
2498 * gencode.c (build_mips16_operands): Fix base PC value for PC
2500 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2502 * interp.c (simJALDELAYSLOT): Define.
2503 (JALDELAYSLOT): Define.
2504 (INDELAYSLOT, INJALDELAYSLOT): Define.
2505 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2507 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2509 * interp.c (sim_open): add flush_cache as a PMON routine
2510 (sim_monitor): handle flush_cache by ignoring it
2512 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2514 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2516 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2517 (BigEndianMem): Rename to ByteSwapMem and change sense.
2518 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2519 BigEndianMem references to !ByteSwapMem.
2520 (set_endianness): New function, with prototype.
2521 (sim_open): Call set_endianness.
2522 (sim_info): Use simBE instead of BigEndianMem.
2523 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2524 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2525 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2526 ifdefs, keeping the prototype declaration.
2527 (swap_word): Rewrite correctly.
2528 (ColdReset): Delete references to CONFIG. Delete endianness related
2529 code; moved to set_endianness.
2531 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2533 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2534 * interp.c (CHECKHILO): Define away.
2535 (simSIGINT): New macro.
2536 (membank_size): Increase from 1MB to 2MB.
2537 (control_c): New function.
2538 (sim_resume): Rename parameter signal to signal_number. Add local
2539 variable prev. Call signal before and after simulate.
2540 (sim_stop_reason): Add simSIGINT support.
2541 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2543 (sim_warning): Delete call to SignalException. Do call printf_filtered
2545 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2546 a call to sim_warning.
2548 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2550 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2551 16 bit instructions.
2553 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2555 Add support for mips16 (16 bit MIPS implementation):
2556 * gencode.c (inst_type): Add mips16 instruction encoding types.
2557 (GETDATASIZEINSN): Define.
2558 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2559 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2561 (MIPS16_DECODE): New table, for mips16 instructions.
2562 (bitmap_val): New static function.
2563 (struct mips16_op): Define.
2564 (mips16_op_table): New table, for mips16 operands.
2565 (build_mips16_operands): New static function.
2566 (process_instructions): If PC is odd, decode a mips16
2567 instruction. Break out instruction handling into new
2568 build_instruction function.
2569 (build_instruction): New static function, broken out of
2570 process_instructions. Check modifiers rather than flags for SHIFT
2571 bit count and m[ft]{hi,lo} direction.
2572 (usage): Pass program name to fprintf.
2573 (main): Remove unused variable this_option_optind. Change
2574 ``*loptarg++'' to ``loptarg++''.
2575 (my_strtoul): Parenthesize && within ||.
2576 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2577 (simulate): If PC is odd, fetch a 16 bit instruction, and
2578 increment PC by 2 rather than 4.
2579 * configure.in: Add case for mips16*-*-*.
2580 * configure: Rebuild.
2582 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2584 * interp.c: Allow -t to enable tracing in standalone simulator.
2585 Fix garbage output in trace file and error messages.
2587 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2589 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2590 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2591 * configure.in: Simplify using macros in ../common/aclocal.m4.
2592 * configure: Regenerated.
2593 * tconfig.in: New file.
2595 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2597 * interp.c: Fix bugs in 64-bit port.
2598 Use ansi function declarations for msvc compiler.
2599 Initialize and test file pointer in trace code.
2600 Prevent duplicate definition of LAST_EMED_REGNUM.
2602 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2604 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2606 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2608 * interp.c (SignalException): Check for explicit terminating
2610 * gencode.c: Pass instruction value through SignalException()
2611 calls for Trap, Breakpoint and Syscall.
2613 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2615 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2616 only used on those hosts that provide it.
2617 * configure.in: Add sqrt() to list of functions to be checked for.
2618 * config.in: Re-generated.
2619 * configure: Re-generated.
2621 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2623 * gencode.c (process_instructions): Call build_endian_shift when
2624 expanding STORE RIGHT, to fix swr.
2625 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2626 clear the high bits.
2627 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2628 Fix float to int conversions to produce signed values.
2630 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2632 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2633 (process_instructions): Correct handling of nor instruction.
2634 Correct shift count for 32 bit shift instructions. Correct sign
2635 extension for arithmetic shifts to not shift the number of bits in
2636 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2637 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2639 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2640 It's OK to have a mult follow a mult. What's not OK is to have a
2641 mult follow an mfhi.
2642 (Convert): Comment out incorrect rounding code.
2644 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2646 * interp.c (sim_monitor): Improved monitor printf
2647 simulation. Tidied up simulator warnings, and added "--log" option
2648 for directing warning message output.
2649 * gencode.c: Use sim_warning() rather than WARNING macro.
2651 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2653 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2654 getopt1.o, rather than on gencode.c. Link objects together.
2655 Don't link against -liberty.
2656 (gencode.o, getopt.o, getopt1.o): New targets.
2657 * gencode.c: Include <ctype.h> and "ansidecl.h".
2658 (AND): Undefine after including "ansidecl.h".
2659 (ULONG_MAX): Define if not defined.
2660 (OP_*): Don't define macros; now defined in opcode/mips.h.
2661 (main): Call my_strtoul rather than strtoul.
2662 (my_strtoul): New static function.
2664 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2666 * gencode.c (process_instructions): Generate word64 and uword64
2667 instead of `long long' and `unsigned long long' data types.
2668 * interp.c: #include sysdep.h to get signals, and define default
2670 * (Convert): Work around for Visual-C++ compiler bug with type
2672 * support.h: Make things compile under Visual-C++ by using
2673 __int64 instead of `long long'. Change many refs to long long
2674 into word64/uword64 typedefs.
2676 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2678 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2679 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2681 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2682 (AC_PROG_INSTALL): Added.
2683 (AC_PROG_CC): Moved to before configure.host call.
2684 * configure: Rebuilt.
2686 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2688 * configure.in: Define @SIMCONF@ depending on mips target.
2689 * configure: Rebuild.
2690 * Makefile.in (run): Add @SIMCONF@ to control simulator
2692 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2693 * interp.c: Remove some debugging, provide more detailed error
2694 messages, update memory accesses to use LOADDRMASK.
2696 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2698 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2699 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2701 * configure: Rebuild.
2702 * config.in: New file, generated by autoheader.
2703 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2704 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2705 HAVE_ANINT and HAVE_AINT, as appropriate.
2706 * Makefile.in (run): Use @LIBS@ rather than -lm.
2707 (interp.o): Depend upon config.h.
2708 (Makefile): Just rebuild Makefile.
2709 (clean): Remove stamp-h.
2710 (mostlyclean): Make the same as clean, not as distclean.
2711 (config.h, stamp-h): New targets.
2713 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2715 * interp.c (ColdReset): Fix boolean test. Make all simulator
2718 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2720 * interp.c (xfer_direct_word, xfer_direct_long,
2721 swap_direct_word, swap_direct_long, xfer_big_word,
2722 xfer_big_long, xfer_little_word, xfer_little_long,
2723 swap_word,swap_long): Added.
2724 * interp.c (ColdReset): Provide function indirection to
2725 host<->simulated_target transfer routines.
2726 * interp.c (sim_store_register, sim_fetch_register): Updated to
2727 make use of indirected transfer routines.
2729 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2731 * gencode.c (process_instructions): Ensure FP ABS instruction
2733 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2734 system call support.
2736 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2738 * interp.c (sim_do_command): Complain if callback structure not
2741 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2743 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2744 support for Sun hosts.
2745 * Makefile.in (gencode): Ensure the host compiler and libraries
2746 used for cross-hosted build.
2748 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2750 * interp.c, gencode.c: Some more (TODO) tidying.
2752 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2754 * gencode.c, interp.c: Replaced explicit long long references with
2755 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2756 * support.h (SET64LO, SET64HI): Macros added.
2758 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2760 * configure: Regenerate with autoconf 2.7.
2762 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2764 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2765 * support.h: Remove superfluous "1" from #if.
2766 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2768 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2770 * interp.c (StoreFPR): Control UndefinedResult() call on
2771 WARN_RESULT manifest.
2773 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2775 * gencode.c: Tidied instruction decoding, and added FP instruction
2778 * interp.c: Added dineroIII, and BSD profiling support. Also
2779 run-time FP handling.
2781 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2783 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2784 gencode.c, interp.c, support.h: created.