1 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
3 * interp.c: #include "itable.h" if WITH_IGEN.
4 (get_insn_name): New function.
5 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
6 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
9 Tue Sep 22 10:35:37 1998 Frank Ch. Eigler <fche@cygnus.com>
11 * sim-main.c (tlb_try_match): Specially match virtual
12 pages mapped to scratchpad RAM, an unimplemented feature.
16 Fri Sep 18 11:31:16 1998 Frank Ch. Eigler <fche@cygnus.com>
18 * r5900.igen (prot3w): Correct rotation sequence; patch
22 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
24 * configure: Rebuilt to inhale new common/aclocal.m4.
27 Thu Sep 10 11:50:54 1998 Doug Evans <devans@canuck.cygnus.com>
29 * r5900.igen (plzcw): Make `i' signed.
31 Wed Sep 9 15:02:10 1998 Doug Evans <devans@canuck.cygnus.com>
33 * sim-main.h (COP0_COUNT,COP0_COMPARE,status_IM7): New macros.
34 * sky-engine.c (cpu_issue): Increment COP0_COUNT and signal an
35 interrupt if == COP0_COMPARE and interrupt masks/enables allow it.
36 * interp.c (signal_exception, sky version): Handle INT 2.
38 Wed Sep 9 11:28:20 1998 Ron Unrau <runrau@cygnus.com>
40 * sim-main.h: track COP0 registers
41 * interp.c (sim_{fetch,store}_register): read/write COP0 registers
43 Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
45 * r5900.igen (mtsab): Correct typo in input register.
47 * sim-main.h (TMP_*): New macros for accessing local 128-bit
48 temporary for multimedia instructions.
49 * r5900.igen (*): Convert most instructions to use new TMP
50 macros to store output result during computation.
54 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
56 * dv-tx3904sio.c: Include sim-assert.h.
58 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
60 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
61 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
62 Reorganize target-specific sim-hardware checks.
64 * interp.c (sim_open): For tx39 target boards, set
65 OPERATING_ENVIRONMENT, add tx3904sio devices.
66 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
67 ROM executables. Install dv-sockser into sim-modules list.
69 * dv-tx3904irc.c: Compiler warning clean-up.
70 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
71 frequent hw-trace messages.
75 Tue Aug 11 13:52:16 1998 Frank Ch. Eigler <fche@cygnus.com>
77 * interp.c (signal_exception): Set IP3 bit in CAUSE on
81 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
83 * vr.igen (MulAcc): Identify as a vr4100 specific function.
85 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
87 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
90 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
91 * mips.igen: Define vr4100 model. Include vr.igen.
93 * vr5400.igen: Move instructions to vr.igen
94 * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen.
97 * vr4320.igen: Move instructions to vr.igen.
98 * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen.
102 Fri Jul 24 16:01:03 1998 Ian Carmichael <iancarm@cygnus.com>
104 * interp.c (MONITOR_SIZE): Make 1MB monitor for SKY.
105 * mips.igen (BREAK): Fix 0xffff2 monitor call. Slightly less
106 confusing message if not enough --load-next options appear.
108 * sky-pke.h (VUx_MEMx_SRCADDR_START): Move to 0x19800000 range.
109 * sim-main.c (GDB_COMM_AREA): Move to 0x19810000.
110 * sky-gdb.c (init_fifo_bp_cache): Use VIO_BASE when reading GDB area.
111 (resume_handler): Same.
112 (suspend_handler): Same.
114 Wed Jul 22 13:04:13 1998 Frank Ch. Eigler <fche@cygnus.com>
116 * mips.igen (break): Implement LOAD_INSTRUCTION ("break 0xffff1")
117 to trigger multi-phase load.
119 * sim-main.c: Include sim-assert.h for ASSERT macro.
120 * sim-main.h (PRINTF_INSTRUCTION): Correct bit pattern for
123 Tue Jul 21 18:37:36 1998 Ian Carmichael <iancarm@cygnus.com>
126 * interp.c (sim_open): Initialize TLB.
127 * interp.c (signal_exceptions): New 5900 handling.
128 * r5900.igen (TLBWR, TLBWI, TLBR, TLBP): Make these work.
129 * sim-main.c (tlb_try_match, tlb_lookup): New functions.
130 (address_translation): Use the TLB.
131 * sim-main.h (r4000_tlb_entry_t): New type.
132 (TLB_*): New constants.
133 (COP0_*): New register names.
135 Sky character I/O device.
136 * sky-psio.c: New file.
137 * sky-psio.h: New file.
138 * Makefile.in: Add sky-psio.o.
142 Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
144 * r5900.igen (r59fp_overflow): Replace argument ANS with argument
147 (r59fp_store): Update calls.
148 (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
151 start-sanitize-branchbug4011
152 Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com>
154 * interp.c (OPTION_BRANCH_BUG_4011): Add.
155 (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
156 (mips_options): Define the option.
157 * mips.igen (check_4011_branch_bug): New.
158 (mark_4011_branch_bug): New.
159 (all branch insn): Call mark_branch_bug, and check_branch_bug.
160 * sim-main.h (branchbug4011_option, branchbug4011_last_target,
161 branchbug4011_last_cia, BRANCHBUG4011_OPTION,
162 BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
163 check_branch_bug, mark_branch_bug): Define.
165 end-sanitize-branchbug4011
166 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
168 * mips.igen (check_mf_hilo): Correct check.
171 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
173 * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
174 COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
175 purpose registers, add 8 COP0 break-point registers, add 64 COP0
176 performance registers.
178 * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
179 MFP* instructions. Just transfer value to/from corresponding
182 * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
183 status is always true.
184 (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
185 (EI, DI): Set/clear Status-EIE bit.
189 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
191 * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
195 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
198 * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
200 * sky-gdb.c: Include "sim-assert.h".
203 * sim-main.h (interrupt_event): Add prototype.
205 start-sanitize-tx3904
206 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
207 register_ptr, register_value.
208 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
211 * sim-main.h (tracefh): Make extern.
213 start-sanitize-tx3904
214 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
216 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
217 Reduce unnecessarily high timer event frequency.
218 * dv-tx3904cpu.c: Ditto for interrupt event.
222 Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com>
224 * interp.c (decode_coproc): Removed COP2 branches.
225 * r5900.igen: Moved COP2 branch instructions here.
226 * mips.igen: Restricted COPz == COP2 bit pattern to
227 exclude COP2 branches.
230 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
232 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
234 (interrupt_event): Made non-static.
235 start-sanitize-tx3904
237 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
238 interchange of configuration values for external vs. internal
242 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
244 * mips.igen (BREAK): Moved code to here for
245 simulator-reserved break instructions.
246 * gencode.c (build_instruction): Ditto.
247 * interp.c (signal_exception): Code moved from here. Non-
248 reserved instructions now use exception vector, rather
250 * sim-main.h: Moved magic constants to here.
252 start-sanitize-tx3904
253 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
255 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
256 register upon non-zero interrupt event level, clear upon zero
258 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
259 by passing zero event value.
260 (*_io_{read,write}_buffer): Endianness fixes.
261 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
262 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
264 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
265 serial I/O and timer module at base address 0xFFFF0000.
268 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
270 * mips.igen (SWC1) : Correct the handling of ReverseEndian
273 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
275 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
279 start-sanitize-tx3904
280 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
282 * dv-tx3904tmr.c: New file - implements tx3904 timer.
283 * dv-tx3904{irc,cpu}.c: Mild reformatting.
284 * configure.in: Include tx3904tmr in hw_device list.
285 * configure: Rebuilt.
286 * interp.c (sim_open): Instantiate three timer instances.
287 Fix address typo of tx3904irc instance.
291 Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
293 * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
294 Select corresponding check_mt_hilo function.
295 (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
298 * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
302 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
304 * interp.c (signal_exception): SystemCall exception now uses
305 the exception vector.
307 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
309 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
313 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
315 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
319 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
321 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
323 start-sanitize-tx3904
324 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
326 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
328 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
329 sim-main.h. Declare a struct hw_descriptor instead of struct
330 hw_device_descriptor.
333 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
335 * mips.igen (do_store_left, do_load_left): Compute nr of left and
336 right bits and then re-align left hand bytes to correct byte
337 lanes. Fix incorrect computation in do_store_left when loading
338 bytes from second word.
340 start-sanitize-tx3904
341 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
343 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
344 * interp.c (sim_open): Only create a device tree when HW is
347 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
348 * interp.c (signal_exception): Ditto.
351 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
353 * gencode.c: Mark BEGEZALL as LIKELY.
355 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
357 * sim-main.h (ALU32_END): Sign extend 32 bit results.
358 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
361 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
363 * interp.c (sim_fetch_register): Convert internal r5900 regs to
367 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
369 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
370 modules. Recognize TX39 target with "mips*tx39" pattern.
371 * configure: Rebuilt.
372 * sim-main.h (*): Added many macros defining bits in
373 TX39 control registers.
374 (SignalInterrupt): Send actual PC instead of NULL.
375 (SignalNMIReset): New exception type.
376 * interp.c (board): New variable for future use to identify
377 a particular board being simulated.
378 (mips_option_handler,mips_options): Added "--board" option.
379 (interrupt_event): Send actual PC.
380 (sim_open): Make memory layout conditional on board setting.
381 (signal_exception): Initial implementation of hardware interrupt
382 handling. Accept another break instruction variant for simulator
384 (decode_coproc): Implement RFE instruction for TX39.
385 (mips.igen): Decode RFE instruction as such.
386 start-sanitize-tx3904
387 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
388 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
389 bbegin to implement memory map.
390 * dv-tx3904cpu.c: New file.
391 * dv-tx3904irc.c: New file.
394 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
396 * mips.igen (check_mt_hilo): Create a separate r3900 version.
399 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
401 * r5900.igen: Replace the calls and the definition of the
402 function check_op_hilo_hi1lo1 with the pair
403 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
406 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
408 * tx.igen (madd,maddu): Replace calls to check_op_hilo
409 with calls to check_div_hilo.
411 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
413 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
414 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
415 Add special r3900 version of do_mult_hilo.
416 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
417 with calls to check_mult_hilo.
418 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
419 with calls to check_div_hilo.
421 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
423 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
424 Document a replacement.
426 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
428 * interp.c (sim_monitor): Make mon_printf work.
430 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
432 * sim-main.h (INSN_NAME): New arg `cpu'.
435 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
437 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
442 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
444 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
445 * r5900.igen (r59fp_overflow): Use.
447 * r5900.igen (r59fp_op3): Rename to
448 (r59fp_mula): This, delete opm argument.
449 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
450 (r59fp_mula): Overflowing product propogates through to result.
451 (r59fp_mula): ACC to the MAX propogates to result.
452 (r59fp_mula): Underflow during multiply only sets SU.
455 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
457 * configure: Regenerated to track ../common/aclocal.m4 changes.
459 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
461 * configure: Regenerated to track ../common/aclocal.m4 changes.
464 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
466 * acconfig.h: New file.
467 * configure.in: Reverted change of Apr 24; use sinclude again.
469 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
471 * configure: Regenerated to track ../common/aclocal.m4 changes.
474 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
476 * configure.in: Don't call sinclude.
478 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
480 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
482 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
484 * mips.igen (ERET): Implement.
486 * interp.c (decode_coproc): Return sign-extended EPC.
488 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
490 * interp.c (signal_exception): Do not ignore Trap.
491 (signal_exception): On TRAP, restart at exception address.
492 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
493 (signal_exception): Update.
494 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
495 so that TRAP instructions are caught.
497 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
499 * sim-main.h (struct hilo_access, struct hilo_history): Define,
500 contains HI/LO access history.
501 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
502 (HIACCESS, LOACCESS): Delete, replace with
503 (HIHISTORY, LOHISTORY): New macros.
504 (start-sanitize-r5900):
505 (struct sim_5900_cpu): Make hi1access, lo1access of type
507 (HI1ACCESS, LO1ACCESS): Delete, replace with
508 (HI1HISTORY, LO1HISTORY): New macros.
509 (end-sanitize-r5900):
510 (CHECKHILO): Delete all, moved to mips.igen
512 * gencode.c (build_instruction): Do not generate checks for
513 correct HI/LO register usage.
515 * interp.c (old_engine_run): Delete checks for correct HI/LO
518 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
519 check_mf_cycles): New functions.
520 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
521 do_divu, domultx, do_mult, do_multu): Use.
523 * tx.igen ("madd", "maddu"): Use.
524 (start-sanitize-r5900):
526 r5900.igen: Update all HI/LO checks.
527 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
528 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
529 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
530 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
531 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
533 (end-sanitize-r5900):
536 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
538 * interp.c (decode_coproc): Correct CMFC2/QMTC2
541 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
542 instead of a single 128-bit access.
546 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
548 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
549 * interp.c (cop_[ls]q): Fixes corresponding to above.
553 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
555 * interp.c (decode_coproc): Adapt COP2 micro interlock to
556 clarified specs. Reset "M" bit; exit also on "E" bit.
560 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
562 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
563 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
565 * r5900.igen (r59fp_unpack): New function.
566 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
567 RSQRT.S, SQRT.S): Use.
568 (r59fp_zero): New function.
569 (r59fp_overflow): Generate r5900 specific overflow value.
570 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
572 (CVT.S.W, CVT.W.S): Exchange implementations.
574 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
578 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
580 * configure.in (tx19, sim_use_gen): Switch to igen.
581 * configure: Re-build.
585 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
587 * interp.c (decode_coproc): Make COP2 branch code compile after
588 igen signature changes.
591 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
593 * mips.igen (DSRAV): Use function do_dsrav.
594 (SRAV): Use new function do_srav.
596 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
597 (B): Sign extend 11 bit immediate.
598 (EXT-B*): Shift 16 bit immediate left by 1.
599 (ADDIU*): Don't sign extend immediate value.
601 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
603 * m16run.c (sim_engine_run): Restore CIA after handling an event.
606 * mips.igen (mtc0): Valid tx19 instruction.
609 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
612 * mips.igen (delayslot32, nullify_next_insn): New functions.
613 (m16.igen): Always include.
614 (do_*): Add more tracing.
616 * m16.igen (delayslot16): Add NIA argument, could be called by a
617 32 bit MIPS16 instruction.
619 * interp.c (ifetch16): Move function from here.
620 * sim-main.c (ifetch16): To here.
622 * sim-main.c (ifetch16, ifetch32): Update to match current
623 implementations of LH, LW.
624 (signal_exception): Don't print out incorrect hex value of illegal
627 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
629 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
632 * m16.igen: Implement MIPS16 instructions.
634 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
635 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
636 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
637 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
638 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
639 bodies of corresponding code from 32 bit insn to these. Also used
640 by MIPS16 versions of functions.
642 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
643 (IMEM16): Drop NR argument from macro.
646 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
648 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
649 of VU lower instruction.
653 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
655 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
658 * sim-main.h: Removed attempt at allowing 128-bit access.
662 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
664 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
666 * interp.c (decode_coproc): Refer to VU CIA as a "special"
667 register, not as a "misc" register. Aha. Add activity
668 assertions after VCALLMS* instructions.
672 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
674 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
675 to upper code of generated VU instruction.
679 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
681 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
683 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
686 * r5900.igen (SQC2): Thinko.
690 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
692 * interp.c (*): Adapt code to merged VU device & state structs.
693 (decode_coproc): Execute COP2 each macroinstruction without
694 pipelining, by stepping VU to completion state. Adapted to
695 read_vu_*_reg style of register access.
697 * mips.igen ([SL]QC2): Removed these COP2 instructions.
699 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
701 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
704 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
706 * Makefile.in (SIM_OBJS): Add sim-main.o.
708 * sim-main.h (address_translation, load_memory, store_memory,
709 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
711 (pr_addr, pr_uword64): Declare.
712 (sim-main.c): Include when H_REVEALS_MODULE_P.
714 * interp.c (address_translation, load_memory, store_memory,
715 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
717 * sim-main.c: To here. Fix compilation problems.
719 * configure.in: Enable inlining.
720 * configure: Re-config.
722 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
724 * configure: Regenerated to track ../common/aclocal.m4 changes.
726 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
728 * mips.igen: Include tx.igen.
729 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
730 * tx.igen: New file, contains MADD and MADDU.
732 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
733 the hardwired constant `7'.
734 (store_memory): Ditto.
735 (LOADDRMASK): Move definition to sim-main.h.
737 mips.igen (MTC0): Enable for r3900.
740 mips.igen (do_load_byte): Delete.
741 (do_load, do_store, do_load_left, do_load_write, do_store_left,
742 do_store_right): New functions.
743 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
745 configure.in: Let the tx39 use igen again.
748 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
750 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
751 not an address sized quantity. Return zero for cache sizes.
753 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
755 * mips.igen (r3900): r3900 does not support 64 bit integer
759 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
761 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
765 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
767 * interp.c (decode_coproc): Continuing COP2 work.
768 (cop_[ls]q): Make sky-target-only.
770 * sim-main.h (COP_[LS]Q): Make sky-target-only.
772 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
774 * configure.in (mipstx39*-*-*): Use gencode simulator rather
776 * configure : Rebuild.
779 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
781 * interp.c (decode_coproc): Added a missing TARGET_SKY check
782 around COP2 implementation skeleton.
786 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
788 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
790 * interp.c (sim_{load,store}_register): Use new vu[01]_device
791 static to access VU registers.
792 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
793 decoding. Work in progress.
795 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
796 overlapping/redundant bit pattern.
797 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
800 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
803 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
804 access to coprocessor registers.
806 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
808 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
810 * configure: Regenerated to track ../common/aclocal.m4 changes.
812 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
814 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
816 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
818 * configure: Regenerated to track ../common/aclocal.m4 changes.
819 * config.in: Regenerated to track ../common/aclocal.m4 changes.
821 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
823 * configure: Regenerated to track ../common/aclocal.m4 changes.
825 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
827 * interp.c (Max, Min): Comment out functions. Not yet used.
829 start-sanitize-vr4320
830 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
832 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
835 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
837 * configure: Regenerated to track ../common/aclocal.m4 changes.
839 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
841 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
842 configurable settings for stand-alone simulator.
845 * configure.in: Added --with-sim-gpu2 option to specify path of
846 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
847 links/compiles stand-alone simulator with this library.
849 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
851 * configure.in: Added X11 search, just in case.
853 * configure: Regenerated.
855 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
857 * interp.c (sim_write, sim_read, load_memory, store_memory):
858 Replace sim_core_*_map with read_map, write_map, exec_map resp.
860 start-sanitize-vr4320
861 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
863 * vr4320.igen (clz,dclz) : Added.
864 (dmac): Replaced 99, with LO.
867 start-sanitize-cygnus
868 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
870 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
873 start-sanitize-vr4320
874 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
876 * vr4320.igen: New file.
877 * Makefile.in (vr4320.igen) : Added.
878 * configure.in (mips64vr4320-*-*): Added.
879 * configure : Rebuilt.
880 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
881 Add the vr4320 model entry and mark the vr4320 insn as necessary.
884 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
886 * sim-main.h (GETFCC): Return an unsigned value.
889 * r5900.igen: Use an unsigned array index variable `i'.
890 (QFSRV): Ditto for variable bytes.
893 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
895 * mips.igen (DIV): Fix check for -1 / MIN_INT.
896 (DADD): Result destination is RD not RT.
899 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
900 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
904 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
906 * sim-main.h (HIACCESS, LOACCESS): Always define.
908 * mdmx.igen (Maxi, Mini): Rename Max, Min.
910 * interp.c (sim_info): Delete.
912 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
914 * interp.c (DECLARE_OPTION_HANDLER): Use it.
915 (mips_option_handler): New argument `cpu'.
916 (sim_open): Update call to sim_add_option_table.
918 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
920 * mips.igen (CxC1): Add tracing.
923 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
925 * r5900.igen (StoreFP): Delete.
926 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
928 (rsqrt.s, sqrt.s): Implement.
929 (r59cond): New function.
930 (C.COND.S): Call r59cond in assembler line.
931 (cvt.w.s, cvt.s.w): Implement.
933 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
936 * sim-main.h: Define an enum of r5900 FCSR bit fields.
940 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
942 * r5900.igen: Add tracing to all p* instructions.
944 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
946 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
947 to get gdb talking to re-aranged sim_cpu register structure.
950 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
952 * sim-main.h (Max, Min): Declare.
954 * interp.c (Max, Min): New functions.
956 * mips.igen (BC1): Add tracing.
958 start-sanitize-cygnus
959 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
961 * mdmx.igen: Tag all functions as requiring either with mdmx or
966 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
968 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
970 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
972 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
974 * r5900.igen: Rewrite.
976 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
978 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
979 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
982 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
984 * interp.c Added memory map for stack in vr4100
986 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
988 * interp.c (load_memory): Add missing "break"'s.
990 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
992 * interp.c (sim_store_register, sim_fetch_register): Pass in
993 length parameter. Return -1.
995 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
997 * interp.c: Added hardware init hook, fixed warnings.
999 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1001 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1003 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1005 * interp.c (ifetch16): New function.
1007 * sim-main.h (IMEM32): Rename IMEM.
1008 (IMEM16_IMMED): Define.
1010 (DELAY_SLOT): Update.
1012 * m16run.c (sim_engine_run): New file.
1014 * m16.igen: All instructions except LB.
1015 (LB): Call do_load_byte.
1016 * mips.igen (do_load_byte): New function.
1017 (LB): Call do_load_byte.
1019 * mips.igen: Move spec for insn bit size and high bit from here.
1020 * Makefile.in (tmp-igen, tmp-m16): To here.
1022 * m16.dc: New file, decode mips16 instructions.
1024 * Makefile.in (SIM_NO_ALL): Define.
1025 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1028 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
1032 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1034 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1035 point unit to 32 bit registers.
1036 * configure: Re-generate.
1038 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1040 * configure.in (sim_use_gen): Make IGEN the default simulator
1041 generator for generic 32 and 64 bit mips targets.
1042 * configure: Re-generate.
1044 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1046 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1049 * interp.c (sim_fetch_register, sim_store_register): Read/write
1050 FGR from correct location.
1051 (sim_open): Set size of FGR's according to
1052 WITH_TARGET_FLOATING_POINT_BITSIZE.
1054 * sim-main.h (FGR): Store floating point registers in a separate
1057 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1059 * configure: Regenerated to track ../common/aclocal.m4 changes.
1061 start-sanitize-cygnus
1062 * mdmx.igen: Mark all instructions as 64bit/fp specific.
1065 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1067 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1069 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1071 * interp.c (pending_tick): New function. Deliver pending writes.
1073 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1074 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1075 it can handle mixed sized quantites and single bits.
1077 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1079 * interp.c (oengine.h): Do not include when building with IGEN.
1080 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1081 (sim_info): Ditto for PROCESSOR_64BIT.
1082 (sim_monitor): Replace ut_reg with unsigned_word.
1083 (*): Ditto for t_reg.
1084 (LOADDRMASK): Define.
1085 (sim_open): Remove defunct check that host FP is IEEE compliant,
1086 using software to emulate floating point.
1087 (value_fpr, ...): Always compile, was conditional on HASFPU.
1089 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1091 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1094 * interp.c (SD, CPU): Define.
1095 (mips_option_handler): Set flags in each CPU.
1096 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1097 (sim_close): Do not clear STATE, deleted anyway.
1098 (sim_write, sim_read): Assume CPU zero's vm should be used for
1100 (sim_create_inferior): Set the PC for all processors.
1101 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1103 (mips16_entry): Pass correct nr of args to store_word, load_word.
1104 (ColdReset): Cold reset all cpu's.
1105 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1106 (sim_monitor, load_memory, store_memory, signal_exception): Use
1107 `CPU' instead of STATE_CPU.
1110 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1113 * sim-main.h (signal_exception): Add sim_cpu arg.
1114 (SignalException*): Pass both SD and CPU to signal_exception.
1115 * interp.c (signal_exception): Update.
1117 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1119 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1120 address_translation): Ditto
1121 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1123 start-sanitize-cygnus
1124 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
1126 (ByteAlign): Use StoreFPR, pass args in correct order.
1129 start-sanitize-r5900
1130 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1132 * configure.in (sim_igen_filter): For r5900, configure as SMP.
1135 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1137 * configure: Regenerated to track ../common/aclocal.m4 changes.
1139 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1141 start-sanitize-r5900
1142 * configure.in (sim_igen_filter): For r5900, use igen.
1143 * configure: Re-generate.
1146 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1148 * mips.igen (model): Map processor names onto BFD name.
1150 * sim-main.h (CPU_CIA): Delete.
1151 (SET_CIA, GET_CIA): Define
1153 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1155 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1158 * configure.in (default_endian): Configure a big-endian simulator
1160 * configure: Re-generate.
1162 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1164 * configure: Regenerated to track ../common/aclocal.m4 changes.
1166 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1168 * interp.c (sim_monitor): Handle Densan monitor outbyte
1169 and inbyte functions.
1171 1997-12-29 Felix Lee <flee@cygnus.com>
1173 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1175 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1177 * Makefile.in (tmp-igen): Arrange for $zero to always be
1178 reset to zero after every instruction.
1180 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1182 * configure: Regenerated to track ../common/aclocal.m4 changes.
1185 start-sanitize-cygnus
1186 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1188 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1191 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
1193 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1194 vr5400 with the vr5000 as the default.
1197 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1199 * mips.igen (MSUB): Fix to work like MADD.
1200 * gencode.c (MSUB): Similarly.
1202 start-sanitize-cygnus
1203 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
1205 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1209 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1211 * configure: Regenerated to track ../common/aclocal.m4 changes.
1213 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1215 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1217 start-sanitize-cygnus
1218 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1219 (value_cc, store_cc): Implement.
1221 * sim-main.h: Add 8*3*8 bit accumulator.
1223 * vr5400.igen: Move mdmx instructins from here
1224 * mdmx.igen: To here - new file. Add/fix missing instructions.
1225 * mips.igen: Include mdmx.igen.
1226 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1229 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1231 * sim-main.h (sim-fpu.h): Include.
1233 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1234 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1235 using host independant sim_fpu module.
1237 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1239 * interp.c (signal_exception): Report internal errors with SIGABRT
1242 * sim-main.h (C0_CONFIG): New register.
1243 (signal.h): No longer include.
1245 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1247 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1249 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1251 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1253 * mips.igen: Tag vr5000 instructions.
1254 (ANDI): Was missing mipsIV model, fix assembler syntax.
1255 (do_c_cond_fmt): New function.
1256 (C.cond.fmt): Handle mips I-III which do not support CC field
1258 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1259 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1261 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1262 vr5000 which saves LO in a GPR separatly.
1264 * configure.in (enable-sim-igen): For vr5000, select vr5000
1265 specific instructions.
1266 * configure: Re-generate.
1268 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1270 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1272 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1273 fmt_uninterpreted_64 bit cases to switch. Convert to
1276 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1278 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1279 as specified in IV3.2 spec.
1280 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1282 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1284 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1285 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1286 (start-sanitize-r5900):
1287 (LWXC1, SWXC1): Delete from r5900 instruction set.
1288 (end-sanitize-r5900):
1289 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1290 PENDING_FILL versions of instructions. Simplify.
1292 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1294 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1296 (MTHI, MFHI): Disable code checking HI-LO.
1298 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1300 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1302 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1304 * gencode.c (build_mips16_operands): Replace IPC with cia.
1306 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1307 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1309 (UndefinedResult): Replace function with macro/function
1311 (sim_engine_run): Don't save PC in IPC.
1313 * sim-main.h (IPC): Delete.
1315 start-sanitize-cygnus
1316 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1317 (do_select): Rename function select.
1320 * interp.c (signal_exception, store_word, load_word,
1321 address_translation, load_memory, store_memory, cache_op,
1322 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1323 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1324 current instruction address - cia - argument.
1325 (sim_read, sim_write): Call address_translation directly.
1326 (sim_engine_run): Rename variable vaddr to cia.
1327 (signal_exception): Pass cia to sim_monitor
1329 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1330 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1331 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1333 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1334 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1337 * interp.c (signal_exception): Pass restart address to
1340 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1341 idecode.o): Add dependency.
1343 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1345 (DELAY_SLOT): Update NIA not PC with branch address.
1346 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1348 * mips.igen: Use CIA not PC in branch calculations.
1349 (illegal): Call SignalException.
1350 (BEQ, ADDIU): Fix assembler.
1352 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1354 * m16.igen (JALX): Was missing.
1356 * configure.in (enable-sim-igen): New configuration option.
1357 * configure: Re-generate.
1359 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1361 * interp.c (load_memory, store_memory): Delete parameter RAW.
1362 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1363 bypassing {load,store}_memory.
1365 * sim-main.h (ByteSwapMem): Delete definition.
1367 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1369 * interp.c (sim_do_command, sim_commands): Delete mips specific
1370 commands. Handled by module sim-options.
1372 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1373 (WITH_MODULO_MEMORY): Define.
1375 * interp.c (sim_info): Delete code printing memory size.
1377 * interp.c (mips_size): Nee sim_size, delete function.
1379 (monitor, monitor_base, monitor_size): Delete global variables.
1380 (sim_open, sim_close): Delete code creating monitor and other
1381 memory regions. Use sim-memopts module, via sim_do_commandf, to
1382 manage memory regions.
1383 (load_memory, store_memory): Use sim-core for memory model.
1385 * interp.c (address_translation): Delete all memory map code
1386 except line forcing 32 bit addresses.
1388 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1390 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1393 * interp.c (logfh, logfile): Delete globals.
1394 (sim_open, sim_close): Delete code opening & closing log file.
1395 (mips_option_handler): Delete -l and -n options.
1396 (OPTION mips_options): Ditto.
1398 * interp.c (OPTION mips_options): Rename option trace to dinero.
1399 (mips_option_handler): Update.
1401 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1403 * interp.c (fetch_str): New function.
1404 (sim_monitor): Rewrite using sim_read & sim_write.
1405 (sim_open): Check magic number.
1406 (sim_open): Write monitor vectors into memory using sim_write.
1407 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1408 (sim_read, sim_write): Simplify - transfer data one byte at a
1410 (load_memory, store_memory): Clarify meaning of parameter RAW.
1412 * sim-main.h (isHOST): Defete definition.
1413 (isTARGET): Mark as depreciated.
1414 (address_translation): Delete parameter HOST.
1416 * interp.c (address_translation): Delete parameter HOST.
1419 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1421 * gencode.c: Add tx49 configury and insns.
1422 * configure.in: Add tx49 configury.
1423 * configure: Update.
1426 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1430 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1431 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1433 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1435 * mips.igen: Add model filter field to records.
1437 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1439 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1441 interp.c (sim_engine_run): Do not compile function sim_engine_run
1442 when WITH_IGEN == 1.
1444 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1445 target architecture.
1447 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1448 igen. Replace with configuration variables sim_igen_flags /
1451 start-sanitize-r5900
1452 * r5900.igen: New file. Copy r5900 insns here.
1454 start-sanitize-cygnus
1455 * vr5400.igen: New file.
1457 * m16.igen: New file. Copy mips16 insns here.
1458 * mips.igen: From here.
1460 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1462 start-sanitize-cygnus
1463 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1465 * configure.in: Add mips64vr5400 target.
1466 * configure: Re-generate.
1469 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1471 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1473 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1475 * gencode.c (build_instruction): Follow sim_write's lead in using
1476 BigEndianMem instead of !ByteSwapMem.
1478 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1480 * configure.in (sim_gen): Dependent on target, select type of
1481 generator. Always select old style generator.
1483 configure: Re-generate.
1485 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1487 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1488 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1489 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1490 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1491 SIM_@sim_gen@_*, set by autoconf.
1493 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1495 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1497 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1498 CURRENT_FLOATING_POINT instead.
1500 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1501 (address_translation): Raise exception InstructionFetch when
1502 translation fails and isINSTRUCTION.
1504 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1505 sim_engine_run): Change type of of vaddr and paddr to
1507 (address_translation, prefetch, load_memory, store_memory,
1508 cache_op): Change type of vAddr and pAddr to address_word.
1510 * gencode.c (build_instruction): Change type of vaddr and paddr to
1513 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1515 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1516 macro to obtain result of ALU op.
1518 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1520 * interp.c (sim_info): Call profile_print.
1522 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1524 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1526 * sim-main.h (WITH_PROFILE): Do not define, defined in
1527 common/sim-config.h. Use sim-profile module.
1528 (simPROFILE): Delete defintion.
1530 * interp.c (PROFILE): Delete definition.
1531 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1532 (sim_close): Delete code writing profile histogram.
1533 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1535 (sim_engine_run): Delete code profiling the PC.
1537 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1539 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1541 * interp.c (sim_monitor): Make register pointers of type
1544 * sim-main.h: Make registers of type unsigned_word not
1547 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1549 start-sanitize-r5900
1550 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1551 ...): Move to sim-main.h
1554 * interp.c (sync_operation): Rename from SyncOperation, make
1555 global, add SD argument.
1556 (prefetch): Rename from Prefetch, make global, add SD argument.
1557 (decode_coproc): Make global.
1559 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1561 * gencode.c (build_instruction): Generate DecodeCoproc not
1562 decode_coproc calls.
1564 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1565 (SizeFGR): Move to sim-main.h
1566 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1567 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1568 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1570 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1571 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1572 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1573 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1574 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1575 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1577 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1579 (sim-alu.h): Include.
1580 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1581 (sim_cia): Typedef to instruction_address.
1583 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1585 * Makefile.in (interp.o): Rename generated file engine.c to
1590 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1592 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1594 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1596 * gencode.c (build_instruction): For "FPSQRT", output correct
1597 number of arguments to Recip.
1599 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601 * Makefile.in (interp.o): Depends on sim-main.h
1603 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1605 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1606 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1607 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1608 STATE, DSSTATE): Define
1609 (GPR, FGRIDX, ..): Define.
1611 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1612 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1613 (GPR, FGRIDX, ...): Delete macros.
1615 * interp.c: Update names to match defines from sim-main.h
1617 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1619 * interp.c (sim_monitor): Add SD argument.
1620 (sim_warning): Delete. Replace calls with calls to
1622 (sim_error): Delete. Replace calls with sim_io_error.
1623 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1624 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1625 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1627 (mips_size): Rename from sim_size. Add SD argument.
1629 * interp.c (simulator): Delete global variable.
1630 (callback): Delete global variable.
1631 (mips_option_handler, sim_open, sim_write, sim_read,
1632 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1633 sim_size,sim_monitor): Use sim_io_* not callback->*.
1634 (sim_open): ZALLOC simulator struct.
1635 (PROFILE): Do not define.
1637 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1639 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1640 support.h with corresponding code.
1642 * sim-main.h (word64, uword64), support.h: Move definition to
1644 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1647 * Makefile.in: Update dependencies
1648 * interp.c: Do not include.
1650 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1652 * interp.c (address_translation, load_memory, store_memory,
1653 cache_op): Rename to from AddressTranslation et.al., make global,
1656 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1659 * interp.c (SignalException): Rename to signal_exception, make
1662 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1664 * sim-main.h (SignalException, SignalExceptionInterrupt,
1665 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1666 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1667 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1670 * interp.c, support.h: Use.
1672 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1674 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1675 to value_fpr / store_fpr. Add SD argument.
1676 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1677 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1679 * sim-main.h (ValueFPR, StoreFPR): Define.
1681 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1683 * interp.c (sim_engine_run): Check consistency between configure
1684 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1687 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1688 (mips_fpu): Configure WITH_FLOATING_POINT.
1689 (mips_endian): Configure WITH_TARGET_ENDIAN.
1690 * configure: Update.
1692 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1694 * configure: Regenerated to track ../common/aclocal.m4 changes.
1696 start-sanitize-r5900
1697 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1699 * interp.c (MAX_REG): Allow up-to 128 registers.
1700 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1701 (REGISTER_SA): Ditto.
1702 (sim_open): Initialize register_widths for r5900 specific
1704 (sim_fetch_register, sim_store_register): Check for request of
1705 r5900 specific SA register. Check for request for hi 64 bits of
1706 r5900 specific registers.
1709 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1711 * configure: Regenerated.
1713 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1715 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1717 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1719 * gencode.c (print_igen_insn_models): Assume certain architectures
1720 include all mips* instructions.
1721 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1724 * Makefile.in (tmp.igen): Add target. Generate igen input from
1727 * gencode.c (FEATURE_IGEN): Define.
1728 (main): Add --igen option. Generate output in igen format.
1729 (process_instructions): Format output according to igen option.
1730 (print_igen_insn_format): New function.
1731 (print_igen_insn_models): New function.
1732 (process_instructions): Only issue warnings and ignore
1733 instructions when no FEATURE_IGEN.
1735 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1737 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1740 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1742 * configure: Regenerated to track ../common/aclocal.m4 changes.
1744 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1746 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1747 SIM_RESERVED_BITS): Delete, moved to common.
1748 (SIM_EXTRA_CFLAGS): Update.
1750 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1752 * configure.in: Configure non-strict memory alignment.
1753 * configure: Regenerated to track ../common/aclocal.m4 changes.
1755 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1757 * configure: Regenerated to track ../common/aclocal.m4 changes.
1759 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1761 * gencode.c (SDBBP,DERET): Added (3900) insns.
1762 (RFE): Turn on for 3900.
1763 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1764 (dsstate): Made global.
1765 (SUBTARGET_R3900): Added.
1766 (CANCELDELAYSLOT): New.
1767 (SignalException): Ignore SystemCall rather than ignore and
1768 terminate. Add DebugBreakPoint handling.
1769 (decode_coproc): New insns RFE, DERET; and new registers Debug
1770 and DEPC protected by SUBTARGET_R3900.
1771 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1773 * Makefile.in,configure.in: Add mips subtarget option.
1774 * configure: Update.
1776 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1778 * gencode.c: Add r3900 (tx39).
1781 * gencode.c: Fix some configuration problems by improving
1782 the relationship between tx19 and tx39.
1785 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1787 * gencode.c (build_instruction): Don't need to subtract 4 for
1790 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1792 * interp.c: Correct some HASFPU problems.
1794 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1796 * configure: Regenerated to track ../common/aclocal.m4 changes.
1798 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1800 * interp.c (mips_options): Fix samples option short form, should
1803 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1805 * interp.c (sim_info): Enable info code. Was just returning.
1807 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1809 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1812 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1814 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1816 (build_instruction): Ditto for LL.
1819 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1821 * mips/configure.in, mips/gencode: Add tx19/r1900.
1824 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1826 * configure: Regenerated to track ../common/aclocal.m4 changes.
1828 start-sanitize-r5900
1829 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1831 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1832 for overflow due to ABS of MININT, set result to MAXINT.
1833 (build_instruction): For "psrlvw", signextend bit 31.
1836 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1838 * configure: Regenerated to track ../common/aclocal.m4 changes.
1841 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1843 * interp.c (sim_open): Add call to sim_analyze_program, update
1846 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1848 * interp.c (sim_kill): Delete.
1849 (sim_create_inferior): Add ABFD argument. Set PC from same.
1850 (sim_load): Move code initializing trap handlers from here.
1851 (sim_open): To here.
1852 (sim_load): Delete, use sim-hload.c.
1854 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1856 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1858 * configure: Regenerated to track ../common/aclocal.m4 changes.
1861 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1863 * interp.c (sim_open): Add ABFD argument.
1864 (sim_load): Move call to sim_config from here.
1865 (sim_open): To here. Check return status.
1867 start-sanitize-r5900
1868 * gencode.c (build_instruction): Do not define x8000000000000000,
1869 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1872 start-sanitize-r5900
1873 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1875 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1876 "pdivuw" check for overflow due to signed divide by -1.
1879 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1881 * gencode.c (build_instruction): Two arg MADD should
1882 not assign result to $0.
1884 start-sanitize-r5900
1885 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1887 * gencode.c (build_instruction): For "ppac5" use unsigned
1888 arrithmetic so that the sign bit doesn't smear when right shifted.
1889 (build_instruction): For "pdiv" perform sign extension when
1890 storing results in HI and LO.
1891 (build_instructions): For "pdiv" and "pdivbw" check for
1893 (build_instruction): For "pmfhl.slw" update hi part of dest
1894 register as well as low part.
1895 (build_instruction): For "pmfhl" portably handle long long values.
1896 (build_instruction): For "pmfhl.sh" correctly negative values.
1897 Store half words 2 and three in the correct place.
1898 (build_instruction): For "psllvw", sign extend value after shift.
1901 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1903 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1904 * sim/mips/configure.in: Regenerate.
1906 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1908 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1909 signed8, unsigned8 et.al. types.
1911 start-sanitize-r5900
1912 * gencode.c (build_instruction): For PMULTU* do not sign extend
1913 registers. Make generated code easier to debug.
1916 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1917 hosts when selecting subreg.
1919 start-sanitize-r5900
1920 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1922 * gencode.c (type_for_data_len): For 32bit operations concerned
1923 with overflow, perform op using 64bits.
1924 (build_instruction): For PADD, always compute operation using type
1925 returned by type_for_data_len.
1926 (build_instruction): For PSUBU, when overflow, saturate to zero as
1930 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1932 start-sanitize-r5900
1933 * gencode.c (build_instruction): Handle "pext5" according to
1934 version 1.95 of the r5900 ISA.
1936 * gencode.c (build_instruction): Handle "ppac5" according to
1937 version 1.95 of the r5900 ISA.
1940 * interp.c (sim_engine_run): Reset the ZERO register to zero
1941 regardless of FEATURE_WARN_ZERO.
1942 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1944 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1946 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1947 (SignalException): For BreakPoints ignore any mode bits and just
1949 (SignalException): Always set the CAUSE register.
1951 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1953 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1954 exception has been taken.
1956 * interp.c: Implement the ERET and mt/f sr instructions.
1958 start-sanitize-r5900
1959 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1961 * gencode.c (build_instruction): For paddu, extract unsigned
1964 * gencode.c (build_instruction): Saturate padds instead of padd
1968 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1970 * interp.c (SignalException): Don't bother restarting an
1973 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1975 * interp.c (SignalException): Really take an interrupt.
1976 (interrupt_event): Only deliver interrupts when enabled.
1978 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1980 * interp.c (sim_info): Only print info when verbose.
1981 (sim_info) Use sim_io_printf for output.
1983 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1985 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1988 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1990 * interp.c (sim_do_command): Check for common commands if a
1991 simulator specific command fails.
1993 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1995 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1996 and simBE when DEBUG is defined.
1998 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2000 * interp.c (interrupt_event): New function. Pass exception event
2001 onto exception handler.
2003 * configure.in: Check for stdlib.h.
2004 * configure: Regenerate.
2006 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2007 variable declaration.
2008 (build_instruction): Initialize memval1.
2009 (build_instruction): Add UNUSED attribute to byte, bigend,
2011 (build_operands): Ditto.
2013 * interp.c: Fix GCC warnings.
2014 (sim_get_quit_code): Delete.
2016 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2017 * Makefile.in: Ditto.
2018 * configure: Re-generate.
2020 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2022 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2024 * interp.c (mips_option_handler): New function parse argumes using
2026 (myname): Replace with STATE_MY_NAME.
2027 (sim_open): Delete check for host endianness - performed by
2029 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2030 (sim_open): Move much of the initialization from here.
2031 (sim_load): To here. After the image has been loaded and
2033 (sim_open): Move ColdReset from here.
2034 (sim_create_inferior): To here.
2035 (sim_open): Make FP check less dependant on host endianness.
2037 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2039 * interp.c (sim_set_callbacks): Delete.
2041 * interp.c (membank, membank_base, membank_size): Replace with
2042 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2043 (sim_open): Remove call to callback->init. gdb/run do this.
2047 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2049 * interp.c (big_endian_p): Delete, replaced by
2050 current_target_byte_order.
2052 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2054 * interp.c (host_read_long, host_read_word, host_swap_word,
2055 host_swap_long): Delete. Using common sim-endian.
2056 (sim_fetch_register, sim_store_register): Use H2T.
2057 (pipeline_ticks): Delete. Handled by sim-events.
2059 (sim_engine_run): Update.
2061 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2063 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2065 (SignalException): To here. Signal using sim_engine_halt.
2066 (sim_stop_reason): Delete, moved to common.
2068 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2070 * interp.c (sim_open): Add callback argument.
2071 (sim_set_callbacks): Delete SIM_DESC argument.
2074 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2076 * Makefile.in (SIM_OBJS): Add common modules.
2078 * interp.c (sim_set_callbacks): Also set SD callback.
2079 (set_endianness, xfer_*, swap_*): Delete.
2080 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2081 Change to functions using sim-endian macros.
2082 (control_c, sim_stop): Delete, use common version.
2083 (simulate): Convert into.
2084 (sim_engine_run): This function.
2085 (sim_resume): Delete.
2087 * interp.c (simulation): New variable - the simulator object.
2088 (sim_kind): Delete global - merged into simulation.
2089 (sim_load): Cleanup. Move PC assignment from here.
2090 (sim_create_inferior): To here.
2092 * sim-main.h: New file.
2093 * interp.c (sim-main.h): Include.
2095 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2097 * configure: Regenerated to track ../common/aclocal.m4 changes.
2099 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2101 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2103 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2105 * gencode.c (build_instruction): DIV instructions: check
2106 for division by zero and integer overflow before using
2107 host's division operation.
2109 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2111 * Makefile.in (SIM_OBJS): Add sim-load.o.
2112 * interp.c: #include bfd.h.
2113 (target_byte_order): Delete.
2114 (sim_kind, myname, big_endian_p): New static locals.
2115 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2116 after argument parsing. Recognize -E arg, set endianness accordingly.
2117 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2118 load file into simulator. Set PC from bfd.
2119 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2120 (set_endianness): Use big_endian_p instead of target_byte_order.
2122 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2124 * interp.c (sim_size): Delete prototype - conflicts with
2125 definition in remote-sim.h. Correct definition.
2127 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2129 * configure: Regenerated to track ../common/aclocal.m4 changes.
2132 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2134 * interp.c (sim_open): New arg `kind'.
2136 * configure: Regenerated to track ../common/aclocal.m4 changes.
2138 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2140 * configure: Regenerated to track ../common/aclocal.m4 changes.
2142 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2144 * interp.c (sim_open): Set optind to 0 before calling getopt.
2146 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2148 * configure: Regenerated to track ../common/aclocal.m4 changes.
2150 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2152 * interp.c : Replace uses of pr_addr with pr_uword64
2153 where the bit length is always 64 independent of SIM_ADDR.
2154 (pr_uword64) : added.
2156 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2158 * configure: Re-generate.
2160 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2162 * configure: Regenerate to track ../common/aclocal.m4 changes.
2164 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2166 * interp.c (sim_open): New SIM_DESC result. Argument is now
2168 (other sim_*): New SIM_DESC argument.
2170 start-sanitize-r5900
2171 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
2173 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2174 Change values to avoid overloading DOUBLEWORD which is tested
2176 * gencode.c: reinstate "offending code".
2179 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2181 * interp.c: Fix printing of addresses for non-64-bit targets.
2182 (pr_addr): Add function to print address based on size.
2183 start-sanitize-r5900
2184 * gencode.c: #ifdef out offending code until a permanent fix
2185 can be added. Code is causing build errors for non-5900 mips targets.
2188 start-sanitize-r5900
2189 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
2191 * gencode.c (process_instructions): Correct test for ISA dependent
2192 architecture bits in isa field of MIPS_DECODE.
2195 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2197 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2199 start-sanitize-r5900
2200 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2202 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2206 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2208 * gencode.c (build_mips16_operands): Correct computation of base
2209 address for extended PC relative instruction.
2211 start-sanitize-r5900
2212 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2214 * Makefile.in, configure, configure.in, gencode.c,
2215 interp.c, support.h: add r5900.
2218 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2220 * interp.c (mips16_entry): Add support for floating point cases.
2221 (SignalException): Pass floating point cases to mips16_entry.
2222 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2224 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2226 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2227 and then set the state to fmt_uninterpreted.
2228 (COP_SW): Temporarily set the state to fmt_word while calling
2231 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2233 * gencode.c (build_instruction): The high order may be set in the
2234 comparison flags at any ISA level, not just ISA 4.
2236 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2238 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2239 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2240 * configure.in: sinclude ../common/aclocal.m4.
2241 * configure: Regenerated.
2243 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2245 * configure: Rebuild after change to aclocal.m4.
2247 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2249 * configure configure.in Makefile.in: Update to new configure
2250 scheme which is more compatible with WinGDB builds.
2251 * configure.in: Improve comment on how to run autoconf.
2252 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2253 * Makefile.in: Use autoconf substitution to install common
2256 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2258 * gencode.c (build_instruction): Use BigEndianCPU instead of
2261 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2263 * interp.c (sim_monitor): Make output to stdout visible in
2264 wingdb's I/O log window.
2266 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2268 * support.h: Undo previous change to SIGTRAP
2271 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2273 * interp.c (store_word, load_word): New static functions.
2274 (mips16_entry): New static function.
2275 (SignalException): Look for mips16 entry and exit instructions.
2276 (simulate): Use the correct index when setting fpr_state after
2277 doing a pending move.
2279 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2281 * interp.c: Fix byte-swapping code throughout to work on
2282 both little- and big-endian hosts.
2284 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2286 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2287 with gdb/config/i386/xm-windows.h.
2289 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2291 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2292 that messes up arithmetic shifts.
2294 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2296 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2297 SIGTRAP and SIGQUIT for _WIN32.
2299 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2301 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2302 force a 64 bit multiplication.
2303 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2304 destination register is 0, since that is the default mips16 nop
2307 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2309 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2310 (build_endian_shift): Don't check proc64.
2311 (build_instruction): Always set memval to uword64. Cast op2 to
2312 uword64 when shifting it left in memory instructions. Always use
2313 the same code for stores--don't special case proc64.
2315 * gencode.c (build_mips16_operands): Fix base PC value for PC
2317 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2319 * interp.c (simJALDELAYSLOT): Define.
2320 (JALDELAYSLOT): Define.
2321 (INDELAYSLOT, INJALDELAYSLOT): Define.
2322 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2324 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2326 * interp.c (sim_open): add flush_cache as a PMON routine
2327 (sim_monitor): handle flush_cache by ignoring it
2329 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2331 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2333 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2334 (BigEndianMem): Rename to ByteSwapMem and change sense.
2335 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2336 BigEndianMem references to !ByteSwapMem.
2337 (set_endianness): New function, with prototype.
2338 (sim_open): Call set_endianness.
2339 (sim_info): Use simBE instead of BigEndianMem.
2340 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2341 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2342 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2343 ifdefs, keeping the prototype declaration.
2344 (swap_word): Rewrite correctly.
2345 (ColdReset): Delete references to CONFIG. Delete endianness related
2346 code; moved to set_endianness.
2348 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2350 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2351 * interp.c (CHECKHILO): Define away.
2352 (simSIGINT): New macro.
2353 (membank_size): Increase from 1MB to 2MB.
2354 (control_c): New function.
2355 (sim_resume): Rename parameter signal to signal_number. Add local
2356 variable prev. Call signal before and after simulate.
2357 (sim_stop_reason): Add simSIGINT support.
2358 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2360 (sim_warning): Delete call to SignalException. Do call printf_filtered
2362 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2363 a call to sim_warning.
2365 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2367 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2368 16 bit instructions.
2370 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2372 Add support for mips16 (16 bit MIPS implementation):
2373 * gencode.c (inst_type): Add mips16 instruction encoding types.
2374 (GETDATASIZEINSN): Define.
2375 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2376 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2378 (MIPS16_DECODE): New table, for mips16 instructions.
2379 (bitmap_val): New static function.
2380 (struct mips16_op): Define.
2381 (mips16_op_table): New table, for mips16 operands.
2382 (build_mips16_operands): New static function.
2383 (process_instructions): If PC is odd, decode a mips16
2384 instruction. Break out instruction handling into new
2385 build_instruction function.
2386 (build_instruction): New static function, broken out of
2387 process_instructions. Check modifiers rather than flags for SHIFT
2388 bit count and m[ft]{hi,lo} direction.
2389 (usage): Pass program name to fprintf.
2390 (main): Remove unused variable this_option_optind. Change
2391 ``*loptarg++'' to ``loptarg++''.
2392 (my_strtoul): Parenthesize && within ||.
2393 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2394 (simulate): If PC is odd, fetch a 16 bit instruction, and
2395 increment PC by 2 rather than 4.
2396 * configure.in: Add case for mips16*-*-*.
2397 * configure: Rebuild.
2399 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2401 * interp.c: Allow -t to enable tracing in standalone simulator.
2402 Fix garbage output in trace file and error messages.
2404 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2406 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2407 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2408 * configure.in: Simplify using macros in ../common/aclocal.m4.
2409 * configure: Regenerated.
2410 * tconfig.in: New file.
2412 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2414 * interp.c: Fix bugs in 64-bit port.
2415 Use ansi function declarations for msvc compiler.
2416 Initialize and test file pointer in trace code.
2417 Prevent duplicate definition of LAST_EMED_REGNUM.
2419 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2421 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2423 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2425 * interp.c (SignalException): Check for explicit terminating
2427 * gencode.c: Pass instruction value through SignalException()
2428 calls for Trap, Breakpoint and Syscall.
2430 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2432 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2433 only used on those hosts that provide it.
2434 * configure.in: Add sqrt() to list of functions to be checked for.
2435 * config.in: Re-generated.
2436 * configure: Re-generated.
2438 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2440 * gencode.c (process_instructions): Call build_endian_shift when
2441 expanding STORE RIGHT, to fix swr.
2442 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2443 clear the high bits.
2444 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2445 Fix float to int conversions to produce signed values.
2447 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2449 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2450 (process_instructions): Correct handling of nor instruction.
2451 Correct shift count for 32 bit shift instructions. Correct sign
2452 extension for arithmetic shifts to not shift the number of bits in
2453 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2454 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2456 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2457 It's OK to have a mult follow a mult. What's not OK is to have a
2458 mult follow an mfhi.
2459 (Convert): Comment out incorrect rounding code.
2461 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2463 * interp.c (sim_monitor): Improved monitor printf
2464 simulation. Tidied up simulator warnings, and added "--log" option
2465 for directing warning message output.
2466 * gencode.c: Use sim_warning() rather than WARNING macro.
2468 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2470 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2471 getopt1.o, rather than on gencode.c. Link objects together.
2472 Don't link against -liberty.
2473 (gencode.o, getopt.o, getopt1.o): New targets.
2474 * gencode.c: Include <ctype.h> and "ansidecl.h".
2475 (AND): Undefine after including "ansidecl.h".
2476 (ULONG_MAX): Define if not defined.
2477 (OP_*): Don't define macros; now defined in opcode/mips.h.
2478 (main): Call my_strtoul rather than strtoul.
2479 (my_strtoul): New static function.
2481 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2483 * gencode.c (process_instructions): Generate word64 and uword64
2484 instead of `long long' and `unsigned long long' data types.
2485 * interp.c: #include sysdep.h to get signals, and define default
2487 * (Convert): Work around for Visual-C++ compiler bug with type
2489 * support.h: Make things compile under Visual-C++ by using
2490 __int64 instead of `long long'. Change many refs to long long
2491 into word64/uword64 typedefs.
2493 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2495 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2496 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2498 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2499 (AC_PROG_INSTALL): Added.
2500 (AC_PROG_CC): Moved to before configure.host call.
2501 * configure: Rebuilt.
2503 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2505 * configure.in: Define @SIMCONF@ depending on mips target.
2506 * configure: Rebuild.
2507 * Makefile.in (run): Add @SIMCONF@ to control simulator
2509 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2510 * interp.c: Remove some debugging, provide more detailed error
2511 messages, update memory accesses to use LOADDRMASK.
2513 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2515 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2516 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2518 * configure: Rebuild.
2519 * config.in: New file, generated by autoheader.
2520 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2521 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2522 HAVE_ANINT and HAVE_AINT, as appropriate.
2523 * Makefile.in (run): Use @LIBS@ rather than -lm.
2524 (interp.o): Depend upon config.h.
2525 (Makefile): Just rebuild Makefile.
2526 (clean): Remove stamp-h.
2527 (mostlyclean): Make the same as clean, not as distclean.
2528 (config.h, stamp-h): New targets.
2530 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2532 * interp.c (ColdReset): Fix boolean test. Make all simulator
2535 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2537 * interp.c (xfer_direct_word, xfer_direct_long,
2538 swap_direct_word, swap_direct_long, xfer_big_word,
2539 xfer_big_long, xfer_little_word, xfer_little_long,
2540 swap_word,swap_long): Added.
2541 * interp.c (ColdReset): Provide function indirection to
2542 host<->simulated_target transfer routines.
2543 * interp.c (sim_store_register, sim_fetch_register): Updated to
2544 make use of indirected transfer routines.
2546 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2548 * gencode.c (process_instructions): Ensure FP ABS instruction
2550 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2551 system call support.
2553 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2555 * interp.c (sim_do_command): Complain if callback structure not
2558 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2560 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2561 support for Sun hosts.
2562 * Makefile.in (gencode): Ensure the host compiler and libraries
2563 used for cross-hosted build.
2565 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2567 * interp.c, gencode.c: Some more (TODO) tidying.
2569 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2571 * gencode.c, interp.c: Replaced explicit long long references with
2572 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2573 * support.h (SET64LO, SET64HI): Macros added.
2575 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2577 * configure: Regenerate with autoconf 2.7.
2579 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2581 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2582 * support.h: Remove superfluous "1" from #if.
2583 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2585 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2587 * interp.c (StoreFPR): Control UndefinedResult() call on
2588 WARN_RESULT manifest.
2590 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2592 * gencode.c: Tidied instruction decoding, and added FP instruction
2595 * interp.c: Added dineroIII, and BSD profiling support. Also
2596 run-time FP handling.
2598 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2600 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2601 gencode.c, interp.c, support.h: created.