1 2002-06-12 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (X): Delete unused function.
5 2002-06-08 Andrew Cagney <cagney@redhat.com>
7 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
9 2002-06-07 Chris Demetriou <cgd@broadcom.com>
10 Ed Satterthwaite <ehs@broadcom.com>
12 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
13 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
14 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
15 (fp_nmsub): New prototypes.
16 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
17 (NegMultiplySub): New defines.
18 * mips.igen (RSQRT.fmt): Use RSquareRoot().
19 (MADD.D, MADD.S): Replace with...
20 (MADD.fmt): New instruction.
21 (MSUB.D, MSUB.S): Replace with...
22 (MSUB.fmt): New instruction.
23 (NMADD.D, NMADD.S): Replace with...
24 (NMADD.fmt): New instruction.
25 (NMSUB.D, MSUB.S): Replace with...
26 (NMSUB.fmt): New instruction.
28 2002-06-07 Chris Demetriou <cgd@broadcom.com>
29 Ed Satterthwaite <ehs@broadcom.com>
31 * cp1.c: Fix more comment spelling and formatting.
32 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
33 (denorm_mode): New function.
34 (fpu_unary, fpu_binary): Round results after operation, collect
35 status from rounding operations, and update the FCSR.
36 (convert): Collect status from integer conversions and rounding
37 operations, and update the FCSR. Adjust NaN values that result
38 from conversions. Convert to use sim_io_eprintf rather than
39 fprintf, and remove some debugging code.
40 * cp1.h (fenr_FS): New define.
42 2002-06-07 Chris Demetriou <cgd@broadcom.com>
44 * cp1.c (convert): Remove unusable debugging code, and move MIPS
45 rounding mode to sim FP rounding mode flag conversion code into...
46 (rounding_mode): New function.
48 2002-06-07 Chris Demetriou <cgd@broadcom.com>
50 * cp1.c: Clean up formatting of a few comments.
51 (value_fpr): Reformat switch statement.
53 2002-06-06 Chris Demetriou <cgd@broadcom.com>
54 Ed Satterthwaite <ehs@broadcom.com>
57 * sim-main.h: Include cp1.h.
58 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
59 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
60 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
61 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
62 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
63 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
64 * cp1.c: Don't include sim-fpu.h; already included by
65 sim-main.h. Clean up formatting of some comments.
66 (NaN, Equal, Less): Remove.
67 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
68 (fp_cmp): New functions.
69 * mips.igen (do_c_cond_fmt): Remove.
70 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
71 Compare. Add result tracing.
72 (CxC1): Remove, replace with...
73 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
74 (DMxC1): Remove, replace with...
75 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
76 (MxC1): Remove, replace with...
77 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
79 2002-06-04 Chris Demetriou <cgd@broadcom.com>
81 * sim-main.h (FGRIDX): Remove, replace all uses with...
82 (FGR_BASE): New macro.
83 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
84 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
85 (NR_FGR, FGR): Likewise.
86 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
87 * mips.igen: Likewise.
89 2002-06-04 Chris Demetriou <cgd@broadcom.com>
91 * cp1.c: Add an FSF Copyright notice to this file.
93 2002-06-04 Chris Demetriou <cgd@broadcom.com>
94 Ed Satterthwaite <ehs@broadcom.com>
96 * cp1.c (Infinity): Remove.
97 * sim-main.h (Infinity): Likewise.
99 * cp1.c (fp_unary, fp_binary): New functions.
100 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
101 (fp_sqrt): New functions, implemented in terms of the above.
102 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
103 (Recip, SquareRoot): Remove (replaced by functions above).
104 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
105 (fp_recip, fp_sqrt): New prototypes.
106 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
107 (Recip, SquareRoot): Replace prototypes with #defines which
108 invoke the functions above.
110 2002-06-03 Chris Demetriou <cgd@broadcom.com>
112 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
113 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
114 file, remove PARAMS from prototypes.
115 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
116 simulator state arguments.
117 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
118 pass simulator state arguments.
119 * cp1.c (SD): Redefine as CPU_STATE(cpu).
120 (store_fpr, convert): Remove 'sd' argument.
121 (value_fpr): Likewise. Convert to use 'SD' instead.
123 2002-06-03 Chris Demetriou <cgd@broadcom.com>
125 * cp1.c (Min, Max): Remove #if 0'd functions.
126 * sim-main.h (Min, Max): Remove.
128 2002-06-03 Chris Demetriou <cgd@broadcom.com>
130 * cp1.c: fix formatting of switch case and default labels.
131 * interp.c: Likewise.
132 * sim-main.c: Likewise.
134 2002-06-03 Chris Demetriou <cgd@broadcom.com>
136 * cp1.c: Clean up comments which describe FP formats.
137 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
139 2002-06-03 Chris Demetriou <cgd@broadcom.com>
140 Ed Satterthwaite <ehs@broadcom.com>
142 * configure.in (mipsisa64sb1*-*-*): New target for supporting
143 Broadcom SiByte SB-1 processor configurations.
144 * configure: Regenerate.
145 * sb1.igen: New file.
146 * mips.igen: Include sb1.igen.
148 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
149 * mdmx.igen: Add "sb1" model to all appropriate functions and
151 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
152 (ob_func, ob_acc): Reference the above.
153 (qh_acc): Adjust to keep the same size as ob_acc.
154 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
155 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
157 2002-06-03 Chris Demetriou <cgd@broadcom.com>
159 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
161 2002-06-02 Chris Demetriou <cgd@broadcom.com>
162 Ed Satterthwaite <ehs@broadcom.com>
164 * mips.igen (mdmx): New (pseudo-)model.
165 * mdmx.c, mdmx.igen: New files.
166 * Makefile.in (SIM_OBJS): Add mdmx.o.
167 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
169 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
170 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
171 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
172 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
173 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
174 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
175 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
176 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
177 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
178 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
179 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
180 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
181 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
182 (qh_fmtsel): New macros.
183 (_sim_cpu): New member "acc".
184 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
185 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
187 2002-05-01 Chris Demetriou <cgd@broadcom.com>
189 * interp.c: Use 'deprecated' rather than 'depreciated.'
190 * sim-main.h: Likewise.
192 2002-05-01 Chris Demetriou <cgd@broadcom.com>
194 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
195 which wouldn't compile anyway.
196 * sim-main.h (unpredictable_action): New function prototype.
197 (Unpredictable): Define to call igen function unpredictable().
198 (NotWordValue): New macro to call igen function not_word_value().
199 (UndefinedResult): Remove.
200 * interp.c (undefined_result): Remove.
201 (unpredictable_action): New function.
202 * mips.igen (not_word_value, unpredictable): New functions.
203 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
204 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
205 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
206 NotWordValue() to check for unpredictable inputs, then
207 Unpredictable() to handle them.
209 2002-02-24 Chris Demetriou <cgd@broadcom.com>
211 * mips.igen: Fix formatting of calls to Unpredictable().
213 2002-04-20 Andrew Cagney <ac131313@redhat.com>
215 * interp.c (sim_open): Revert previous change.
217 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
219 * interp.c (sim_open): Disable chunk of code that wrote code in
220 vector table entries.
222 2002-03-19 Chris Demetriou <cgd@broadcom.com>
224 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
225 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
228 2002-03-19 Chris Demetriou <cgd@broadcom.com>
230 * cp1.c: Fix many formatting issues.
232 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
234 * cp1.c (fpu_format_name): New function to replace...
235 (DOFMT): This. Delete, and update all callers.
236 (fpu_rounding_mode_name): New function to replace...
237 (RMMODE): This. Delete, and update all callers.
239 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
241 * interp.c: Move FPU support routines from here to...
242 * cp1.c: Here. New file.
243 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
246 2002-03-12 Chris Demetriou <cgd@broadcom.com>
248 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
249 * mips.igen (mips32, mips64): New models, add to all instructions
250 and functions as appropriate.
251 (loadstore_ea, check_u64): New variant for model mips64.
252 (check_fmt_p): New variant for models mipsV and mips64, remove
253 mipsV model marking fro other variant.
256 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
257 for mips32 and mips64.
258 (DCLO, DCLZ): New instructions for mips64.
260 2002-03-07 Chris Demetriou <cgd@broadcom.com>
262 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
263 immediate or code as a hex value with the "%#lx" format.
264 (ANDI): Likewise, and fix printed instruction name.
266 2002-03-05 Chris Demetriou <cgd@broadcom.com>
268 * sim-main.h (UndefinedResult, Unpredictable): New macros
269 which currently do nothing.
271 2002-03-05 Chris Demetriou <cgd@broadcom.com>
273 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
274 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
275 (status_CU3): New definitions.
277 * sim-main.h (ExceptionCause): Add new values for MIPS32
278 and MIPS64: MDMX, MCheck, CacheErr. Update comments
279 for DebugBreakPoint and NMIReset to note their status in
281 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
282 (SignalExceptionCacheErr): New exception macros.
284 2002-03-05 Chris Demetriou <cgd@broadcom.com>
286 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
287 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
289 (SignalExceptionCoProcessorUnusable): Take as argument the
290 unusable coprocessor number.
292 2002-03-05 Chris Demetriou <cgd@broadcom.com>
294 * mips.igen: Fix formatting of all SignalException calls.
296 2002-03-05 Chris Demetriou <cgd@broadcom.com>
298 * sim-main.h (SIGNEXTEND): Remove.
300 2002-03-04 Chris Demetriou <cgd@broadcom.com>
302 * mips.igen: Remove gencode comment from top of file, fix
303 spelling in another comment.
305 2002-03-04 Chris Demetriou <cgd@broadcom.com>
307 * mips.igen (check_fmt, check_fmt_p): New functions to check
308 whether specific floating point formats are usable.
309 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
310 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
311 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
312 Use the new functions.
313 (do_c_cond_fmt): Remove format checks...
314 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
316 2002-03-03 Chris Demetriou <cgd@broadcom.com>
318 * mips.igen: Fix formatting of check_fpu calls.
320 2002-03-03 Chris Demetriou <cgd@broadcom.com>
322 * mips.igen (FLOOR.L.fmt): Store correct destination register.
324 2002-03-03 Chris Demetriou <cgd@broadcom.com>
326 * mips.igen: Remove whitespace at end of lines.
328 2002-03-02 Chris Demetriou <cgd@broadcom.com>
330 * mips.igen (loadstore_ea): New function to do effective
331 address calculations.
332 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
333 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
334 CACHE): Use loadstore_ea to do effective address computations.
336 2002-03-02 Chris Demetriou <cgd@broadcom.com>
338 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
339 * mips.igen (LL, CxC1, MxC1): Likewise.
341 2002-03-02 Chris Demetriou <cgd@broadcom.com>
343 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
344 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
345 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
346 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
347 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
348 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
349 Don't split opcode fields by hand, use the opcode field values
352 2002-03-01 Chris Demetriou <cgd@broadcom.com>
354 * mips.igen (do_divu): Fix spacing.
356 * mips.igen (do_dsllv): Move to be right before DSLLV,
357 to match the rest of the do_<shift> functions.
359 2002-03-01 Chris Demetriou <cgd@broadcom.com>
361 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
362 DSRL32, do_dsrlv): Trace inputs and results.
364 2002-03-01 Chris Demetriou <cgd@broadcom.com>
366 * mips.igen (CACHE): Provide instruction-printing string.
368 * interp.c (signal_exception): Comment tokens after #endif.
370 2002-02-28 Chris Demetriou <cgd@broadcom.com>
372 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
373 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
374 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
375 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
376 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
377 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
378 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
379 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
381 2002-02-28 Chris Demetriou <cgd@broadcom.com>
383 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
384 instruction-printing string.
385 (LWU): Use '64' as the filter flag.
387 2002-02-28 Chris Demetriou <cgd@broadcom.com>
389 * mips.igen (SDXC1): Fix instruction-printing string.
391 2002-02-28 Chris Demetriou <cgd@broadcom.com>
393 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
396 2002-02-27 Chris Demetriou <cgd@broadcom.com>
398 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
401 2002-02-27 Chris Demetriou <cgd@broadcom.com>
403 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
404 add a comma) so that it more closely match the MIPS ISA
405 documentation opcode partitioning.
406 (PREF): Put useful names on opcode fields, and include
407 instruction-printing string.
409 2002-02-27 Chris Demetriou <cgd@broadcom.com>
411 * mips.igen (check_u64): New function which in the future will
412 check whether 64-bit instructions are usable and signal an
413 exception if not. Currently a no-op.
414 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
415 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
416 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
417 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
419 * mips.igen (check_fpu): New function which in the future will
420 check whether FPU instructions are usable and signal an exception
421 if not. Currently a no-op.
422 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
423 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
424 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
425 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
426 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
427 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
428 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
429 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
431 2002-02-27 Chris Demetriou <cgd@broadcom.com>
433 * mips.igen (do_load_left, do_load_right): Move to be immediately
435 (do_store_left, do_store_right): Move to be immediately following
438 2002-02-27 Chris Demetriou <cgd@broadcom.com>
440 * mips.igen (mipsV): New model name. Also, add it to
441 all instructions and functions where it is appropriate.
443 2002-02-18 Chris Demetriou <cgd@broadcom.com>
445 * mips.igen: For all functions and instructions, list model
446 names that support that instruction one per line.
448 2002-02-11 Chris Demetriou <cgd@broadcom.com>
450 * mips.igen: Add some additional comments about supported
451 models, and about which instructions go where.
452 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
453 order as is used in the rest of the file.
455 2002-02-11 Chris Demetriou <cgd@broadcom.com>
457 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
458 indicating that ALU32_END or ALU64_END are there to check
460 (DADD): Likewise, but also remove previous comment about
463 2002-02-10 Chris Demetriou <cgd@broadcom.com>
465 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
466 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
467 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
468 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
469 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
470 fields (i.e., add and move commas) so that they more closely
471 match the MIPS ISA documentation opcode partitioning.
473 2002-02-10 Chris Demetriou <cgd@broadcom.com>
475 * mips.igen (ADDI): Print immediate value.
477 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
478 (SLL): Print "nop" specially, and don't run the code
479 that does the shift for the "nop" case.
481 2001-11-17 Fred Fish <fnf@redhat.com>
483 * sim-main.h (float_operation): Move enum declaration outside
484 of _sim_cpu struct declaration.
486 2001-04-12 Jim Blandy <jimb@redhat.com>
488 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
489 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
491 * sim-main.h (COCIDX): Remove definition; this isn't supported by
492 PENDING_FILL, and you can get the intended effect gracefully by
493 calling PENDING_SCHED directly.
495 2001-02-23 Ben Elliston <bje@redhat.com>
497 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
498 already defined elsewhere.
500 2001-02-19 Ben Elliston <bje@redhat.com>
502 * sim-main.h (sim_monitor): Return an int.
503 * interp.c (sim_monitor): Add return values.
504 (signal_exception): Handle error conditions from sim_monitor.
506 2001-02-08 Ben Elliston <bje@redhat.com>
508 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
509 (store_memory): Likewise, pass cia to sim_core_write*.
511 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
513 On advice from Chris G. Demetriou <cgd@sibyte.com>:
514 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
516 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
518 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
519 * Makefile.in: Don't delete *.igen when cleaning directory.
521 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
523 * m16.igen (break): Call SignalException not sim_engine_halt.
525 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
528 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
530 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
532 * mips.igen (MxC1, DMxC1): Fix printf formatting.
534 2000-05-24 Michael Hayes <mhayes@cygnus.com>
536 * mips.igen (do_dmultx): Fix typo.
538 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
540 * configure: Regenerated to track ../common/aclocal.m4 changes.
542 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
544 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
546 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
548 * sim-main.h (GPR_CLEAR): Define macro.
550 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
552 * interp.c (decode_coproc): Output long using %lx and not %s.
554 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
556 * interp.c (sim_open): Sort & extend dummy memory regions for
557 --board=jmr3904 for eCos.
559 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
561 * configure: Regenerated.
563 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
565 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
566 calls, conditional on the simulator being in verbose mode.
568 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
570 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
571 cache don't get ReservedInstruction traps.
573 1999-11-29 Mark Salter <msalter@cygnus.com>
575 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
576 to clear status bits in sdisr register. This is how the hardware works.
578 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
579 being used by cygmon.
581 1999-11-11 Andrew Haley <aph@cygnus.com>
583 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
586 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
588 * mips.igen (MULT): Correct previous mis-applied patch.
590 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
592 * mips.igen (delayslot32): Handle sequence like
593 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
594 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
595 (MULT): Actually pass the third register...
597 1999-09-03 Mark Salter <msalter@cygnus.com>
599 * interp.c (sim_open): Added more memory aliases for additional
600 hardware being touched by cygmon on jmr3904 board.
602 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
604 * configure: Regenerated to track ../common/aclocal.m4 changes.
606 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
608 * interp.c (sim_store_register): Handle case where client - GDB -
609 specifies that a 4 byte register is 8 bytes in size.
610 (sim_fetch_register): Ditto.
612 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
614 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
615 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
616 (idt_monitor_base): Base address for IDT monitor traps.
617 (pmon_monitor_base): Ditto for PMON.
618 (lsipmon_monitor_base): Ditto for LSI PMON.
619 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
620 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
621 (sim_firmware_command): New function.
622 (mips_option_handler): Call it for OPTION_FIRMWARE.
623 (sim_open): Allocate memory for idt_monitor region. If "--board"
624 option was given, add no monitor by default. Add BREAK hooks only if
625 monitors are also there.
627 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
629 * interp.c (sim_monitor): Flush output before reading input.
631 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
633 * tconfig.in (SIM_HANDLES_LMA): Always define.
635 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
637 From Mark Salter <msalter@cygnus.com>:
638 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
639 (sim_open): Add setup for BSP board.
641 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
643 * mips.igen (MULT, MULTU): Add syntax for two operand version.
644 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
645 them as unimplemented.
647 1999-05-08 Felix Lee <flee@cygnus.com>
649 * configure: Regenerated to track ../common/aclocal.m4 changes.
651 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
653 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
655 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
657 * configure.in: Any mips64vr5*-*-* target should have
658 -DTARGET_ENABLE_FR=1.
659 (default_endian): Any mips64vr*el-*-* target should default to
661 * configure: Re-generate.
663 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
665 * mips.igen (ldl): Extend from _16_, not 32.
667 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
669 * interp.c (sim_store_register): Force registers written to by GDB
670 into an un-interpreted state.
672 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
674 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
675 CPU, start periodic background I/O polls.
676 (tx3904sio_poll): New function: periodic I/O poller.
678 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
680 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
682 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
684 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
687 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
689 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
690 (load_word): Call SIM_CORE_SIGNAL hook on error.
691 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
692 starting. For exception dispatching, pass PC instead of NULL_CIA.
693 (decode_coproc): Use COP0_BADVADDR to store faulting address.
694 * sim-main.h (COP0_BADVADDR): Define.
695 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
696 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
697 (_sim_cpu): Add exc_* fields to store register value snapshots.
698 * mips.igen (*): Replace memory-related SignalException* calls
699 with references to SIM_CORE_SIGNAL hook.
701 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
703 * sim-main.c (*): Minor warning cleanups.
705 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
707 * m16.igen (DADDIU5): Correct type-o.
709 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
711 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
714 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
716 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
718 (interp.o): Add dependency on itable.h
719 (oengine.c, gencode): Delete remaining references.
720 (BUILT_SRC_FROM_GEN): Clean up.
722 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
725 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
726 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
728 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
729 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
730 Drop the "64" qualifier to get the HACK generator working.
731 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
732 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
733 qualifier to get the hack generator working.
734 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
736 (DSLLV): Use do_dsllv.
739 (DSRLV): Use do_dsrlv.
740 (BC1): Move *vr4100 to get the HACK generator working.
741 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
742 get the HACK generator working.
743 (MACC) Rename to get the HACK generator working.
744 (DMACC,MACCS,DMACCS): Add the 64.
746 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
748 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
749 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
751 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
753 * mips/interp.c (DEBUG): Cleanups.
755 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
757 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
758 (tx3904sio_tickle): fflush after a stdout character output.
760 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
762 * interp.c (sim_close): Uninstall modules.
764 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
766 * sim-main.h, interp.c (sim_monitor): Change to global
769 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
771 * configure.in (vr4100): Only include vr4100 instructions in
773 * configure: Re-generate.
774 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
776 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
778 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
779 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
782 * configure.in (sim_default_gen, sim_use_gen): Replace with
784 (--enable-sim-igen): Delete config option. Always using IGEN.
785 * configure: Re-generate.
787 * Makefile.in (gencode): Kill, kill, kill.
790 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
792 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
793 bit mips16 igen simulator.
794 * configure: Re-generate.
796 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
797 as part of vr4100 ISA.
798 * vr.igen: Mark all instructions as 64 bit only.
800 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
802 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
805 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
807 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
808 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
809 * configure: Re-generate.
811 * m16.igen (BREAK): Define breakpoint instruction.
812 (JALX32): Mark instruction as mips16 and not r3900.
813 * mips.igen (C.cond.fmt): Fix typo in instruction format.
815 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
817 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
819 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
820 insn as a debug breakpoint.
822 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
824 (PENDING_SCHED): Clean up trace statement.
825 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
826 (PENDING_FILL): Delay write by only one cycle.
827 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
829 * sim-main.c (pending_tick): Clean up trace statements. Add trace
831 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
833 (pending_tick): Move incrementing of index to FOR statement.
834 (pending_tick): Only update PENDING_OUT after a write has occured.
836 * configure.in: Add explicit mips-lsi-* target. Use gencode to
838 * configure: Re-generate.
840 * interp.c (sim_engine_run OLD): Delete explicit call to
841 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
843 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
845 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
846 interrupt level number to match changed SignalExceptionInterrupt
849 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
851 * interp.c: #include "itable.h" if WITH_IGEN.
852 (get_insn_name): New function.
853 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
854 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
856 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
858 * configure: Rebuilt to inhale new common/aclocal.m4.
860 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
862 * dv-tx3904sio.c: Include sim-assert.h.
864 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
866 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
867 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
868 Reorganize target-specific sim-hardware checks.
869 * configure: rebuilt.
870 * interp.c (sim_open): For tx39 target boards, set
871 OPERATING_ENVIRONMENT, add tx3904sio devices.
872 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
873 ROM executables. Install dv-sockser into sim-modules list.
875 * dv-tx3904irc.c: Compiler warning clean-up.
876 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
877 frequent hw-trace messages.
879 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
881 * vr.igen (MulAcc): Identify as a vr4100 specific function.
883 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
885 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
888 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
889 * mips.igen: Define vr4100 model. Include vr.igen.
890 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
892 * mips.igen (check_mf_hilo): Correct check.
894 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
896 * sim-main.h (interrupt_event): Add prototype.
898 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
899 register_ptr, register_value.
900 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
902 * sim-main.h (tracefh): Make extern.
904 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
906 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
907 Reduce unnecessarily high timer event frequency.
908 * dv-tx3904cpu.c: Ditto for interrupt event.
910 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
912 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
914 (interrupt_event): Made non-static.
916 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
917 interchange of configuration values for external vs. internal
920 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
922 * mips.igen (BREAK): Moved code to here for
923 simulator-reserved break instructions.
924 * gencode.c (build_instruction): Ditto.
925 * interp.c (signal_exception): Code moved from here. Non-
926 reserved instructions now use exception vector, rather
928 * sim-main.h: Moved magic constants to here.
930 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
932 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
933 register upon non-zero interrupt event level, clear upon zero
935 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
936 by passing zero event value.
937 (*_io_{read,write}_buffer): Endianness fixes.
938 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
939 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
941 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
942 serial I/O and timer module at base address 0xFFFF0000.
944 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
946 * mips.igen (SWC1) : Correct the handling of ReverseEndian
949 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
951 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
955 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
957 * dv-tx3904tmr.c: New file - implements tx3904 timer.
958 * dv-tx3904{irc,cpu}.c: Mild reformatting.
959 * configure.in: Include tx3904tmr in hw_device list.
960 * configure: Rebuilt.
961 * interp.c (sim_open): Instantiate three timer instances.
962 Fix address typo of tx3904irc instance.
964 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
966 * interp.c (signal_exception): SystemCall exception now uses
967 the exception vector.
969 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
971 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
974 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
976 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
978 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
980 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
982 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
983 sim-main.h. Declare a struct hw_descriptor instead of struct
984 hw_device_descriptor.
986 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
988 * mips.igen (do_store_left, do_load_left): Compute nr of left and
989 right bits and then re-align left hand bytes to correct byte
990 lanes. Fix incorrect computation in do_store_left when loading
991 bytes from second word.
993 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
995 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
996 * interp.c (sim_open): Only create a device tree when HW is
999 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1000 * interp.c (signal_exception): Ditto.
1002 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1004 * gencode.c: Mark BEGEZALL as LIKELY.
1006 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1008 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1009 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1011 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1013 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1014 modules. Recognize TX39 target with "mips*tx39" pattern.
1015 * configure: Rebuilt.
1016 * sim-main.h (*): Added many macros defining bits in
1017 TX39 control registers.
1018 (SignalInterrupt): Send actual PC instead of NULL.
1019 (SignalNMIReset): New exception type.
1020 * interp.c (board): New variable for future use to identify
1021 a particular board being simulated.
1022 (mips_option_handler,mips_options): Added "--board" option.
1023 (interrupt_event): Send actual PC.
1024 (sim_open): Make memory layout conditional on board setting.
1025 (signal_exception): Initial implementation of hardware interrupt
1026 handling. Accept another break instruction variant for simulator
1028 (decode_coproc): Implement RFE instruction for TX39.
1029 (mips.igen): Decode RFE instruction as such.
1030 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1031 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1032 bbegin to implement memory map.
1033 * dv-tx3904cpu.c: New file.
1034 * dv-tx3904irc.c: New file.
1036 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1038 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1040 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1042 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1043 with calls to check_div_hilo.
1045 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1047 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1048 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1049 Add special r3900 version of do_mult_hilo.
1050 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1051 with calls to check_mult_hilo.
1052 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1053 with calls to check_div_hilo.
1055 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1057 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1058 Document a replacement.
1060 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1062 * interp.c (sim_monitor): Make mon_printf work.
1064 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1066 * sim-main.h (INSN_NAME): New arg `cpu'.
1068 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1070 * configure: Regenerated to track ../common/aclocal.m4 changes.
1072 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1074 * configure: Regenerated to track ../common/aclocal.m4 changes.
1077 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1079 * acconfig.h: New file.
1080 * configure.in: Reverted change of Apr 24; use sinclude again.
1082 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1084 * configure: Regenerated to track ../common/aclocal.m4 changes.
1087 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1089 * configure.in: Don't call sinclude.
1091 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1093 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1095 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1097 * mips.igen (ERET): Implement.
1099 * interp.c (decode_coproc): Return sign-extended EPC.
1101 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1103 * interp.c (signal_exception): Do not ignore Trap.
1104 (signal_exception): On TRAP, restart at exception address.
1105 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1106 (signal_exception): Update.
1107 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1108 so that TRAP instructions are caught.
1110 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1112 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1113 contains HI/LO access history.
1114 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1115 (HIACCESS, LOACCESS): Delete, replace with
1116 (HIHISTORY, LOHISTORY): New macros.
1117 (CHECKHILO): Delete all, moved to mips.igen
1119 * gencode.c (build_instruction): Do not generate checks for
1120 correct HI/LO register usage.
1122 * interp.c (old_engine_run): Delete checks for correct HI/LO
1125 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1126 check_mf_cycles): New functions.
1127 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1128 do_divu, domultx, do_mult, do_multu): Use.
1130 * tx.igen ("madd", "maddu"): Use.
1132 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1134 * mips.igen (DSRAV): Use function do_dsrav.
1135 (SRAV): Use new function do_srav.
1137 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1138 (B): Sign extend 11 bit immediate.
1139 (EXT-B*): Shift 16 bit immediate left by 1.
1140 (ADDIU*): Don't sign extend immediate value.
1142 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1144 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1146 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1149 * mips.igen (delayslot32, nullify_next_insn): New functions.
1150 (m16.igen): Always include.
1151 (do_*): Add more tracing.
1153 * m16.igen (delayslot16): Add NIA argument, could be called by a
1154 32 bit MIPS16 instruction.
1156 * interp.c (ifetch16): Move function from here.
1157 * sim-main.c (ifetch16): To here.
1159 * sim-main.c (ifetch16, ifetch32): Update to match current
1160 implementations of LH, LW.
1161 (signal_exception): Don't print out incorrect hex value of illegal
1164 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1166 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1169 * m16.igen: Implement MIPS16 instructions.
1171 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1172 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1173 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1174 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1175 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1176 bodies of corresponding code from 32 bit insn to these. Also used
1177 by MIPS16 versions of functions.
1179 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1180 (IMEM16): Drop NR argument from macro.
1182 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1184 * Makefile.in (SIM_OBJS): Add sim-main.o.
1186 * sim-main.h (address_translation, load_memory, store_memory,
1187 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1189 (pr_addr, pr_uword64): Declare.
1190 (sim-main.c): Include when H_REVEALS_MODULE_P.
1192 * interp.c (address_translation, load_memory, store_memory,
1193 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1195 * sim-main.c: To here. Fix compilation problems.
1197 * configure.in: Enable inlining.
1198 * configure: Re-config.
1200 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1202 * configure: Regenerated to track ../common/aclocal.m4 changes.
1204 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1206 * mips.igen: Include tx.igen.
1207 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1208 * tx.igen: New file, contains MADD and MADDU.
1210 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1211 the hardwired constant `7'.
1212 (store_memory): Ditto.
1213 (LOADDRMASK): Move definition to sim-main.h.
1215 mips.igen (MTC0): Enable for r3900.
1218 mips.igen (do_load_byte): Delete.
1219 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1220 do_store_right): New functions.
1221 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1223 configure.in: Let the tx39 use igen again.
1226 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1228 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1229 not an address sized quantity. Return zero for cache sizes.
1231 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1233 * mips.igen (r3900): r3900 does not support 64 bit integer
1236 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1238 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1240 * configure : Rebuild.
1242 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1244 * configure: Regenerated to track ../common/aclocal.m4 changes.
1246 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1248 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1250 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1252 * configure: Regenerated to track ../common/aclocal.m4 changes.
1253 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1255 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1257 * configure: Regenerated to track ../common/aclocal.m4 changes.
1259 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1261 * interp.c (Max, Min): Comment out functions. Not yet used.
1263 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1265 * configure: Regenerated to track ../common/aclocal.m4 changes.
1267 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1269 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1270 configurable settings for stand-alone simulator.
1272 * configure.in: Added X11 search, just in case.
1274 * configure: Regenerated.
1276 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1278 * interp.c (sim_write, sim_read, load_memory, store_memory):
1279 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1281 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1283 * sim-main.h (GETFCC): Return an unsigned value.
1285 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1287 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1288 (DADD): Result destination is RD not RT.
1290 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1292 * sim-main.h (HIACCESS, LOACCESS): Always define.
1294 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1296 * interp.c (sim_info): Delete.
1298 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1300 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1301 (mips_option_handler): New argument `cpu'.
1302 (sim_open): Update call to sim_add_option_table.
1304 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1306 * mips.igen (CxC1): Add tracing.
1308 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1310 * sim-main.h (Max, Min): Declare.
1312 * interp.c (Max, Min): New functions.
1314 * mips.igen (BC1): Add tracing.
1316 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1318 * interp.c Added memory map for stack in vr4100
1320 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1322 * interp.c (load_memory): Add missing "break"'s.
1324 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1326 * interp.c (sim_store_register, sim_fetch_register): Pass in
1327 length parameter. Return -1.
1329 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1331 * interp.c: Added hardware init hook, fixed warnings.
1333 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1335 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1337 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1339 * interp.c (ifetch16): New function.
1341 * sim-main.h (IMEM32): Rename IMEM.
1342 (IMEM16_IMMED): Define.
1344 (DELAY_SLOT): Update.
1346 * m16run.c (sim_engine_run): New file.
1348 * m16.igen: All instructions except LB.
1349 (LB): Call do_load_byte.
1350 * mips.igen (do_load_byte): New function.
1351 (LB): Call do_load_byte.
1353 * mips.igen: Move spec for insn bit size and high bit from here.
1354 * Makefile.in (tmp-igen, tmp-m16): To here.
1356 * m16.dc: New file, decode mips16 instructions.
1358 * Makefile.in (SIM_NO_ALL): Define.
1359 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1361 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1363 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1364 point unit to 32 bit registers.
1365 * configure: Re-generate.
1367 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1369 * configure.in (sim_use_gen): Make IGEN the default simulator
1370 generator for generic 32 and 64 bit mips targets.
1371 * configure: Re-generate.
1373 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1375 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1378 * interp.c (sim_fetch_register, sim_store_register): Read/write
1379 FGR from correct location.
1380 (sim_open): Set size of FGR's according to
1381 WITH_TARGET_FLOATING_POINT_BITSIZE.
1383 * sim-main.h (FGR): Store floating point registers in a separate
1386 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1388 * configure: Regenerated to track ../common/aclocal.m4 changes.
1390 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1392 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1394 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1396 * interp.c (pending_tick): New function. Deliver pending writes.
1398 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1399 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1400 it can handle mixed sized quantites and single bits.
1402 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1404 * interp.c (oengine.h): Do not include when building with IGEN.
1405 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1406 (sim_info): Ditto for PROCESSOR_64BIT.
1407 (sim_monitor): Replace ut_reg with unsigned_word.
1408 (*): Ditto for t_reg.
1409 (LOADDRMASK): Define.
1410 (sim_open): Remove defunct check that host FP is IEEE compliant,
1411 using software to emulate floating point.
1412 (value_fpr, ...): Always compile, was conditional on HASFPU.
1414 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1416 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1419 * interp.c (SD, CPU): Define.
1420 (mips_option_handler): Set flags in each CPU.
1421 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1422 (sim_close): Do not clear STATE, deleted anyway.
1423 (sim_write, sim_read): Assume CPU zero's vm should be used for
1425 (sim_create_inferior): Set the PC for all processors.
1426 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1428 (mips16_entry): Pass correct nr of args to store_word, load_word.
1429 (ColdReset): Cold reset all cpu's.
1430 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1431 (sim_monitor, load_memory, store_memory, signal_exception): Use
1432 `CPU' instead of STATE_CPU.
1435 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1438 * sim-main.h (signal_exception): Add sim_cpu arg.
1439 (SignalException*): Pass both SD and CPU to signal_exception.
1440 * interp.c (signal_exception): Update.
1442 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1444 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1445 address_translation): Ditto
1446 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1448 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1450 * configure: Regenerated to track ../common/aclocal.m4 changes.
1452 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1454 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1456 * mips.igen (model): Map processor names onto BFD name.
1458 * sim-main.h (CPU_CIA): Delete.
1459 (SET_CIA, GET_CIA): Define
1461 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1463 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1466 * configure.in (default_endian): Configure a big-endian simulator
1468 * configure: Re-generate.
1470 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1472 * configure: Regenerated to track ../common/aclocal.m4 changes.
1474 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1476 * interp.c (sim_monitor): Handle Densan monitor outbyte
1477 and inbyte functions.
1479 1997-12-29 Felix Lee <flee@cygnus.com>
1481 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1483 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1485 * Makefile.in (tmp-igen): Arrange for $zero to always be
1486 reset to zero after every instruction.
1488 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1490 * configure: Regenerated to track ../common/aclocal.m4 changes.
1493 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1495 * mips.igen (MSUB): Fix to work like MADD.
1496 * gencode.c (MSUB): Similarly.
1498 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1500 * configure: Regenerated to track ../common/aclocal.m4 changes.
1502 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1504 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1506 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1508 * sim-main.h (sim-fpu.h): Include.
1510 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1511 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1512 using host independant sim_fpu module.
1514 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1516 * interp.c (signal_exception): Report internal errors with SIGABRT
1519 * sim-main.h (C0_CONFIG): New register.
1520 (signal.h): No longer include.
1522 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1524 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1526 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1528 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530 * mips.igen: Tag vr5000 instructions.
1531 (ANDI): Was missing mipsIV model, fix assembler syntax.
1532 (do_c_cond_fmt): New function.
1533 (C.cond.fmt): Handle mips I-III which do not support CC field
1535 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1536 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1538 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1539 vr5000 which saves LO in a GPR separatly.
1541 * configure.in (enable-sim-igen): For vr5000, select vr5000
1542 specific instructions.
1543 * configure: Re-generate.
1545 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1547 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1549 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1550 fmt_uninterpreted_64 bit cases to switch. Convert to
1553 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1555 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1556 as specified in IV3.2 spec.
1557 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1559 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1561 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1562 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1563 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1564 PENDING_FILL versions of instructions. Simplify.
1566 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1568 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1570 (MTHI, MFHI): Disable code checking HI-LO.
1572 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1574 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1576 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1578 * gencode.c (build_mips16_operands): Replace IPC with cia.
1580 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1581 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1583 (UndefinedResult): Replace function with macro/function
1585 (sim_engine_run): Don't save PC in IPC.
1587 * sim-main.h (IPC): Delete.
1590 * interp.c (signal_exception, store_word, load_word,
1591 address_translation, load_memory, store_memory, cache_op,
1592 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1593 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1594 current instruction address - cia - argument.
1595 (sim_read, sim_write): Call address_translation directly.
1596 (sim_engine_run): Rename variable vaddr to cia.
1597 (signal_exception): Pass cia to sim_monitor
1599 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1600 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1601 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1603 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1604 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1607 * interp.c (signal_exception): Pass restart address to
1610 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1611 idecode.o): Add dependency.
1613 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1615 (DELAY_SLOT): Update NIA not PC with branch address.
1616 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1618 * mips.igen: Use CIA not PC in branch calculations.
1619 (illegal): Call SignalException.
1620 (BEQ, ADDIU): Fix assembler.
1622 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1624 * m16.igen (JALX): Was missing.
1626 * configure.in (enable-sim-igen): New configuration option.
1627 * configure: Re-generate.
1629 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1631 * interp.c (load_memory, store_memory): Delete parameter RAW.
1632 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1633 bypassing {load,store}_memory.
1635 * sim-main.h (ByteSwapMem): Delete definition.
1637 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1639 * interp.c (sim_do_command, sim_commands): Delete mips specific
1640 commands. Handled by module sim-options.
1642 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1643 (WITH_MODULO_MEMORY): Define.
1645 * interp.c (sim_info): Delete code printing memory size.
1647 * interp.c (mips_size): Nee sim_size, delete function.
1649 (monitor, monitor_base, monitor_size): Delete global variables.
1650 (sim_open, sim_close): Delete code creating monitor and other
1651 memory regions. Use sim-memopts module, via sim_do_commandf, to
1652 manage memory regions.
1653 (load_memory, store_memory): Use sim-core for memory model.
1655 * interp.c (address_translation): Delete all memory map code
1656 except line forcing 32 bit addresses.
1658 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1660 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1663 * interp.c (logfh, logfile): Delete globals.
1664 (sim_open, sim_close): Delete code opening & closing log file.
1665 (mips_option_handler): Delete -l and -n options.
1666 (OPTION mips_options): Ditto.
1668 * interp.c (OPTION mips_options): Rename option trace to dinero.
1669 (mips_option_handler): Update.
1671 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1673 * interp.c (fetch_str): New function.
1674 (sim_monitor): Rewrite using sim_read & sim_write.
1675 (sim_open): Check magic number.
1676 (sim_open): Write monitor vectors into memory using sim_write.
1677 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1678 (sim_read, sim_write): Simplify - transfer data one byte at a
1680 (load_memory, store_memory): Clarify meaning of parameter RAW.
1682 * sim-main.h (isHOST): Defete definition.
1683 (isTARGET): Mark as depreciated.
1684 (address_translation): Delete parameter HOST.
1686 * interp.c (address_translation): Delete parameter HOST.
1688 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1692 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1693 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1695 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1697 * mips.igen: Add model filter field to records.
1699 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1701 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1703 interp.c (sim_engine_run): Do not compile function sim_engine_run
1704 when WITH_IGEN == 1.
1706 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1707 target architecture.
1709 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1710 igen. Replace with configuration variables sim_igen_flags /
1713 * m16.igen: New file. Copy mips16 insns here.
1714 * mips.igen: From here.
1716 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1718 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1720 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1722 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1724 * gencode.c (build_instruction): Follow sim_write's lead in using
1725 BigEndianMem instead of !ByteSwapMem.
1727 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1729 * configure.in (sim_gen): Dependent on target, select type of
1730 generator. Always select old style generator.
1732 configure: Re-generate.
1734 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1736 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1737 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1738 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1739 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1740 SIM_@sim_gen@_*, set by autoconf.
1742 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1744 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1746 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1747 CURRENT_FLOATING_POINT instead.
1749 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1750 (address_translation): Raise exception InstructionFetch when
1751 translation fails and isINSTRUCTION.
1753 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1754 sim_engine_run): Change type of of vaddr and paddr to
1756 (address_translation, prefetch, load_memory, store_memory,
1757 cache_op): Change type of vAddr and pAddr to address_word.
1759 * gencode.c (build_instruction): Change type of vaddr and paddr to
1762 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1764 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1765 macro to obtain result of ALU op.
1767 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1769 * interp.c (sim_info): Call profile_print.
1771 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1773 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1775 * sim-main.h (WITH_PROFILE): Do not define, defined in
1776 common/sim-config.h. Use sim-profile module.
1777 (simPROFILE): Delete defintion.
1779 * interp.c (PROFILE): Delete definition.
1780 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1781 (sim_close): Delete code writing profile histogram.
1782 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1784 (sim_engine_run): Delete code profiling the PC.
1786 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1788 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1790 * interp.c (sim_monitor): Make register pointers of type
1793 * sim-main.h: Make registers of type unsigned_word not
1796 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1798 * interp.c (sync_operation): Rename from SyncOperation, make
1799 global, add SD argument.
1800 (prefetch): Rename from Prefetch, make global, add SD argument.
1801 (decode_coproc): Make global.
1803 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1805 * gencode.c (build_instruction): Generate DecodeCoproc not
1806 decode_coproc calls.
1808 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1809 (SizeFGR): Move to sim-main.h
1810 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1811 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1812 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1814 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1815 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1816 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1817 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1818 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1819 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1821 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1823 (sim-alu.h): Include.
1824 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1825 (sim_cia): Typedef to instruction_address.
1827 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1829 * Makefile.in (interp.o): Rename generated file engine.c to
1834 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1836 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1838 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840 * gencode.c (build_instruction): For "FPSQRT", output correct
1841 number of arguments to Recip.
1843 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1845 * Makefile.in (interp.o): Depends on sim-main.h
1847 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1849 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1850 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1851 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1852 STATE, DSSTATE): Define
1853 (GPR, FGRIDX, ..): Define.
1855 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1856 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1857 (GPR, FGRIDX, ...): Delete macros.
1859 * interp.c: Update names to match defines from sim-main.h
1861 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1863 * interp.c (sim_monitor): Add SD argument.
1864 (sim_warning): Delete. Replace calls with calls to
1866 (sim_error): Delete. Replace calls with sim_io_error.
1867 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1868 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1869 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1871 (mips_size): Rename from sim_size. Add SD argument.
1873 * interp.c (simulator): Delete global variable.
1874 (callback): Delete global variable.
1875 (mips_option_handler, sim_open, sim_write, sim_read,
1876 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1877 sim_size,sim_monitor): Use sim_io_* not callback->*.
1878 (sim_open): ZALLOC simulator struct.
1879 (PROFILE): Do not define.
1881 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1883 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1884 support.h with corresponding code.
1886 * sim-main.h (word64, uword64), support.h: Move definition to
1888 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1891 * Makefile.in: Update dependencies
1892 * interp.c: Do not include.
1894 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1896 * interp.c (address_translation, load_memory, store_memory,
1897 cache_op): Rename to from AddressTranslation et.al., make global,
1900 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1903 * interp.c (SignalException): Rename to signal_exception, make
1906 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1908 * sim-main.h (SignalException, SignalExceptionInterrupt,
1909 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1910 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1911 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1914 * interp.c, support.h: Use.
1916 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1918 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1919 to value_fpr / store_fpr. Add SD argument.
1920 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1921 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1923 * sim-main.h (ValueFPR, StoreFPR): Define.
1925 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1927 * interp.c (sim_engine_run): Check consistency between configure
1928 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1931 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1932 (mips_fpu): Configure WITH_FLOATING_POINT.
1933 (mips_endian): Configure WITH_TARGET_ENDIAN.
1934 * configure: Update.
1936 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1938 * configure: Regenerated to track ../common/aclocal.m4 changes.
1940 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1942 * configure: Regenerated.
1944 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1946 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1948 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1950 * gencode.c (print_igen_insn_models): Assume certain architectures
1951 include all mips* instructions.
1952 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1955 * Makefile.in (tmp.igen): Add target. Generate igen input from
1958 * gencode.c (FEATURE_IGEN): Define.
1959 (main): Add --igen option. Generate output in igen format.
1960 (process_instructions): Format output according to igen option.
1961 (print_igen_insn_format): New function.
1962 (print_igen_insn_models): New function.
1963 (process_instructions): Only issue warnings and ignore
1964 instructions when no FEATURE_IGEN.
1966 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1968 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1971 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1973 * configure: Regenerated to track ../common/aclocal.m4 changes.
1975 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1977 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1978 SIM_RESERVED_BITS): Delete, moved to common.
1979 (SIM_EXTRA_CFLAGS): Update.
1981 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1983 * configure.in: Configure non-strict memory alignment.
1984 * configure: Regenerated to track ../common/aclocal.m4 changes.
1986 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1988 * configure: Regenerated to track ../common/aclocal.m4 changes.
1990 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1992 * gencode.c (SDBBP,DERET): Added (3900) insns.
1993 (RFE): Turn on for 3900.
1994 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1995 (dsstate): Made global.
1996 (SUBTARGET_R3900): Added.
1997 (CANCELDELAYSLOT): New.
1998 (SignalException): Ignore SystemCall rather than ignore and
1999 terminate. Add DebugBreakPoint handling.
2000 (decode_coproc): New insns RFE, DERET; and new registers Debug
2001 and DEPC protected by SUBTARGET_R3900.
2002 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2004 * Makefile.in,configure.in: Add mips subtarget option.
2005 * configure: Update.
2007 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2009 * gencode.c: Add r3900 (tx39).
2012 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2014 * gencode.c (build_instruction): Don't need to subtract 4 for
2017 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2019 * interp.c: Correct some HASFPU problems.
2021 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2023 * configure: Regenerated to track ../common/aclocal.m4 changes.
2025 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2027 * interp.c (mips_options): Fix samples option short form, should
2030 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2032 * interp.c (sim_info): Enable info code. Was just returning.
2034 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2036 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2039 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2041 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2043 (build_instruction): Ditto for LL.
2045 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2047 * configure: Regenerated to track ../common/aclocal.m4 changes.
2049 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2051 * configure: Regenerated to track ../common/aclocal.m4 changes.
2054 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2056 * interp.c (sim_open): Add call to sim_analyze_program, update
2059 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2061 * interp.c (sim_kill): Delete.
2062 (sim_create_inferior): Add ABFD argument. Set PC from same.
2063 (sim_load): Move code initializing trap handlers from here.
2064 (sim_open): To here.
2065 (sim_load): Delete, use sim-hload.c.
2067 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2069 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2071 * configure: Regenerated to track ../common/aclocal.m4 changes.
2074 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2076 * interp.c (sim_open): Add ABFD argument.
2077 (sim_load): Move call to sim_config from here.
2078 (sim_open): To here. Check return status.
2080 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2082 * gencode.c (build_instruction): Two arg MADD should
2083 not assign result to $0.
2085 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2087 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2088 * sim/mips/configure.in: Regenerate.
2090 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2092 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2093 signed8, unsigned8 et.al. types.
2095 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2096 hosts when selecting subreg.
2098 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2100 * interp.c (sim_engine_run): Reset the ZERO register to zero
2101 regardless of FEATURE_WARN_ZERO.
2102 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2104 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2106 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2107 (SignalException): For BreakPoints ignore any mode bits and just
2109 (SignalException): Always set the CAUSE register.
2111 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2113 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2114 exception has been taken.
2116 * interp.c: Implement the ERET and mt/f sr instructions.
2118 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2120 * interp.c (SignalException): Don't bother restarting an
2123 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2125 * interp.c (SignalException): Really take an interrupt.
2126 (interrupt_event): Only deliver interrupts when enabled.
2128 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2130 * interp.c (sim_info): Only print info when verbose.
2131 (sim_info) Use sim_io_printf for output.
2133 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2135 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2138 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2140 * interp.c (sim_do_command): Check for common commands if a
2141 simulator specific command fails.
2143 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2145 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2146 and simBE when DEBUG is defined.
2148 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2150 * interp.c (interrupt_event): New function. Pass exception event
2151 onto exception handler.
2153 * configure.in: Check for stdlib.h.
2154 * configure: Regenerate.
2156 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2157 variable declaration.
2158 (build_instruction): Initialize memval1.
2159 (build_instruction): Add UNUSED attribute to byte, bigend,
2161 (build_operands): Ditto.
2163 * interp.c: Fix GCC warnings.
2164 (sim_get_quit_code): Delete.
2166 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2167 * Makefile.in: Ditto.
2168 * configure: Re-generate.
2170 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2172 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2174 * interp.c (mips_option_handler): New function parse argumes using
2176 (myname): Replace with STATE_MY_NAME.
2177 (sim_open): Delete check for host endianness - performed by
2179 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2180 (sim_open): Move much of the initialization from here.
2181 (sim_load): To here. After the image has been loaded and
2183 (sim_open): Move ColdReset from here.
2184 (sim_create_inferior): To here.
2185 (sim_open): Make FP check less dependant on host endianness.
2187 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2189 * interp.c (sim_set_callbacks): Delete.
2191 * interp.c (membank, membank_base, membank_size): Replace with
2192 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2193 (sim_open): Remove call to callback->init. gdb/run do this.
2197 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2199 * interp.c (big_endian_p): Delete, replaced by
2200 current_target_byte_order.
2202 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2204 * interp.c (host_read_long, host_read_word, host_swap_word,
2205 host_swap_long): Delete. Using common sim-endian.
2206 (sim_fetch_register, sim_store_register): Use H2T.
2207 (pipeline_ticks): Delete. Handled by sim-events.
2209 (sim_engine_run): Update.
2211 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2213 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2215 (SignalException): To here. Signal using sim_engine_halt.
2216 (sim_stop_reason): Delete, moved to common.
2218 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2220 * interp.c (sim_open): Add callback argument.
2221 (sim_set_callbacks): Delete SIM_DESC argument.
2224 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2226 * Makefile.in (SIM_OBJS): Add common modules.
2228 * interp.c (sim_set_callbacks): Also set SD callback.
2229 (set_endianness, xfer_*, swap_*): Delete.
2230 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2231 Change to functions using sim-endian macros.
2232 (control_c, sim_stop): Delete, use common version.
2233 (simulate): Convert into.
2234 (sim_engine_run): This function.
2235 (sim_resume): Delete.
2237 * interp.c (simulation): New variable - the simulator object.
2238 (sim_kind): Delete global - merged into simulation.
2239 (sim_load): Cleanup. Move PC assignment from here.
2240 (sim_create_inferior): To here.
2242 * sim-main.h: New file.
2243 * interp.c (sim-main.h): Include.
2245 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2247 * configure: Regenerated to track ../common/aclocal.m4 changes.
2249 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2251 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2253 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2255 * gencode.c (build_instruction): DIV instructions: check
2256 for division by zero and integer overflow before using
2257 host's division operation.
2259 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2261 * Makefile.in (SIM_OBJS): Add sim-load.o.
2262 * interp.c: #include bfd.h.
2263 (target_byte_order): Delete.
2264 (sim_kind, myname, big_endian_p): New static locals.
2265 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2266 after argument parsing. Recognize -E arg, set endianness accordingly.
2267 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2268 load file into simulator. Set PC from bfd.
2269 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2270 (set_endianness): Use big_endian_p instead of target_byte_order.
2272 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2274 * interp.c (sim_size): Delete prototype - conflicts with
2275 definition in remote-sim.h. Correct definition.
2277 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2279 * configure: Regenerated to track ../common/aclocal.m4 changes.
2282 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2284 * interp.c (sim_open): New arg `kind'.
2286 * configure: Regenerated to track ../common/aclocal.m4 changes.
2288 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2290 * configure: Regenerated to track ../common/aclocal.m4 changes.
2292 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2294 * interp.c (sim_open): Set optind to 0 before calling getopt.
2296 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2298 * configure: Regenerated to track ../common/aclocal.m4 changes.
2300 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2302 * interp.c : Replace uses of pr_addr with pr_uword64
2303 where the bit length is always 64 independent of SIM_ADDR.
2304 (pr_uword64) : added.
2306 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2308 * configure: Re-generate.
2310 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2312 * configure: Regenerate to track ../common/aclocal.m4 changes.
2314 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2316 * interp.c (sim_open): New SIM_DESC result. Argument is now
2318 (other sim_*): New SIM_DESC argument.
2320 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2322 * interp.c: Fix printing of addresses for non-64-bit targets.
2323 (pr_addr): Add function to print address based on size.
2325 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2327 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2329 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2331 * gencode.c (build_mips16_operands): Correct computation of base
2332 address for extended PC relative instruction.
2334 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2336 * interp.c (mips16_entry): Add support for floating point cases.
2337 (SignalException): Pass floating point cases to mips16_entry.
2338 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2340 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2342 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2343 and then set the state to fmt_uninterpreted.
2344 (COP_SW): Temporarily set the state to fmt_word while calling
2347 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2349 * gencode.c (build_instruction): The high order may be set in the
2350 comparison flags at any ISA level, not just ISA 4.
2352 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2354 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2355 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2356 * configure.in: sinclude ../common/aclocal.m4.
2357 * configure: Regenerated.
2359 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2361 * configure: Rebuild after change to aclocal.m4.
2363 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2365 * configure configure.in Makefile.in: Update to new configure
2366 scheme which is more compatible with WinGDB builds.
2367 * configure.in: Improve comment on how to run autoconf.
2368 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2369 * Makefile.in: Use autoconf substitution to install common
2372 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2374 * gencode.c (build_instruction): Use BigEndianCPU instead of
2377 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2379 * interp.c (sim_monitor): Make output to stdout visible in
2380 wingdb's I/O log window.
2382 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2384 * support.h: Undo previous change to SIGTRAP
2387 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2389 * interp.c (store_word, load_word): New static functions.
2390 (mips16_entry): New static function.
2391 (SignalException): Look for mips16 entry and exit instructions.
2392 (simulate): Use the correct index when setting fpr_state after
2393 doing a pending move.
2395 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2397 * interp.c: Fix byte-swapping code throughout to work on
2398 both little- and big-endian hosts.
2400 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2402 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2403 with gdb/config/i386/xm-windows.h.
2405 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2407 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2408 that messes up arithmetic shifts.
2410 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2412 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2413 SIGTRAP and SIGQUIT for _WIN32.
2415 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2417 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2418 force a 64 bit multiplication.
2419 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2420 destination register is 0, since that is the default mips16 nop
2423 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2425 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2426 (build_endian_shift): Don't check proc64.
2427 (build_instruction): Always set memval to uword64. Cast op2 to
2428 uword64 when shifting it left in memory instructions. Always use
2429 the same code for stores--don't special case proc64.
2431 * gencode.c (build_mips16_operands): Fix base PC value for PC
2433 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2435 * interp.c (simJALDELAYSLOT): Define.
2436 (JALDELAYSLOT): Define.
2437 (INDELAYSLOT, INJALDELAYSLOT): Define.
2438 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2440 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2442 * interp.c (sim_open): add flush_cache as a PMON routine
2443 (sim_monitor): handle flush_cache by ignoring it
2445 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2447 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2449 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2450 (BigEndianMem): Rename to ByteSwapMem and change sense.
2451 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2452 BigEndianMem references to !ByteSwapMem.
2453 (set_endianness): New function, with prototype.
2454 (sim_open): Call set_endianness.
2455 (sim_info): Use simBE instead of BigEndianMem.
2456 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2457 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2458 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2459 ifdefs, keeping the prototype declaration.
2460 (swap_word): Rewrite correctly.
2461 (ColdReset): Delete references to CONFIG. Delete endianness related
2462 code; moved to set_endianness.
2464 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2466 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2467 * interp.c (CHECKHILO): Define away.
2468 (simSIGINT): New macro.
2469 (membank_size): Increase from 1MB to 2MB.
2470 (control_c): New function.
2471 (sim_resume): Rename parameter signal to signal_number. Add local
2472 variable prev. Call signal before and after simulate.
2473 (sim_stop_reason): Add simSIGINT support.
2474 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2476 (sim_warning): Delete call to SignalException. Do call printf_filtered
2478 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2479 a call to sim_warning.
2481 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2483 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2484 16 bit instructions.
2486 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2488 Add support for mips16 (16 bit MIPS implementation):
2489 * gencode.c (inst_type): Add mips16 instruction encoding types.
2490 (GETDATASIZEINSN): Define.
2491 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2492 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2494 (MIPS16_DECODE): New table, for mips16 instructions.
2495 (bitmap_val): New static function.
2496 (struct mips16_op): Define.
2497 (mips16_op_table): New table, for mips16 operands.
2498 (build_mips16_operands): New static function.
2499 (process_instructions): If PC is odd, decode a mips16
2500 instruction. Break out instruction handling into new
2501 build_instruction function.
2502 (build_instruction): New static function, broken out of
2503 process_instructions. Check modifiers rather than flags for SHIFT
2504 bit count and m[ft]{hi,lo} direction.
2505 (usage): Pass program name to fprintf.
2506 (main): Remove unused variable this_option_optind. Change
2507 ``*loptarg++'' to ``loptarg++''.
2508 (my_strtoul): Parenthesize && within ||.
2509 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2510 (simulate): If PC is odd, fetch a 16 bit instruction, and
2511 increment PC by 2 rather than 4.
2512 * configure.in: Add case for mips16*-*-*.
2513 * configure: Rebuild.
2515 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2517 * interp.c: Allow -t to enable tracing in standalone simulator.
2518 Fix garbage output in trace file and error messages.
2520 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2522 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2523 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2524 * configure.in: Simplify using macros in ../common/aclocal.m4.
2525 * configure: Regenerated.
2526 * tconfig.in: New file.
2528 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2530 * interp.c: Fix bugs in 64-bit port.
2531 Use ansi function declarations for msvc compiler.
2532 Initialize and test file pointer in trace code.
2533 Prevent duplicate definition of LAST_EMED_REGNUM.
2535 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2537 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2539 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2541 * interp.c (SignalException): Check for explicit terminating
2543 * gencode.c: Pass instruction value through SignalException()
2544 calls for Trap, Breakpoint and Syscall.
2546 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2548 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2549 only used on those hosts that provide it.
2550 * configure.in: Add sqrt() to list of functions to be checked for.
2551 * config.in: Re-generated.
2552 * configure: Re-generated.
2554 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2556 * gencode.c (process_instructions): Call build_endian_shift when
2557 expanding STORE RIGHT, to fix swr.
2558 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2559 clear the high bits.
2560 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2561 Fix float to int conversions to produce signed values.
2563 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2565 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2566 (process_instructions): Correct handling of nor instruction.
2567 Correct shift count for 32 bit shift instructions. Correct sign
2568 extension for arithmetic shifts to not shift the number of bits in
2569 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2570 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2572 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2573 It's OK to have a mult follow a mult. What's not OK is to have a
2574 mult follow an mfhi.
2575 (Convert): Comment out incorrect rounding code.
2577 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2579 * interp.c (sim_monitor): Improved monitor printf
2580 simulation. Tidied up simulator warnings, and added "--log" option
2581 for directing warning message output.
2582 * gencode.c: Use sim_warning() rather than WARNING macro.
2584 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2586 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2587 getopt1.o, rather than on gencode.c. Link objects together.
2588 Don't link against -liberty.
2589 (gencode.o, getopt.o, getopt1.o): New targets.
2590 * gencode.c: Include <ctype.h> and "ansidecl.h".
2591 (AND): Undefine after including "ansidecl.h".
2592 (ULONG_MAX): Define if not defined.
2593 (OP_*): Don't define macros; now defined in opcode/mips.h.
2594 (main): Call my_strtoul rather than strtoul.
2595 (my_strtoul): New static function.
2597 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2599 * gencode.c (process_instructions): Generate word64 and uword64
2600 instead of `long long' and `unsigned long long' data types.
2601 * interp.c: #include sysdep.h to get signals, and define default
2603 * (Convert): Work around for Visual-C++ compiler bug with type
2605 * support.h: Make things compile under Visual-C++ by using
2606 __int64 instead of `long long'. Change many refs to long long
2607 into word64/uword64 typedefs.
2609 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2611 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2612 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2614 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2615 (AC_PROG_INSTALL): Added.
2616 (AC_PROG_CC): Moved to before configure.host call.
2617 * configure: Rebuilt.
2619 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2621 * configure.in: Define @SIMCONF@ depending on mips target.
2622 * configure: Rebuild.
2623 * Makefile.in (run): Add @SIMCONF@ to control simulator
2625 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2626 * interp.c: Remove some debugging, provide more detailed error
2627 messages, update memory accesses to use LOADDRMASK.
2629 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2631 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2632 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2634 * configure: Rebuild.
2635 * config.in: New file, generated by autoheader.
2636 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2637 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2638 HAVE_ANINT and HAVE_AINT, as appropriate.
2639 * Makefile.in (run): Use @LIBS@ rather than -lm.
2640 (interp.o): Depend upon config.h.
2641 (Makefile): Just rebuild Makefile.
2642 (clean): Remove stamp-h.
2643 (mostlyclean): Make the same as clean, not as distclean.
2644 (config.h, stamp-h): New targets.
2646 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2648 * interp.c (ColdReset): Fix boolean test. Make all simulator
2651 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2653 * interp.c (xfer_direct_word, xfer_direct_long,
2654 swap_direct_word, swap_direct_long, xfer_big_word,
2655 xfer_big_long, xfer_little_word, xfer_little_long,
2656 swap_word,swap_long): Added.
2657 * interp.c (ColdReset): Provide function indirection to
2658 host<->simulated_target transfer routines.
2659 * interp.c (sim_store_register, sim_fetch_register): Updated to
2660 make use of indirected transfer routines.
2662 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2664 * gencode.c (process_instructions): Ensure FP ABS instruction
2666 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2667 system call support.
2669 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2671 * interp.c (sim_do_command): Complain if callback structure not
2674 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2676 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2677 support for Sun hosts.
2678 * Makefile.in (gencode): Ensure the host compiler and libraries
2679 used for cross-hosted build.
2681 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2683 * interp.c, gencode.c: Some more (TODO) tidying.
2685 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2687 * gencode.c, interp.c: Replaced explicit long long references with
2688 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2689 * support.h (SET64LO, SET64HI): Macros added.
2691 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2693 * configure: Regenerate with autoconf 2.7.
2695 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2697 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2698 * support.h: Remove superfluous "1" from #if.
2699 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2701 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2703 * interp.c (StoreFPR): Control UndefinedResult() call on
2704 WARN_RESULT manifest.
2706 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2708 * gencode.c: Tidied instruction decoding, and added FP instruction
2711 * interp.c: Added dineroIII, and BSD profiling support. Also
2712 run-time FP handling.
2714 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2716 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2717 gencode.c, interp.c, support.h: created.