1 2003-05-16 Ian Lance Taylor <ian@airs.com>
3 * Makefile.in (SHELL): Make sure this is defined.
4 (various): Use $(SHELL) whenever we invoke move-if-change.
6 2003-05-03 Chris Demetriou <cgd@broadcom.com>
8 * cp1.c: Tweak attribution slightly.
11 * mdmx.igen: Likewise.
12 * mips3d.igen: Likewise.
15 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
17 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
20 2003-02-27 Andrew Cagney <cagney@redhat.com>
22 * interp.c (sim_open): Rename _bfd to bfd.
23 (sim_create_inferior): Ditto.
25 2003-01-14 Chris Demetriou <cgd@broadcom.com>
27 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
29 2003-01-14 Chris Demetriou <cgd@broadcom.com>
31 * mips.igen (EI, DI): Remove.
33 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
35 * Makefile.in (tmp-run-multi): Fix mips16 filter.
37 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
38 Andrew Cagney <ac131313@redhat.com>
39 Gavin Romig-Koch <gavin@redhat.com>
40 Graydon Hoare <graydon@redhat.com>
41 Aldy Hernandez <aldyh@redhat.com>
42 Dave Brolley <brolley@redhat.com>
43 Chris Demetriou <cgd@broadcom.com>
45 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
46 (sim_mach_default): New variable.
47 (mips64vr-*-*, mips64vrel-*-*): New configurations.
48 Add a new simulator generator, MULTI.
49 * configure: Regenerate.
50 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
51 (multi-run.o): New dependency.
52 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
53 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
54 (tmp-multi): Combine them.
55 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
56 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
57 (distclean-extra): New rule.
58 * sim-main.h: Include bfd.h.
59 (MIPS_MACH): New macro.
60 * mips.igen (vr4120, vr5400, vr5500): New models.
61 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
62 * vr.igen: Replace with new version.
64 2003-01-04 Chris Demetriou <cgd@broadcom.com>
66 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
67 * configure: Regenerate.
69 2002-12-31 Chris Demetriou <cgd@broadcom.com>
71 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
72 * mips.igen: Remove all invocations of check_branch_bug and
75 2002-12-16 Chris Demetriou <cgd@broadcom.com>
77 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
79 2002-07-30 Chris Demetriou <cgd@broadcom.com>
81 * mips.igen (do_load_double, do_store_double): New functions.
82 (LDC1, SDC1): Rename to...
83 (LDC1b, SDC1b): respectively.
84 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
86 2002-07-29 Michael Snyder <msnyder@redhat.com>
88 * cp1.c (fp_recip2): Modify initialization expression so that
89 GCC will recognize it as constant.
91 2002-06-18 Chris Demetriou <cgd@broadcom.com>
93 * mdmx.c (SD_): Delete.
94 (Unpredictable): Re-define, for now, to directly invoke
95 unpredictable_action().
96 (mdmx_acc_op): Fix error in .ob immediate handling.
98 2002-06-18 Andrew Cagney <cagney@redhat.com>
100 * interp.c (sim_firmware_command): Initialize `address'.
102 2002-06-16 Andrew Cagney <ac131313@redhat.com>
104 * configure: Regenerated to track ../common/aclocal.m4 changes.
106 2002-06-14 Chris Demetriou <cgd@broadcom.com>
107 Ed Satterthwaite <ehs@broadcom.com>
109 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
110 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
111 * mips.igen: Include mips3d.igen.
112 (mips3d): New model name for MIPS-3D ASE instructions.
113 (CVT.W.fmt): Don't use this instruction for word (source) format
115 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
116 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
117 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
118 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
119 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
120 (RSquareRoot1, RSquareRoot2): New macros.
121 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
122 (fp_rsqrt2): New functions.
123 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
124 * configure: Regenerate.
126 2002-06-13 Chris Demetriou <cgd@broadcom.com>
127 Ed Satterthwaite <ehs@broadcom.com>
129 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
130 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
131 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
132 (convert): Note that this function is not used for paired-single
134 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
135 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
136 (check_fmt_p): Enable paired-single support.
137 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
138 (PUU.PS): New instructions.
139 (CVT.S.fmt): Don't use this instruction for paired-single format
141 * sim-main.h (FP_formats): New value 'fmt_ps.'
142 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
143 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
145 2002-06-12 Chris Demetriou <cgd@broadcom.com>
147 * mips.igen: Fix formatting of function calls in
150 2002-06-12 Chris Demetriou <cgd@broadcom.com>
152 * mips.igen (MOVN, MOVZ): Trace result.
153 (TNEI): Print "tnei" as the opcode name in traces.
154 (CEIL.W): Add disassembly string for traces.
155 (RSQRT.fmt): Make location of disassembly string consistent
156 with other instructions.
158 2002-06-12 Chris Demetriou <cgd@broadcom.com>
160 * mips.igen (X): Delete unused function.
162 2002-06-08 Andrew Cagney <cagney@redhat.com>
164 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
166 2002-06-07 Chris Demetriou <cgd@broadcom.com>
167 Ed Satterthwaite <ehs@broadcom.com>
169 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
170 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
171 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
172 (fp_nmsub): New prototypes.
173 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
174 (NegMultiplySub): New defines.
175 * mips.igen (RSQRT.fmt): Use RSquareRoot().
176 (MADD.D, MADD.S): Replace with...
177 (MADD.fmt): New instruction.
178 (MSUB.D, MSUB.S): Replace with...
179 (MSUB.fmt): New instruction.
180 (NMADD.D, NMADD.S): Replace with...
181 (NMADD.fmt): New instruction.
182 (NMSUB.D, MSUB.S): Replace with...
183 (NMSUB.fmt): New instruction.
185 2002-06-07 Chris Demetriou <cgd@broadcom.com>
186 Ed Satterthwaite <ehs@broadcom.com>
188 * cp1.c: Fix more comment spelling and formatting.
189 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
190 (denorm_mode): New function.
191 (fpu_unary, fpu_binary): Round results after operation, collect
192 status from rounding operations, and update the FCSR.
193 (convert): Collect status from integer conversions and rounding
194 operations, and update the FCSR. Adjust NaN values that result
195 from conversions. Convert to use sim_io_eprintf rather than
196 fprintf, and remove some debugging code.
197 * cp1.h (fenr_FS): New define.
199 2002-06-07 Chris Demetriou <cgd@broadcom.com>
201 * cp1.c (convert): Remove unusable debugging code, and move MIPS
202 rounding mode to sim FP rounding mode flag conversion code into...
203 (rounding_mode): New function.
205 2002-06-07 Chris Demetriou <cgd@broadcom.com>
207 * cp1.c: Clean up formatting of a few comments.
208 (value_fpr): Reformat switch statement.
210 2002-06-06 Chris Demetriou <cgd@broadcom.com>
211 Ed Satterthwaite <ehs@broadcom.com>
214 * sim-main.h: Include cp1.h.
215 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
216 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
217 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
218 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
219 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
220 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
221 * cp1.c: Don't include sim-fpu.h; already included by
222 sim-main.h. Clean up formatting of some comments.
223 (NaN, Equal, Less): Remove.
224 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
225 (fp_cmp): New functions.
226 * mips.igen (do_c_cond_fmt): Remove.
227 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
228 Compare. Add result tracing.
229 (CxC1): Remove, replace with...
230 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
231 (DMxC1): Remove, replace with...
232 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
233 (MxC1): Remove, replace with...
234 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
236 2002-06-04 Chris Demetriou <cgd@broadcom.com>
238 * sim-main.h (FGRIDX): Remove, replace all uses with...
239 (FGR_BASE): New macro.
240 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
241 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
242 (NR_FGR, FGR): Likewise.
243 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
244 * mips.igen: Likewise.
246 2002-06-04 Chris Demetriou <cgd@broadcom.com>
248 * cp1.c: Add an FSF Copyright notice to this file.
250 2002-06-04 Chris Demetriou <cgd@broadcom.com>
251 Ed Satterthwaite <ehs@broadcom.com>
253 * cp1.c (Infinity): Remove.
254 * sim-main.h (Infinity): Likewise.
256 * cp1.c (fp_unary, fp_binary): New functions.
257 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
258 (fp_sqrt): New functions, implemented in terms of the above.
259 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
260 (Recip, SquareRoot): Remove (replaced by functions above).
261 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
262 (fp_recip, fp_sqrt): New prototypes.
263 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
264 (Recip, SquareRoot): Replace prototypes with #defines which
265 invoke the functions above.
267 2002-06-03 Chris Demetriou <cgd@broadcom.com>
269 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
270 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
271 file, remove PARAMS from prototypes.
272 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
273 simulator state arguments.
274 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
275 pass simulator state arguments.
276 * cp1.c (SD): Redefine as CPU_STATE(cpu).
277 (store_fpr, convert): Remove 'sd' argument.
278 (value_fpr): Likewise. Convert to use 'SD' instead.
280 2002-06-03 Chris Demetriou <cgd@broadcom.com>
282 * cp1.c (Min, Max): Remove #if 0'd functions.
283 * sim-main.h (Min, Max): Remove.
285 2002-06-03 Chris Demetriou <cgd@broadcom.com>
287 * cp1.c: fix formatting of switch case and default labels.
288 * interp.c: Likewise.
289 * sim-main.c: Likewise.
291 2002-06-03 Chris Demetriou <cgd@broadcom.com>
293 * cp1.c: Clean up comments which describe FP formats.
294 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
296 2002-06-03 Chris Demetriou <cgd@broadcom.com>
297 Ed Satterthwaite <ehs@broadcom.com>
299 * configure.in (mipsisa64sb1*-*-*): New target for supporting
300 Broadcom SiByte SB-1 processor configurations.
301 * configure: Regenerate.
302 * sb1.igen: New file.
303 * mips.igen: Include sb1.igen.
305 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
306 * mdmx.igen: Add "sb1" model to all appropriate functions and
308 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
309 (ob_func, ob_acc): Reference the above.
310 (qh_acc): Adjust to keep the same size as ob_acc.
311 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
312 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
314 2002-06-03 Chris Demetriou <cgd@broadcom.com>
316 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
318 2002-06-02 Chris Demetriou <cgd@broadcom.com>
319 Ed Satterthwaite <ehs@broadcom.com>
321 * mips.igen (mdmx): New (pseudo-)model.
322 * mdmx.c, mdmx.igen: New files.
323 * Makefile.in (SIM_OBJS): Add mdmx.o.
324 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
326 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
327 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
328 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
329 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
330 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
331 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
332 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
333 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
334 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
335 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
336 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
337 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
338 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
339 (qh_fmtsel): New macros.
340 (_sim_cpu): New member "acc".
341 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
342 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
344 2002-05-01 Chris Demetriou <cgd@broadcom.com>
346 * interp.c: Use 'deprecated' rather than 'depreciated.'
347 * sim-main.h: Likewise.
349 2002-05-01 Chris Demetriou <cgd@broadcom.com>
351 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
352 which wouldn't compile anyway.
353 * sim-main.h (unpredictable_action): New function prototype.
354 (Unpredictable): Define to call igen function unpredictable().
355 (NotWordValue): New macro to call igen function not_word_value().
356 (UndefinedResult): Remove.
357 * interp.c (undefined_result): Remove.
358 (unpredictable_action): New function.
359 * mips.igen (not_word_value, unpredictable): New functions.
360 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
361 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
362 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
363 NotWordValue() to check for unpredictable inputs, then
364 Unpredictable() to handle them.
366 2002-02-24 Chris Demetriou <cgd@broadcom.com>
368 * mips.igen: Fix formatting of calls to Unpredictable().
370 2002-04-20 Andrew Cagney <ac131313@redhat.com>
372 * interp.c (sim_open): Revert previous change.
374 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
376 * interp.c (sim_open): Disable chunk of code that wrote code in
377 vector table entries.
379 2002-03-19 Chris Demetriou <cgd@broadcom.com>
381 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
382 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
385 2002-03-19 Chris Demetriou <cgd@broadcom.com>
387 * cp1.c: Fix many formatting issues.
389 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
391 * cp1.c (fpu_format_name): New function to replace...
392 (DOFMT): This. Delete, and update all callers.
393 (fpu_rounding_mode_name): New function to replace...
394 (RMMODE): This. Delete, and update all callers.
396 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
398 * interp.c: Move FPU support routines from here to...
399 * cp1.c: Here. New file.
400 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
403 2002-03-12 Chris Demetriou <cgd@broadcom.com>
405 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
406 * mips.igen (mips32, mips64): New models, add to all instructions
407 and functions as appropriate.
408 (loadstore_ea, check_u64): New variant for model mips64.
409 (check_fmt_p): New variant for models mipsV and mips64, remove
410 mipsV model marking fro other variant.
413 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
414 for mips32 and mips64.
415 (DCLO, DCLZ): New instructions for mips64.
417 2002-03-07 Chris Demetriou <cgd@broadcom.com>
419 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
420 immediate or code as a hex value with the "%#lx" format.
421 (ANDI): Likewise, and fix printed instruction name.
423 2002-03-05 Chris Demetriou <cgd@broadcom.com>
425 * sim-main.h (UndefinedResult, Unpredictable): New macros
426 which currently do nothing.
428 2002-03-05 Chris Demetriou <cgd@broadcom.com>
430 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
431 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
432 (status_CU3): New definitions.
434 * sim-main.h (ExceptionCause): Add new values for MIPS32
435 and MIPS64: MDMX, MCheck, CacheErr. Update comments
436 for DebugBreakPoint and NMIReset to note their status in
438 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
439 (SignalExceptionCacheErr): New exception macros.
441 2002-03-05 Chris Demetriou <cgd@broadcom.com>
443 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
444 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
446 (SignalExceptionCoProcessorUnusable): Take as argument the
447 unusable coprocessor number.
449 2002-03-05 Chris Demetriou <cgd@broadcom.com>
451 * mips.igen: Fix formatting of all SignalException calls.
453 2002-03-05 Chris Demetriou <cgd@broadcom.com>
455 * sim-main.h (SIGNEXTEND): Remove.
457 2002-03-04 Chris Demetriou <cgd@broadcom.com>
459 * mips.igen: Remove gencode comment from top of file, fix
460 spelling in another comment.
462 2002-03-04 Chris Demetriou <cgd@broadcom.com>
464 * mips.igen (check_fmt, check_fmt_p): New functions to check
465 whether specific floating point formats are usable.
466 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
467 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
468 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
469 Use the new functions.
470 (do_c_cond_fmt): Remove format checks...
471 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
473 2002-03-03 Chris Demetriou <cgd@broadcom.com>
475 * mips.igen: Fix formatting of check_fpu calls.
477 2002-03-03 Chris Demetriou <cgd@broadcom.com>
479 * mips.igen (FLOOR.L.fmt): Store correct destination register.
481 2002-03-03 Chris Demetriou <cgd@broadcom.com>
483 * mips.igen: Remove whitespace at end of lines.
485 2002-03-02 Chris Demetriou <cgd@broadcom.com>
487 * mips.igen (loadstore_ea): New function to do effective
488 address calculations.
489 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
490 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
491 CACHE): Use loadstore_ea to do effective address computations.
493 2002-03-02 Chris Demetriou <cgd@broadcom.com>
495 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
496 * mips.igen (LL, CxC1, MxC1): Likewise.
498 2002-03-02 Chris Demetriou <cgd@broadcom.com>
500 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
501 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
502 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
503 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
504 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
505 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
506 Don't split opcode fields by hand, use the opcode field values
509 2002-03-01 Chris Demetriou <cgd@broadcom.com>
511 * mips.igen (do_divu): Fix spacing.
513 * mips.igen (do_dsllv): Move to be right before DSLLV,
514 to match the rest of the do_<shift> functions.
516 2002-03-01 Chris Demetriou <cgd@broadcom.com>
518 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
519 DSRL32, do_dsrlv): Trace inputs and results.
521 2002-03-01 Chris Demetriou <cgd@broadcom.com>
523 * mips.igen (CACHE): Provide instruction-printing string.
525 * interp.c (signal_exception): Comment tokens after #endif.
527 2002-02-28 Chris Demetriou <cgd@broadcom.com>
529 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
530 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
531 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
532 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
533 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
534 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
535 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
536 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
538 2002-02-28 Chris Demetriou <cgd@broadcom.com>
540 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
541 instruction-printing string.
542 (LWU): Use '64' as the filter flag.
544 2002-02-28 Chris Demetriou <cgd@broadcom.com>
546 * mips.igen (SDXC1): Fix instruction-printing string.
548 2002-02-28 Chris Demetriou <cgd@broadcom.com>
550 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
553 2002-02-27 Chris Demetriou <cgd@broadcom.com>
555 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
558 2002-02-27 Chris Demetriou <cgd@broadcom.com>
560 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
561 add a comma) so that it more closely match the MIPS ISA
562 documentation opcode partitioning.
563 (PREF): Put useful names on opcode fields, and include
564 instruction-printing string.
566 2002-02-27 Chris Demetriou <cgd@broadcom.com>
568 * mips.igen (check_u64): New function which in the future will
569 check whether 64-bit instructions are usable and signal an
570 exception if not. Currently a no-op.
571 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
572 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
573 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
574 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
576 * mips.igen (check_fpu): New function which in the future will
577 check whether FPU instructions are usable and signal an exception
578 if not. Currently a no-op.
579 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
580 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
581 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
582 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
583 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
584 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
585 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
586 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
588 2002-02-27 Chris Demetriou <cgd@broadcom.com>
590 * mips.igen (do_load_left, do_load_right): Move to be immediately
592 (do_store_left, do_store_right): Move to be immediately following
595 2002-02-27 Chris Demetriou <cgd@broadcom.com>
597 * mips.igen (mipsV): New model name. Also, add it to
598 all instructions and functions where it is appropriate.
600 2002-02-18 Chris Demetriou <cgd@broadcom.com>
602 * mips.igen: For all functions and instructions, list model
603 names that support that instruction one per line.
605 2002-02-11 Chris Demetriou <cgd@broadcom.com>
607 * mips.igen: Add some additional comments about supported
608 models, and about which instructions go where.
609 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
610 order as is used in the rest of the file.
612 2002-02-11 Chris Demetriou <cgd@broadcom.com>
614 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
615 indicating that ALU32_END or ALU64_END are there to check
617 (DADD): Likewise, but also remove previous comment about
620 2002-02-10 Chris Demetriou <cgd@broadcom.com>
622 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
623 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
624 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
625 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
626 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
627 fields (i.e., add and move commas) so that they more closely
628 match the MIPS ISA documentation opcode partitioning.
630 2002-02-10 Chris Demetriou <cgd@broadcom.com>
632 * mips.igen (ADDI): Print immediate value.
634 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
635 (SLL): Print "nop" specially, and don't run the code
636 that does the shift for the "nop" case.
638 2001-11-17 Fred Fish <fnf@redhat.com>
640 * sim-main.h (float_operation): Move enum declaration outside
641 of _sim_cpu struct declaration.
643 2001-04-12 Jim Blandy <jimb@redhat.com>
645 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
646 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
648 * sim-main.h (COCIDX): Remove definition; this isn't supported by
649 PENDING_FILL, and you can get the intended effect gracefully by
650 calling PENDING_SCHED directly.
652 2001-02-23 Ben Elliston <bje@redhat.com>
654 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
655 already defined elsewhere.
657 2001-02-19 Ben Elliston <bje@redhat.com>
659 * sim-main.h (sim_monitor): Return an int.
660 * interp.c (sim_monitor): Add return values.
661 (signal_exception): Handle error conditions from sim_monitor.
663 2001-02-08 Ben Elliston <bje@redhat.com>
665 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
666 (store_memory): Likewise, pass cia to sim_core_write*.
668 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
670 On advice from Chris G. Demetriou <cgd@sibyte.com>:
671 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
673 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
675 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
676 * Makefile.in: Don't delete *.igen when cleaning directory.
678 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
680 * m16.igen (break): Call SignalException not sim_engine_halt.
682 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
685 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
687 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
689 * mips.igen (MxC1, DMxC1): Fix printf formatting.
691 2000-05-24 Michael Hayes <mhayes@cygnus.com>
693 * mips.igen (do_dmultx): Fix typo.
695 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
697 * configure: Regenerated to track ../common/aclocal.m4 changes.
699 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
701 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
703 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
705 * sim-main.h (GPR_CLEAR): Define macro.
707 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
709 * interp.c (decode_coproc): Output long using %lx and not %s.
711 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
713 * interp.c (sim_open): Sort & extend dummy memory regions for
714 --board=jmr3904 for eCos.
716 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
718 * configure: Regenerated.
720 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
722 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
723 calls, conditional on the simulator being in verbose mode.
725 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
727 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
728 cache don't get ReservedInstruction traps.
730 1999-11-29 Mark Salter <msalter@cygnus.com>
732 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
733 to clear status bits in sdisr register. This is how the hardware works.
735 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
736 being used by cygmon.
738 1999-11-11 Andrew Haley <aph@cygnus.com>
740 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
743 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
745 * mips.igen (MULT): Correct previous mis-applied patch.
747 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
749 * mips.igen (delayslot32): Handle sequence like
750 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
751 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
752 (MULT): Actually pass the third register...
754 1999-09-03 Mark Salter <msalter@cygnus.com>
756 * interp.c (sim_open): Added more memory aliases for additional
757 hardware being touched by cygmon on jmr3904 board.
759 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
761 * configure: Regenerated to track ../common/aclocal.m4 changes.
763 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
765 * interp.c (sim_store_register): Handle case where client - GDB -
766 specifies that a 4 byte register is 8 bytes in size.
767 (sim_fetch_register): Ditto.
769 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
771 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
772 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
773 (idt_monitor_base): Base address for IDT monitor traps.
774 (pmon_monitor_base): Ditto for PMON.
775 (lsipmon_monitor_base): Ditto for LSI PMON.
776 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
777 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
778 (sim_firmware_command): New function.
779 (mips_option_handler): Call it for OPTION_FIRMWARE.
780 (sim_open): Allocate memory for idt_monitor region. If "--board"
781 option was given, add no monitor by default. Add BREAK hooks only if
782 monitors are also there.
784 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
786 * interp.c (sim_monitor): Flush output before reading input.
788 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
790 * tconfig.in (SIM_HANDLES_LMA): Always define.
792 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
794 From Mark Salter <msalter@cygnus.com>:
795 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
796 (sim_open): Add setup for BSP board.
798 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
800 * mips.igen (MULT, MULTU): Add syntax for two operand version.
801 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
802 them as unimplemented.
804 1999-05-08 Felix Lee <flee@cygnus.com>
806 * configure: Regenerated to track ../common/aclocal.m4 changes.
808 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
810 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
812 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
814 * configure.in: Any mips64vr5*-*-* target should have
815 -DTARGET_ENABLE_FR=1.
816 (default_endian): Any mips64vr*el-*-* target should default to
818 * configure: Re-generate.
820 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
822 * mips.igen (ldl): Extend from _16_, not 32.
824 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
826 * interp.c (sim_store_register): Force registers written to by GDB
827 into an un-interpreted state.
829 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
831 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
832 CPU, start periodic background I/O polls.
833 (tx3904sio_poll): New function: periodic I/O poller.
835 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
837 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
839 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
841 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
844 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
846 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
847 (load_word): Call SIM_CORE_SIGNAL hook on error.
848 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
849 starting. For exception dispatching, pass PC instead of NULL_CIA.
850 (decode_coproc): Use COP0_BADVADDR to store faulting address.
851 * sim-main.h (COP0_BADVADDR): Define.
852 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
853 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
854 (_sim_cpu): Add exc_* fields to store register value snapshots.
855 * mips.igen (*): Replace memory-related SignalException* calls
856 with references to SIM_CORE_SIGNAL hook.
858 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
860 * sim-main.c (*): Minor warning cleanups.
862 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
864 * m16.igen (DADDIU5): Correct type-o.
866 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
868 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
871 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
873 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
875 (interp.o): Add dependency on itable.h
876 (oengine.c, gencode): Delete remaining references.
877 (BUILT_SRC_FROM_GEN): Clean up.
879 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
882 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
883 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
885 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
886 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
887 Drop the "64" qualifier to get the HACK generator working.
888 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
889 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
890 qualifier to get the hack generator working.
891 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
893 (DSLLV): Use do_dsllv.
896 (DSRLV): Use do_dsrlv.
897 (BC1): Move *vr4100 to get the HACK generator working.
898 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
899 get the HACK generator working.
900 (MACC) Rename to get the HACK generator working.
901 (DMACC,MACCS,DMACCS): Add the 64.
903 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
905 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
906 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
908 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
910 * mips/interp.c (DEBUG): Cleanups.
912 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
914 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
915 (tx3904sio_tickle): fflush after a stdout character output.
917 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
919 * interp.c (sim_close): Uninstall modules.
921 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
923 * sim-main.h, interp.c (sim_monitor): Change to global
926 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
928 * configure.in (vr4100): Only include vr4100 instructions in
930 * configure: Re-generate.
931 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
933 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
935 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
936 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
939 * configure.in (sim_default_gen, sim_use_gen): Replace with
941 (--enable-sim-igen): Delete config option. Always using IGEN.
942 * configure: Re-generate.
944 * Makefile.in (gencode): Kill, kill, kill.
947 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
949 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
950 bit mips16 igen simulator.
951 * configure: Re-generate.
953 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
954 as part of vr4100 ISA.
955 * vr.igen: Mark all instructions as 64 bit only.
957 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
959 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
962 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
964 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
965 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
966 * configure: Re-generate.
968 * m16.igen (BREAK): Define breakpoint instruction.
969 (JALX32): Mark instruction as mips16 and not r3900.
970 * mips.igen (C.cond.fmt): Fix typo in instruction format.
972 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
974 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
976 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
977 insn as a debug breakpoint.
979 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
981 (PENDING_SCHED): Clean up trace statement.
982 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
983 (PENDING_FILL): Delay write by only one cycle.
984 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
986 * sim-main.c (pending_tick): Clean up trace statements. Add trace
988 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
990 (pending_tick): Move incrementing of index to FOR statement.
991 (pending_tick): Only update PENDING_OUT after a write has occured.
993 * configure.in: Add explicit mips-lsi-* target. Use gencode to
995 * configure: Re-generate.
997 * interp.c (sim_engine_run OLD): Delete explicit call to
998 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1000 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1002 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1003 interrupt level number to match changed SignalExceptionInterrupt
1006 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1008 * interp.c: #include "itable.h" if WITH_IGEN.
1009 (get_insn_name): New function.
1010 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1011 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1013 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1015 * configure: Rebuilt to inhale new common/aclocal.m4.
1017 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1019 * dv-tx3904sio.c: Include sim-assert.h.
1021 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1023 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1024 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1025 Reorganize target-specific sim-hardware checks.
1026 * configure: rebuilt.
1027 * interp.c (sim_open): For tx39 target boards, set
1028 OPERATING_ENVIRONMENT, add tx3904sio devices.
1029 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1030 ROM executables. Install dv-sockser into sim-modules list.
1032 * dv-tx3904irc.c: Compiler warning clean-up.
1033 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1034 frequent hw-trace messages.
1036 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1038 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1040 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1042 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1044 * vr.igen: New file.
1045 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1046 * mips.igen: Define vr4100 model. Include vr.igen.
1047 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1049 * mips.igen (check_mf_hilo): Correct check.
1051 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1053 * sim-main.h (interrupt_event): Add prototype.
1055 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1056 register_ptr, register_value.
1057 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1059 * sim-main.h (tracefh): Make extern.
1061 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1063 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1064 Reduce unnecessarily high timer event frequency.
1065 * dv-tx3904cpu.c: Ditto for interrupt event.
1067 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1069 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1071 (interrupt_event): Made non-static.
1073 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1074 interchange of configuration values for external vs. internal
1077 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1079 * mips.igen (BREAK): Moved code to here for
1080 simulator-reserved break instructions.
1081 * gencode.c (build_instruction): Ditto.
1082 * interp.c (signal_exception): Code moved from here. Non-
1083 reserved instructions now use exception vector, rather
1085 * sim-main.h: Moved magic constants to here.
1087 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1089 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1090 register upon non-zero interrupt event level, clear upon zero
1092 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1093 by passing zero event value.
1094 (*_io_{read,write}_buffer): Endianness fixes.
1095 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1096 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1098 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1099 serial I/O and timer module at base address 0xFFFF0000.
1101 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1103 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1106 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1108 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1110 * configure: Update.
1112 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1114 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1115 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1116 * configure.in: Include tx3904tmr in hw_device list.
1117 * configure: Rebuilt.
1118 * interp.c (sim_open): Instantiate three timer instances.
1119 Fix address typo of tx3904irc instance.
1121 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1123 * interp.c (signal_exception): SystemCall exception now uses
1124 the exception vector.
1126 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1128 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1131 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1133 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1135 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1137 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1139 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1140 sim-main.h. Declare a struct hw_descriptor instead of struct
1141 hw_device_descriptor.
1143 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1145 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1146 right bits and then re-align left hand bytes to correct byte
1147 lanes. Fix incorrect computation in do_store_left when loading
1148 bytes from second word.
1150 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1152 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1153 * interp.c (sim_open): Only create a device tree when HW is
1156 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1157 * interp.c (signal_exception): Ditto.
1159 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1161 * gencode.c: Mark BEGEZALL as LIKELY.
1163 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1165 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1166 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1168 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1170 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1171 modules. Recognize TX39 target with "mips*tx39" pattern.
1172 * configure: Rebuilt.
1173 * sim-main.h (*): Added many macros defining bits in
1174 TX39 control registers.
1175 (SignalInterrupt): Send actual PC instead of NULL.
1176 (SignalNMIReset): New exception type.
1177 * interp.c (board): New variable for future use to identify
1178 a particular board being simulated.
1179 (mips_option_handler,mips_options): Added "--board" option.
1180 (interrupt_event): Send actual PC.
1181 (sim_open): Make memory layout conditional on board setting.
1182 (signal_exception): Initial implementation of hardware interrupt
1183 handling. Accept another break instruction variant for simulator
1185 (decode_coproc): Implement RFE instruction for TX39.
1186 (mips.igen): Decode RFE instruction as such.
1187 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1188 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1189 bbegin to implement memory map.
1190 * dv-tx3904cpu.c: New file.
1191 * dv-tx3904irc.c: New file.
1193 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1195 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1197 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1199 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1200 with calls to check_div_hilo.
1202 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1204 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1205 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1206 Add special r3900 version of do_mult_hilo.
1207 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1208 with calls to check_mult_hilo.
1209 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1210 with calls to check_div_hilo.
1212 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1214 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1215 Document a replacement.
1217 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1219 * interp.c (sim_monitor): Make mon_printf work.
1221 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1223 * sim-main.h (INSN_NAME): New arg `cpu'.
1225 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1227 * configure: Regenerated to track ../common/aclocal.m4 changes.
1229 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1231 * configure: Regenerated to track ../common/aclocal.m4 changes.
1234 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1236 * acconfig.h: New file.
1237 * configure.in: Reverted change of Apr 24; use sinclude again.
1239 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1241 * configure: Regenerated to track ../common/aclocal.m4 changes.
1244 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1246 * configure.in: Don't call sinclude.
1248 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1250 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1252 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1254 * mips.igen (ERET): Implement.
1256 * interp.c (decode_coproc): Return sign-extended EPC.
1258 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1260 * interp.c (signal_exception): Do not ignore Trap.
1261 (signal_exception): On TRAP, restart at exception address.
1262 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1263 (signal_exception): Update.
1264 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1265 so that TRAP instructions are caught.
1267 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1269 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1270 contains HI/LO access history.
1271 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1272 (HIACCESS, LOACCESS): Delete, replace with
1273 (HIHISTORY, LOHISTORY): New macros.
1274 (CHECKHILO): Delete all, moved to mips.igen
1276 * gencode.c (build_instruction): Do not generate checks for
1277 correct HI/LO register usage.
1279 * interp.c (old_engine_run): Delete checks for correct HI/LO
1282 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1283 check_mf_cycles): New functions.
1284 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1285 do_divu, domultx, do_mult, do_multu): Use.
1287 * tx.igen ("madd", "maddu"): Use.
1289 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1291 * mips.igen (DSRAV): Use function do_dsrav.
1292 (SRAV): Use new function do_srav.
1294 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1295 (B): Sign extend 11 bit immediate.
1296 (EXT-B*): Shift 16 bit immediate left by 1.
1297 (ADDIU*): Don't sign extend immediate value.
1299 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1301 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1303 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1306 * mips.igen (delayslot32, nullify_next_insn): New functions.
1307 (m16.igen): Always include.
1308 (do_*): Add more tracing.
1310 * m16.igen (delayslot16): Add NIA argument, could be called by a
1311 32 bit MIPS16 instruction.
1313 * interp.c (ifetch16): Move function from here.
1314 * sim-main.c (ifetch16): To here.
1316 * sim-main.c (ifetch16, ifetch32): Update to match current
1317 implementations of LH, LW.
1318 (signal_exception): Don't print out incorrect hex value of illegal
1321 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1323 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1326 * m16.igen: Implement MIPS16 instructions.
1328 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1329 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1330 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1331 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1332 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1333 bodies of corresponding code from 32 bit insn to these. Also used
1334 by MIPS16 versions of functions.
1336 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1337 (IMEM16): Drop NR argument from macro.
1339 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1341 * Makefile.in (SIM_OBJS): Add sim-main.o.
1343 * sim-main.h (address_translation, load_memory, store_memory,
1344 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1346 (pr_addr, pr_uword64): Declare.
1347 (sim-main.c): Include when H_REVEALS_MODULE_P.
1349 * interp.c (address_translation, load_memory, store_memory,
1350 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1352 * sim-main.c: To here. Fix compilation problems.
1354 * configure.in: Enable inlining.
1355 * configure: Re-config.
1357 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1359 * configure: Regenerated to track ../common/aclocal.m4 changes.
1361 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1363 * mips.igen: Include tx.igen.
1364 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1365 * tx.igen: New file, contains MADD and MADDU.
1367 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1368 the hardwired constant `7'.
1369 (store_memory): Ditto.
1370 (LOADDRMASK): Move definition to sim-main.h.
1372 mips.igen (MTC0): Enable for r3900.
1375 mips.igen (do_load_byte): Delete.
1376 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1377 do_store_right): New functions.
1378 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1380 configure.in: Let the tx39 use igen again.
1383 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1385 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1386 not an address sized quantity. Return zero for cache sizes.
1388 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1390 * mips.igen (r3900): r3900 does not support 64 bit integer
1393 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1395 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1397 * configure : Rebuild.
1399 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1401 * configure: Regenerated to track ../common/aclocal.m4 changes.
1403 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1405 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1407 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1409 * configure: Regenerated to track ../common/aclocal.m4 changes.
1410 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1412 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1414 * configure: Regenerated to track ../common/aclocal.m4 changes.
1416 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1418 * interp.c (Max, Min): Comment out functions. Not yet used.
1420 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1422 * configure: Regenerated to track ../common/aclocal.m4 changes.
1424 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1426 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1427 configurable settings for stand-alone simulator.
1429 * configure.in: Added X11 search, just in case.
1431 * configure: Regenerated.
1433 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1435 * interp.c (sim_write, sim_read, load_memory, store_memory):
1436 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1438 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1440 * sim-main.h (GETFCC): Return an unsigned value.
1442 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1444 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1445 (DADD): Result destination is RD not RT.
1447 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1449 * sim-main.h (HIACCESS, LOACCESS): Always define.
1451 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1453 * interp.c (sim_info): Delete.
1455 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1457 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1458 (mips_option_handler): New argument `cpu'.
1459 (sim_open): Update call to sim_add_option_table.
1461 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1463 * mips.igen (CxC1): Add tracing.
1465 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1467 * sim-main.h (Max, Min): Declare.
1469 * interp.c (Max, Min): New functions.
1471 * mips.igen (BC1): Add tracing.
1473 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1475 * interp.c Added memory map for stack in vr4100
1477 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1479 * interp.c (load_memory): Add missing "break"'s.
1481 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1483 * interp.c (sim_store_register, sim_fetch_register): Pass in
1484 length parameter. Return -1.
1486 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1488 * interp.c: Added hardware init hook, fixed warnings.
1490 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1492 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1494 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1496 * interp.c (ifetch16): New function.
1498 * sim-main.h (IMEM32): Rename IMEM.
1499 (IMEM16_IMMED): Define.
1501 (DELAY_SLOT): Update.
1503 * m16run.c (sim_engine_run): New file.
1505 * m16.igen: All instructions except LB.
1506 (LB): Call do_load_byte.
1507 * mips.igen (do_load_byte): New function.
1508 (LB): Call do_load_byte.
1510 * mips.igen: Move spec for insn bit size and high bit from here.
1511 * Makefile.in (tmp-igen, tmp-m16): To here.
1513 * m16.dc: New file, decode mips16 instructions.
1515 * Makefile.in (SIM_NO_ALL): Define.
1516 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1518 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1520 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1521 point unit to 32 bit registers.
1522 * configure: Re-generate.
1524 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1526 * configure.in (sim_use_gen): Make IGEN the default simulator
1527 generator for generic 32 and 64 bit mips targets.
1528 * configure: Re-generate.
1530 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1532 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1535 * interp.c (sim_fetch_register, sim_store_register): Read/write
1536 FGR from correct location.
1537 (sim_open): Set size of FGR's according to
1538 WITH_TARGET_FLOATING_POINT_BITSIZE.
1540 * sim-main.h (FGR): Store floating point registers in a separate
1543 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1545 * configure: Regenerated to track ../common/aclocal.m4 changes.
1547 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1549 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1551 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1553 * interp.c (pending_tick): New function. Deliver pending writes.
1555 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1556 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1557 it can handle mixed sized quantites and single bits.
1559 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1561 * interp.c (oengine.h): Do not include when building with IGEN.
1562 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1563 (sim_info): Ditto for PROCESSOR_64BIT.
1564 (sim_monitor): Replace ut_reg with unsigned_word.
1565 (*): Ditto for t_reg.
1566 (LOADDRMASK): Define.
1567 (sim_open): Remove defunct check that host FP is IEEE compliant,
1568 using software to emulate floating point.
1569 (value_fpr, ...): Always compile, was conditional on HASFPU.
1571 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1573 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1576 * interp.c (SD, CPU): Define.
1577 (mips_option_handler): Set flags in each CPU.
1578 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1579 (sim_close): Do not clear STATE, deleted anyway.
1580 (sim_write, sim_read): Assume CPU zero's vm should be used for
1582 (sim_create_inferior): Set the PC for all processors.
1583 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1585 (mips16_entry): Pass correct nr of args to store_word, load_word.
1586 (ColdReset): Cold reset all cpu's.
1587 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1588 (sim_monitor, load_memory, store_memory, signal_exception): Use
1589 `CPU' instead of STATE_CPU.
1592 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1595 * sim-main.h (signal_exception): Add sim_cpu arg.
1596 (SignalException*): Pass both SD and CPU to signal_exception.
1597 * interp.c (signal_exception): Update.
1599 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1601 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1602 address_translation): Ditto
1603 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1605 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1607 * configure: Regenerated to track ../common/aclocal.m4 changes.
1609 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1611 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1613 * mips.igen (model): Map processor names onto BFD name.
1615 * sim-main.h (CPU_CIA): Delete.
1616 (SET_CIA, GET_CIA): Define
1618 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1620 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1623 * configure.in (default_endian): Configure a big-endian simulator
1625 * configure: Re-generate.
1627 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1629 * configure: Regenerated to track ../common/aclocal.m4 changes.
1631 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1633 * interp.c (sim_monitor): Handle Densan monitor outbyte
1634 and inbyte functions.
1636 1997-12-29 Felix Lee <flee@cygnus.com>
1638 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1640 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1642 * Makefile.in (tmp-igen): Arrange for $zero to always be
1643 reset to zero after every instruction.
1645 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1647 * configure: Regenerated to track ../common/aclocal.m4 changes.
1650 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1652 * mips.igen (MSUB): Fix to work like MADD.
1653 * gencode.c (MSUB): Similarly.
1655 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1657 * configure: Regenerated to track ../common/aclocal.m4 changes.
1659 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1661 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1663 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1665 * sim-main.h (sim-fpu.h): Include.
1667 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1668 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1669 using host independant sim_fpu module.
1671 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1673 * interp.c (signal_exception): Report internal errors with SIGABRT
1676 * sim-main.h (C0_CONFIG): New register.
1677 (signal.h): No longer include.
1679 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1681 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1683 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1685 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1687 * mips.igen: Tag vr5000 instructions.
1688 (ANDI): Was missing mipsIV model, fix assembler syntax.
1689 (do_c_cond_fmt): New function.
1690 (C.cond.fmt): Handle mips I-III which do not support CC field
1692 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1693 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1695 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1696 vr5000 which saves LO in a GPR separatly.
1698 * configure.in (enable-sim-igen): For vr5000, select vr5000
1699 specific instructions.
1700 * configure: Re-generate.
1702 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1704 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1706 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1707 fmt_uninterpreted_64 bit cases to switch. Convert to
1710 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1712 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1713 as specified in IV3.2 spec.
1714 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1716 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1718 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1719 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1720 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1721 PENDING_FILL versions of instructions. Simplify.
1723 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1725 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1727 (MTHI, MFHI): Disable code checking HI-LO.
1729 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1731 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1733 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1735 * gencode.c (build_mips16_operands): Replace IPC with cia.
1737 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1738 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1740 (UndefinedResult): Replace function with macro/function
1742 (sim_engine_run): Don't save PC in IPC.
1744 * sim-main.h (IPC): Delete.
1747 * interp.c (signal_exception, store_word, load_word,
1748 address_translation, load_memory, store_memory, cache_op,
1749 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1750 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1751 current instruction address - cia - argument.
1752 (sim_read, sim_write): Call address_translation directly.
1753 (sim_engine_run): Rename variable vaddr to cia.
1754 (signal_exception): Pass cia to sim_monitor
1756 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1757 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1758 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1760 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1761 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1764 * interp.c (signal_exception): Pass restart address to
1767 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1768 idecode.o): Add dependency.
1770 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1772 (DELAY_SLOT): Update NIA not PC with branch address.
1773 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1775 * mips.igen: Use CIA not PC in branch calculations.
1776 (illegal): Call SignalException.
1777 (BEQ, ADDIU): Fix assembler.
1779 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1781 * m16.igen (JALX): Was missing.
1783 * configure.in (enable-sim-igen): New configuration option.
1784 * configure: Re-generate.
1786 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1788 * interp.c (load_memory, store_memory): Delete parameter RAW.
1789 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1790 bypassing {load,store}_memory.
1792 * sim-main.h (ByteSwapMem): Delete definition.
1794 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1796 * interp.c (sim_do_command, sim_commands): Delete mips specific
1797 commands. Handled by module sim-options.
1799 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1800 (WITH_MODULO_MEMORY): Define.
1802 * interp.c (sim_info): Delete code printing memory size.
1804 * interp.c (mips_size): Nee sim_size, delete function.
1806 (monitor, monitor_base, monitor_size): Delete global variables.
1807 (sim_open, sim_close): Delete code creating monitor and other
1808 memory regions. Use sim-memopts module, via sim_do_commandf, to
1809 manage memory regions.
1810 (load_memory, store_memory): Use sim-core for memory model.
1812 * interp.c (address_translation): Delete all memory map code
1813 except line forcing 32 bit addresses.
1815 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1817 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1820 * interp.c (logfh, logfile): Delete globals.
1821 (sim_open, sim_close): Delete code opening & closing log file.
1822 (mips_option_handler): Delete -l and -n options.
1823 (OPTION mips_options): Ditto.
1825 * interp.c (OPTION mips_options): Rename option trace to dinero.
1826 (mips_option_handler): Update.
1828 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1830 * interp.c (fetch_str): New function.
1831 (sim_monitor): Rewrite using sim_read & sim_write.
1832 (sim_open): Check magic number.
1833 (sim_open): Write monitor vectors into memory using sim_write.
1834 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1835 (sim_read, sim_write): Simplify - transfer data one byte at a
1837 (load_memory, store_memory): Clarify meaning of parameter RAW.
1839 * sim-main.h (isHOST): Defete definition.
1840 (isTARGET): Mark as depreciated.
1841 (address_translation): Delete parameter HOST.
1843 * interp.c (address_translation): Delete parameter HOST.
1845 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1849 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1850 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1852 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854 * mips.igen: Add model filter field to records.
1856 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1858 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1860 interp.c (sim_engine_run): Do not compile function sim_engine_run
1861 when WITH_IGEN == 1.
1863 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1864 target architecture.
1866 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1867 igen. Replace with configuration variables sim_igen_flags /
1870 * m16.igen: New file. Copy mips16 insns here.
1871 * mips.igen: From here.
1873 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1875 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1877 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1879 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1881 * gencode.c (build_instruction): Follow sim_write's lead in using
1882 BigEndianMem instead of !ByteSwapMem.
1884 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1886 * configure.in (sim_gen): Dependent on target, select type of
1887 generator. Always select old style generator.
1889 configure: Re-generate.
1891 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1893 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1894 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1895 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1896 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1897 SIM_@sim_gen@_*, set by autoconf.
1899 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1901 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1903 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1904 CURRENT_FLOATING_POINT instead.
1906 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1907 (address_translation): Raise exception InstructionFetch when
1908 translation fails and isINSTRUCTION.
1910 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1911 sim_engine_run): Change type of of vaddr and paddr to
1913 (address_translation, prefetch, load_memory, store_memory,
1914 cache_op): Change type of vAddr and pAddr to address_word.
1916 * gencode.c (build_instruction): Change type of vaddr and paddr to
1919 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1921 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1922 macro to obtain result of ALU op.
1924 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1926 * interp.c (sim_info): Call profile_print.
1928 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1930 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1932 * sim-main.h (WITH_PROFILE): Do not define, defined in
1933 common/sim-config.h. Use sim-profile module.
1934 (simPROFILE): Delete defintion.
1936 * interp.c (PROFILE): Delete definition.
1937 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1938 (sim_close): Delete code writing profile histogram.
1939 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1941 (sim_engine_run): Delete code profiling the PC.
1943 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1945 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1947 * interp.c (sim_monitor): Make register pointers of type
1950 * sim-main.h: Make registers of type unsigned_word not
1953 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1955 * interp.c (sync_operation): Rename from SyncOperation, make
1956 global, add SD argument.
1957 (prefetch): Rename from Prefetch, make global, add SD argument.
1958 (decode_coproc): Make global.
1960 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1962 * gencode.c (build_instruction): Generate DecodeCoproc not
1963 decode_coproc calls.
1965 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1966 (SizeFGR): Move to sim-main.h
1967 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1968 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1969 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1971 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1972 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1973 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1974 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1975 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1976 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1978 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1980 (sim-alu.h): Include.
1981 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1982 (sim_cia): Typedef to instruction_address.
1984 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1986 * Makefile.in (interp.o): Rename generated file engine.c to
1991 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1993 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1995 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1997 * gencode.c (build_instruction): For "FPSQRT", output correct
1998 number of arguments to Recip.
2000 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2002 * Makefile.in (interp.o): Depends on sim-main.h
2004 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2006 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2007 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2008 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2009 STATE, DSSTATE): Define
2010 (GPR, FGRIDX, ..): Define.
2012 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2013 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2014 (GPR, FGRIDX, ...): Delete macros.
2016 * interp.c: Update names to match defines from sim-main.h
2018 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2020 * interp.c (sim_monitor): Add SD argument.
2021 (sim_warning): Delete. Replace calls with calls to
2023 (sim_error): Delete. Replace calls with sim_io_error.
2024 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2025 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2026 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2028 (mips_size): Rename from sim_size. Add SD argument.
2030 * interp.c (simulator): Delete global variable.
2031 (callback): Delete global variable.
2032 (mips_option_handler, sim_open, sim_write, sim_read,
2033 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2034 sim_size,sim_monitor): Use sim_io_* not callback->*.
2035 (sim_open): ZALLOC simulator struct.
2036 (PROFILE): Do not define.
2038 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2040 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2041 support.h with corresponding code.
2043 * sim-main.h (word64, uword64), support.h: Move definition to
2045 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2048 * Makefile.in: Update dependencies
2049 * interp.c: Do not include.
2051 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2053 * interp.c (address_translation, load_memory, store_memory,
2054 cache_op): Rename to from AddressTranslation et.al., make global,
2057 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2060 * interp.c (SignalException): Rename to signal_exception, make
2063 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2065 * sim-main.h (SignalException, SignalExceptionInterrupt,
2066 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2067 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2068 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2071 * interp.c, support.h: Use.
2073 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2075 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2076 to value_fpr / store_fpr. Add SD argument.
2077 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2078 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2080 * sim-main.h (ValueFPR, StoreFPR): Define.
2082 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2084 * interp.c (sim_engine_run): Check consistency between configure
2085 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2088 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2089 (mips_fpu): Configure WITH_FLOATING_POINT.
2090 (mips_endian): Configure WITH_TARGET_ENDIAN.
2091 * configure: Update.
2093 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2095 * configure: Regenerated to track ../common/aclocal.m4 changes.
2097 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2099 * configure: Regenerated.
2101 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2103 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2105 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2107 * gencode.c (print_igen_insn_models): Assume certain architectures
2108 include all mips* instructions.
2109 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2112 * Makefile.in (tmp.igen): Add target. Generate igen input from
2115 * gencode.c (FEATURE_IGEN): Define.
2116 (main): Add --igen option. Generate output in igen format.
2117 (process_instructions): Format output according to igen option.
2118 (print_igen_insn_format): New function.
2119 (print_igen_insn_models): New function.
2120 (process_instructions): Only issue warnings and ignore
2121 instructions when no FEATURE_IGEN.
2123 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2125 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2128 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2130 * configure: Regenerated to track ../common/aclocal.m4 changes.
2132 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2134 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2135 SIM_RESERVED_BITS): Delete, moved to common.
2136 (SIM_EXTRA_CFLAGS): Update.
2138 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2140 * configure.in: Configure non-strict memory alignment.
2141 * configure: Regenerated to track ../common/aclocal.m4 changes.
2143 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2145 * configure: Regenerated to track ../common/aclocal.m4 changes.
2147 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2149 * gencode.c (SDBBP,DERET): Added (3900) insns.
2150 (RFE): Turn on for 3900.
2151 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2152 (dsstate): Made global.
2153 (SUBTARGET_R3900): Added.
2154 (CANCELDELAYSLOT): New.
2155 (SignalException): Ignore SystemCall rather than ignore and
2156 terminate. Add DebugBreakPoint handling.
2157 (decode_coproc): New insns RFE, DERET; and new registers Debug
2158 and DEPC protected by SUBTARGET_R3900.
2159 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2161 * Makefile.in,configure.in: Add mips subtarget option.
2162 * configure: Update.
2164 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2166 * gencode.c: Add r3900 (tx39).
2169 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2171 * gencode.c (build_instruction): Don't need to subtract 4 for
2174 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2176 * interp.c: Correct some HASFPU problems.
2178 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180 * configure: Regenerated to track ../common/aclocal.m4 changes.
2182 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184 * interp.c (mips_options): Fix samples option short form, should
2187 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2189 * interp.c (sim_info): Enable info code. Was just returning.
2191 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2193 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2196 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2198 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2200 (build_instruction): Ditto for LL.
2202 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2204 * configure: Regenerated to track ../common/aclocal.m4 changes.
2206 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2208 * configure: Regenerated to track ../common/aclocal.m4 changes.
2211 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2213 * interp.c (sim_open): Add call to sim_analyze_program, update
2216 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2218 * interp.c (sim_kill): Delete.
2219 (sim_create_inferior): Add ABFD argument. Set PC from same.
2220 (sim_load): Move code initializing trap handlers from here.
2221 (sim_open): To here.
2222 (sim_load): Delete, use sim-hload.c.
2224 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2226 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2228 * configure: Regenerated to track ../common/aclocal.m4 changes.
2231 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2233 * interp.c (sim_open): Add ABFD argument.
2234 (sim_load): Move call to sim_config from here.
2235 (sim_open): To here. Check return status.
2237 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2239 * gencode.c (build_instruction): Two arg MADD should
2240 not assign result to $0.
2242 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2244 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2245 * sim/mips/configure.in: Regenerate.
2247 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2249 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2250 signed8, unsigned8 et.al. types.
2252 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2253 hosts when selecting subreg.
2255 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2257 * interp.c (sim_engine_run): Reset the ZERO register to zero
2258 regardless of FEATURE_WARN_ZERO.
2259 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2261 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2263 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2264 (SignalException): For BreakPoints ignore any mode bits and just
2266 (SignalException): Always set the CAUSE register.
2268 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2270 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2271 exception has been taken.
2273 * interp.c: Implement the ERET and mt/f sr instructions.
2275 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2277 * interp.c (SignalException): Don't bother restarting an
2280 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2282 * interp.c (SignalException): Really take an interrupt.
2283 (interrupt_event): Only deliver interrupts when enabled.
2285 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2287 * interp.c (sim_info): Only print info when verbose.
2288 (sim_info) Use sim_io_printf for output.
2290 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2292 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2295 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2297 * interp.c (sim_do_command): Check for common commands if a
2298 simulator specific command fails.
2300 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2302 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2303 and simBE when DEBUG is defined.
2305 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2307 * interp.c (interrupt_event): New function. Pass exception event
2308 onto exception handler.
2310 * configure.in: Check for stdlib.h.
2311 * configure: Regenerate.
2313 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2314 variable declaration.
2315 (build_instruction): Initialize memval1.
2316 (build_instruction): Add UNUSED attribute to byte, bigend,
2318 (build_operands): Ditto.
2320 * interp.c: Fix GCC warnings.
2321 (sim_get_quit_code): Delete.
2323 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2324 * Makefile.in: Ditto.
2325 * configure: Re-generate.
2327 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2329 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2331 * interp.c (mips_option_handler): New function parse argumes using
2333 (myname): Replace with STATE_MY_NAME.
2334 (sim_open): Delete check for host endianness - performed by
2336 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2337 (sim_open): Move much of the initialization from here.
2338 (sim_load): To here. After the image has been loaded and
2340 (sim_open): Move ColdReset from here.
2341 (sim_create_inferior): To here.
2342 (sim_open): Make FP check less dependant on host endianness.
2344 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2346 * interp.c (sim_set_callbacks): Delete.
2348 * interp.c (membank, membank_base, membank_size): Replace with
2349 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2350 (sim_open): Remove call to callback->init. gdb/run do this.
2354 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2356 * interp.c (big_endian_p): Delete, replaced by
2357 current_target_byte_order.
2359 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2361 * interp.c (host_read_long, host_read_word, host_swap_word,
2362 host_swap_long): Delete. Using common sim-endian.
2363 (sim_fetch_register, sim_store_register): Use H2T.
2364 (pipeline_ticks): Delete. Handled by sim-events.
2366 (sim_engine_run): Update.
2368 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2370 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2372 (SignalException): To here. Signal using sim_engine_halt.
2373 (sim_stop_reason): Delete, moved to common.
2375 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2377 * interp.c (sim_open): Add callback argument.
2378 (sim_set_callbacks): Delete SIM_DESC argument.
2381 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2383 * Makefile.in (SIM_OBJS): Add common modules.
2385 * interp.c (sim_set_callbacks): Also set SD callback.
2386 (set_endianness, xfer_*, swap_*): Delete.
2387 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2388 Change to functions using sim-endian macros.
2389 (control_c, sim_stop): Delete, use common version.
2390 (simulate): Convert into.
2391 (sim_engine_run): This function.
2392 (sim_resume): Delete.
2394 * interp.c (simulation): New variable - the simulator object.
2395 (sim_kind): Delete global - merged into simulation.
2396 (sim_load): Cleanup. Move PC assignment from here.
2397 (sim_create_inferior): To here.
2399 * sim-main.h: New file.
2400 * interp.c (sim-main.h): Include.
2402 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2404 * configure: Regenerated to track ../common/aclocal.m4 changes.
2406 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2408 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2410 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2412 * gencode.c (build_instruction): DIV instructions: check
2413 for division by zero and integer overflow before using
2414 host's division operation.
2416 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2418 * Makefile.in (SIM_OBJS): Add sim-load.o.
2419 * interp.c: #include bfd.h.
2420 (target_byte_order): Delete.
2421 (sim_kind, myname, big_endian_p): New static locals.
2422 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2423 after argument parsing. Recognize -E arg, set endianness accordingly.
2424 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2425 load file into simulator. Set PC from bfd.
2426 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2427 (set_endianness): Use big_endian_p instead of target_byte_order.
2429 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2431 * interp.c (sim_size): Delete prototype - conflicts with
2432 definition in remote-sim.h. Correct definition.
2434 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2436 * configure: Regenerated to track ../common/aclocal.m4 changes.
2439 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2441 * interp.c (sim_open): New arg `kind'.
2443 * configure: Regenerated to track ../common/aclocal.m4 changes.
2445 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2447 * configure: Regenerated to track ../common/aclocal.m4 changes.
2449 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2451 * interp.c (sim_open): Set optind to 0 before calling getopt.
2453 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2455 * configure: Regenerated to track ../common/aclocal.m4 changes.
2457 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2459 * interp.c : Replace uses of pr_addr with pr_uword64
2460 where the bit length is always 64 independent of SIM_ADDR.
2461 (pr_uword64) : added.
2463 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2465 * configure: Re-generate.
2467 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2469 * configure: Regenerate to track ../common/aclocal.m4 changes.
2471 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2473 * interp.c (sim_open): New SIM_DESC result. Argument is now
2475 (other sim_*): New SIM_DESC argument.
2477 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2479 * interp.c: Fix printing of addresses for non-64-bit targets.
2480 (pr_addr): Add function to print address based on size.
2482 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2484 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2486 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2488 * gencode.c (build_mips16_operands): Correct computation of base
2489 address for extended PC relative instruction.
2491 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2493 * interp.c (mips16_entry): Add support for floating point cases.
2494 (SignalException): Pass floating point cases to mips16_entry.
2495 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2497 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2499 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2500 and then set the state to fmt_uninterpreted.
2501 (COP_SW): Temporarily set the state to fmt_word while calling
2504 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2506 * gencode.c (build_instruction): The high order may be set in the
2507 comparison flags at any ISA level, not just ISA 4.
2509 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2511 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2512 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2513 * configure.in: sinclude ../common/aclocal.m4.
2514 * configure: Regenerated.
2516 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2518 * configure: Rebuild after change to aclocal.m4.
2520 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2522 * configure configure.in Makefile.in: Update to new configure
2523 scheme which is more compatible with WinGDB builds.
2524 * configure.in: Improve comment on how to run autoconf.
2525 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2526 * Makefile.in: Use autoconf substitution to install common
2529 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2531 * gencode.c (build_instruction): Use BigEndianCPU instead of
2534 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2536 * interp.c (sim_monitor): Make output to stdout visible in
2537 wingdb's I/O log window.
2539 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2541 * support.h: Undo previous change to SIGTRAP
2544 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2546 * interp.c (store_word, load_word): New static functions.
2547 (mips16_entry): New static function.
2548 (SignalException): Look for mips16 entry and exit instructions.
2549 (simulate): Use the correct index when setting fpr_state after
2550 doing a pending move.
2552 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2554 * interp.c: Fix byte-swapping code throughout to work on
2555 both little- and big-endian hosts.
2557 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2559 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2560 with gdb/config/i386/xm-windows.h.
2562 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2564 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2565 that messes up arithmetic shifts.
2567 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2569 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2570 SIGTRAP and SIGQUIT for _WIN32.
2572 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2574 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2575 force a 64 bit multiplication.
2576 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2577 destination register is 0, since that is the default mips16 nop
2580 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2582 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2583 (build_endian_shift): Don't check proc64.
2584 (build_instruction): Always set memval to uword64. Cast op2 to
2585 uword64 when shifting it left in memory instructions. Always use
2586 the same code for stores--don't special case proc64.
2588 * gencode.c (build_mips16_operands): Fix base PC value for PC
2590 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2592 * interp.c (simJALDELAYSLOT): Define.
2593 (JALDELAYSLOT): Define.
2594 (INDELAYSLOT, INJALDELAYSLOT): Define.
2595 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2597 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2599 * interp.c (sim_open): add flush_cache as a PMON routine
2600 (sim_monitor): handle flush_cache by ignoring it
2602 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2604 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2606 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2607 (BigEndianMem): Rename to ByteSwapMem and change sense.
2608 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2609 BigEndianMem references to !ByteSwapMem.
2610 (set_endianness): New function, with prototype.
2611 (sim_open): Call set_endianness.
2612 (sim_info): Use simBE instead of BigEndianMem.
2613 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2614 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2615 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2616 ifdefs, keeping the prototype declaration.
2617 (swap_word): Rewrite correctly.
2618 (ColdReset): Delete references to CONFIG. Delete endianness related
2619 code; moved to set_endianness.
2621 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2623 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2624 * interp.c (CHECKHILO): Define away.
2625 (simSIGINT): New macro.
2626 (membank_size): Increase from 1MB to 2MB.
2627 (control_c): New function.
2628 (sim_resume): Rename parameter signal to signal_number. Add local
2629 variable prev. Call signal before and after simulate.
2630 (sim_stop_reason): Add simSIGINT support.
2631 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2633 (sim_warning): Delete call to SignalException. Do call printf_filtered
2635 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2636 a call to sim_warning.
2638 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2640 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2641 16 bit instructions.
2643 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2645 Add support for mips16 (16 bit MIPS implementation):
2646 * gencode.c (inst_type): Add mips16 instruction encoding types.
2647 (GETDATASIZEINSN): Define.
2648 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2649 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2651 (MIPS16_DECODE): New table, for mips16 instructions.
2652 (bitmap_val): New static function.
2653 (struct mips16_op): Define.
2654 (mips16_op_table): New table, for mips16 operands.
2655 (build_mips16_operands): New static function.
2656 (process_instructions): If PC is odd, decode a mips16
2657 instruction. Break out instruction handling into new
2658 build_instruction function.
2659 (build_instruction): New static function, broken out of
2660 process_instructions. Check modifiers rather than flags for SHIFT
2661 bit count and m[ft]{hi,lo} direction.
2662 (usage): Pass program name to fprintf.
2663 (main): Remove unused variable this_option_optind. Change
2664 ``*loptarg++'' to ``loptarg++''.
2665 (my_strtoul): Parenthesize && within ||.
2666 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2667 (simulate): If PC is odd, fetch a 16 bit instruction, and
2668 increment PC by 2 rather than 4.
2669 * configure.in: Add case for mips16*-*-*.
2670 * configure: Rebuild.
2672 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2674 * interp.c: Allow -t to enable tracing in standalone simulator.
2675 Fix garbage output in trace file and error messages.
2677 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2679 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2680 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2681 * configure.in: Simplify using macros in ../common/aclocal.m4.
2682 * configure: Regenerated.
2683 * tconfig.in: New file.
2685 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2687 * interp.c: Fix bugs in 64-bit port.
2688 Use ansi function declarations for msvc compiler.
2689 Initialize and test file pointer in trace code.
2690 Prevent duplicate definition of LAST_EMED_REGNUM.
2692 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2694 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2696 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2698 * interp.c (SignalException): Check for explicit terminating
2700 * gencode.c: Pass instruction value through SignalException()
2701 calls for Trap, Breakpoint and Syscall.
2703 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2705 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2706 only used on those hosts that provide it.
2707 * configure.in: Add sqrt() to list of functions to be checked for.
2708 * config.in: Re-generated.
2709 * configure: Re-generated.
2711 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2713 * gencode.c (process_instructions): Call build_endian_shift when
2714 expanding STORE RIGHT, to fix swr.
2715 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2716 clear the high bits.
2717 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2718 Fix float to int conversions to produce signed values.
2720 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2722 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2723 (process_instructions): Correct handling of nor instruction.
2724 Correct shift count for 32 bit shift instructions. Correct sign
2725 extension for arithmetic shifts to not shift the number of bits in
2726 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2727 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2729 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2730 It's OK to have a mult follow a mult. What's not OK is to have a
2731 mult follow an mfhi.
2732 (Convert): Comment out incorrect rounding code.
2734 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2736 * interp.c (sim_monitor): Improved monitor printf
2737 simulation. Tidied up simulator warnings, and added "--log" option
2738 for directing warning message output.
2739 * gencode.c: Use sim_warning() rather than WARNING macro.
2741 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2743 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2744 getopt1.o, rather than on gencode.c. Link objects together.
2745 Don't link against -liberty.
2746 (gencode.o, getopt.o, getopt1.o): New targets.
2747 * gencode.c: Include <ctype.h> and "ansidecl.h".
2748 (AND): Undefine after including "ansidecl.h".
2749 (ULONG_MAX): Define if not defined.
2750 (OP_*): Don't define macros; now defined in opcode/mips.h.
2751 (main): Call my_strtoul rather than strtoul.
2752 (my_strtoul): New static function.
2754 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2756 * gencode.c (process_instructions): Generate word64 and uword64
2757 instead of `long long' and `unsigned long long' data types.
2758 * interp.c: #include sysdep.h to get signals, and define default
2760 * (Convert): Work around for Visual-C++ compiler bug with type
2762 * support.h: Make things compile under Visual-C++ by using
2763 __int64 instead of `long long'. Change many refs to long long
2764 into word64/uword64 typedefs.
2766 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2768 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2769 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2771 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2772 (AC_PROG_INSTALL): Added.
2773 (AC_PROG_CC): Moved to before configure.host call.
2774 * configure: Rebuilt.
2776 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2778 * configure.in: Define @SIMCONF@ depending on mips target.
2779 * configure: Rebuild.
2780 * Makefile.in (run): Add @SIMCONF@ to control simulator
2782 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2783 * interp.c: Remove some debugging, provide more detailed error
2784 messages, update memory accesses to use LOADDRMASK.
2786 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2788 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2789 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2791 * configure: Rebuild.
2792 * config.in: New file, generated by autoheader.
2793 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2794 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2795 HAVE_ANINT and HAVE_AINT, as appropriate.
2796 * Makefile.in (run): Use @LIBS@ rather than -lm.
2797 (interp.o): Depend upon config.h.
2798 (Makefile): Just rebuild Makefile.
2799 (clean): Remove stamp-h.
2800 (mostlyclean): Make the same as clean, not as distclean.
2801 (config.h, stamp-h): New targets.
2803 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2805 * interp.c (ColdReset): Fix boolean test. Make all simulator
2808 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2810 * interp.c (xfer_direct_word, xfer_direct_long,
2811 swap_direct_word, swap_direct_long, xfer_big_word,
2812 xfer_big_long, xfer_little_word, xfer_little_long,
2813 swap_word,swap_long): Added.
2814 * interp.c (ColdReset): Provide function indirection to
2815 host<->simulated_target transfer routines.
2816 * interp.c (sim_store_register, sim_fetch_register): Updated to
2817 make use of indirected transfer routines.
2819 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2821 * gencode.c (process_instructions): Ensure FP ABS instruction
2823 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2824 system call support.
2826 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2828 * interp.c (sim_do_command): Complain if callback structure not
2831 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2833 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2834 support for Sun hosts.
2835 * Makefile.in (gencode): Ensure the host compiler and libraries
2836 used for cross-hosted build.
2838 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2840 * interp.c, gencode.c: Some more (TODO) tidying.
2842 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2844 * gencode.c, interp.c: Replaced explicit long long references with
2845 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2846 * support.h (SET64LO, SET64HI): Macros added.
2848 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2850 * configure: Regenerate with autoconf 2.7.
2852 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2854 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2855 * support.h: Remove superfluous "1" from #if.
2856 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2858 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2860 * interp.c (StoreFPR): Control UndefinedResult() call on
2861 WARN_RESULT manifest.
2863 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2865 * gencode.c: Tidied instruction decoding, and added FP instruction
2868 * interp.c: Added dineroIII, and BSD profiling support. Also
2869 run-time FP handling.
2871 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2873 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2874 gencode.c, interp.c, support.h: created.