1 2015-03-14 Mike Frysinger <vapier@gentoo.org>
3 * configure.ac (AC_CHECK_HEADERS): Delete.
4 * aclocal.m4, configure: Regenerate.
6 2014-08-19 Alan Modra <amodra@gmail.com>
8 * configure: Regenerate.
10 2014-08-15 Roland McGrath <mcgrathr@google.com>
12 * configure: Regenerate.
13 * config.in: Regenerate.
15 2014-03-04 Mike Frysinger <vapier@gentoo.org>
17 * configure: Regenerate.
19 2013-09-23 Alan Modra <amodra@gmail.com>
21 * configure: Regenerate.
23 2013-06-03 Mike Frysinger <vapier@gentoo.org>
25 * aclocal.m4, configure: Regenerate.
27 2013-05-10 Freddie Chopin <freddie_chopin@op.pl>
31 2013-03-26 Mike Frysinger <vapier@gentoo.org>
33 * configure: Regenerate.
35 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
37 * configure.ac: Address use of dv-sockser.o.
38 * tconfig.in: Conditionalize use of dv_sockser_install.
39 * configure: Regenerated.
40 * config.in: Regenerated.
42 2012-10-04 Chao-ying Fu <fu@mips.com>
43 Steve Ellcey <sellcey@mips.com>
45 * mips/mips3264r2.igen (rdhwr): New.
47 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
49 * configure.ac: Always link against dv-sockser.o.
50 * configure: Regenerate.
52 2012-06-15 Joel Brobecker <brobecker@adacore.com>
54 * config.in, configure: Regenerate.
56 2012-05-18 Nick Clifton <nickc@redhat.com>
59 * interp.c: Include config.h before system header files.
61 2012-03-24 Mike Frysinger <vapier@gentoo.org>
63 * aclocal.m4, config.in, configure: Regenerate.
65 2011-12-03 Mike Frysinger <vapier@gentoo.org>
67 * aclocal.m4: New file.
68 * configure: Regenerate.
70 2011-10-19 Mike Frysinger <vapier@gentoo.org>
72 * configure: Regenerate after common/acinclude.m4 update.
74 2011-10-17 Mike Frysinger <vapier@gentoo.org>
76 * configure.ac: Change include to common/acinclude.m4.
78 2011-10-17 Mike Frysinger <vapier@gentoo.org>
80 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
81 call. Replace common.m4 include with SIM_AC_COMMON.
82 * configure: Regenerate.
84 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
86 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
88 (tmp-mach-multi): Exit early when igen fails.
90 2011-07-05 Mike Frysinger <vapier@gentoo.org>
92 * interp.c (sim_do_command): Delete.
94 2011-02-14 Mike Frysinger <vapier@gentoo.org>
96 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
97 (tx3904sio_fifo_reset): Likewise.
98 * interp.c (sim_monitor): Likewise.
100 2010-04-14 Mike Frysinger <vapier@gentoo.org>
102 * interp.c (sim_write): Add const to buffer arg.
104 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
106 * interp.c: Don't include sysdep.h
108 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
110 * configure: Regenerate.
112 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
114 * config.in: Regenerate.
115 * configure: Likewise.
117 * configure: Regenerate.
119 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
121 * configure: Regenerate to track ../common/common.m4 changes.
124 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
125 Daniel Jacobowitz <dan@codesourcery.com>
126 Joseph Myers <joseph@codesourcery.com>
128 * configure: Regenerate.
130 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
132 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
133 that unconditionally allows fmt_ps.
134 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
135 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
136 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
137 filter from 64,f to 32,f.
138 (PREFX): Change filter from 64 to 32.
139 (LDXC1, LUXC1): Provide separate mips32r2 implementations
140 that use do_load_double instead of do_load. Make both LUXC1
141 versions unpredictable if SizeFGR () != 64.
142 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
143 instead of do_store. Remove unused variable. Make both SUXC1
144 versions unpredictable if SizeFGR () != 64.
146 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
148 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
149 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
150 shifts for that case.
152 2007-09-04 Nick Clifton <nickc@redhat.com>
154 * interp.c (options enum): Add OPTION_INFO_MEMORY.
155 (display_mem_info): New static variable.
156 (mips_option_handler): Handle OPTION_INFO_MEMORY.
157 (mips_options): Add info-memory and memory-info.
158 (sim_open): After processing the command line and board
159 specification, check display_mem_info. If it is set then
160 call the real handler for the --memory-info command line
163 2007-08-24 Joel Brobecker <brobecker@adacore.com>
165 * configure.ac: Change license of multi-run.c to GPL version 3.
166 * configure: Regenerate.
168 2007-06-28 Richard Sandiford <richard@codesourcery.com>
170 * configure.ac, configure: Revert last patch.
172 2007-06-26 Richard Sandiford <richard@codesourcery.com>
174 * configure.ac (sim_mipsisa3264_configs): New variable.
175 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
176 every configuration support all four targets, using the triplet to
177 determine the default.
178 * configure: Regenerate.
180 2007-06-25 Richard Sandiford <richard@codesourcery.com>
182 * Makefile.in (m16run.o): New rule.
184 2007-05-15 Thiemo Seufer <ths@mips.com>
186 * mips3264r2.igen (DSHD): Fix compile warning.
188 2007-05-14 Thiemo Seufer <ths@mips.com>
190 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
191 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
192 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
193 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
196 2007-03-01 Thiemo Seufer <ths@mips.com>
198 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
201 2007-02-20 Thiemo Seufer <ths@mips.com>
203 * dsp.igen: Update copyright notice.
204 * dsp2.igen: Fix copyright notice.
206 2007-02-20 Thiemo Seufer <ths@mips.com>
207 Chao-Ying Fu <fu@mips.com>
209 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
210 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
211 Add dsp2 to sim_igen_machine.
212 * configure: Regenerate.
213 * dsp.igen (do_ph_op): Add MUL support when op = 2.
214 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
215 (mulq_rs.ph): Use do_ph_mulq.
216 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
217 * mips.igen: Add dsp2 model and include dsp2.igen.
218 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
219 for *mips32r2, *mips64r2, *dsp.
220 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
221 for *mips32r2, *mips64r2, *dsp2.
222 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
224 2007-02-19 Thiemo Seufer <ths@mips.com>
225 Nigel Stephens <nigel@mips.com>
227 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
228 jumps with hazard barrier.
230 2007-02-19 Thiemo Seufer <ths@mips.com>
231 Nigel Stephens <nigel@mips.com>
233 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
234 after each call to sim_io_write.
236 2007-02-19 Thiemo Seufer <ths@mips.com>
237 Nigel Stephens <nigel@mips.com>
239 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
240 supported by this simulator.
241 (decode_coproc): Recognise additional CP0 Config registers
244 2007-02-19 Thiemo Seufer <ths@mips.com>
245 Nigel Stephens <nigel@mips.com>
246 David Ung <davidu@mips.com>
248 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
249 uninterpreted formats. If fmt is one of the uninterpreted types
250 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
251 fmt_word, and fmt_uninterpreted_64 like fmt_long.
252 (store_fpr): When writing an invalid odd register, set the
253 matching even register to fmt_unknown, not the following register.
254 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
255 the the memory window at offset 0 set by --memory-size command
257 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
259 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
261 (sim_monitor): When returning the memory size to the MIPS
262 application, use the value in STATE_MEM_SIZE, not an arbitrary
264 (cop_lw): Don' mess around with FPR_STATE, just pass
265 fmt_uninterpreted_32 to StoreFPR.
267 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
269 * mips.igen (not_word_value): Single version for mips32, mips64
272 2007-02-19 Thiemo Seufer <ths@mips.com>
273 Nigel Stephens <nigel@mips.com>
275 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
278 2007-02-17 Thiemo Seufer <ths@mips.com>
280 * configure.ac (mips*-sde-elf*): Move in front of generic machine
282 * configure: Regenerate.
284 2007-02-17 Thiemo Seufer <ths@mips.com>
286 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
287 Add mdmx to sim_igen_machine.
288 (mipsisa64*-*-*): Likewise. Remove dsp.
289 (mipsisa32*-*-*): Remove dsp.
290 * configure: Regenerate.
292 2007-02-13 Thiemo Seufer <ths@mips.com>
294 * configure.ac: Add mips*-sde-elf* target.
295 * configure: Regenerate.
297 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
299 * acconfig.h: Remove.
300 * config.in, configure: Regenerate.
302 2006-11-07 Thiemo Seufer <ths@mips.com>
304 * dsp.igen (do_w_op): Fix compiler warning.
306 2006-08-29 Thiemo Seufer <ths@mips.com>
307 David Ung <davidu@mips.com>
309 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
311 * configure: Regenerate.
312 * mips.igen (model): Add smartmips.
313 (MADDU): Increment ACX if carry.
314 (do_mult): Clear ACX.
315 (ROR,RORV): Add smartmips.
316 (include): Include smartmips.igen.
317 * sim-main.h (ACX): Set to REGISTERS[89].
318 * smartmips.igen: New file.
320 2006-08-29 Thiemo Seufer <ths@mips.com>
321 David Ung <davidu@mips.com>
323 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
324 mips3264r2.igen. Add missing dependency rules.
325 * m16e.igen: Support for mips16e save/restore instructions.
327 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
329 * configure: Regenerated.
331 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
333 * configure: Regenerated.
335 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
337 * configure: Regenerated.
339 2006-05-15 Chao-ying Fu <fu@mips.com>
341 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
343 2006-04-18 Nick Clifton <nickc@redhat.com>
345 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
348 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
350 * configure: Regenerate.
352 2005-12-14 Chao-ying Fu <fu@mips.com>
354 * Makefile.in (SIM_OBJS): Add dsp.o.
355 (dsp.o): New dependency.
356 (IGEN_INCLUDE): Add dsp.igen.
357 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
358 mipsisa64*-*-*): Add dsp to sim_igen_machine.
359 * configure: Regenerate.
360 * mips.igen: Add dsp model and include dsp.igen.
361 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
362 because these instructions are extended in DSP ASE.
363 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
364 adding 6 DSP accumulator registers and 1 DSP control register.
365 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
366 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
367 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
368 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
369 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
370 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
371 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
372 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
373 DSPCR_CCOND_SMASK): New define.
374 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
375 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
377 2005-07-08 Ian Lance Taylor <ian@airs.com>
379 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
381 2005-06-16 David Ung <davidu@mips.com>
382 Nigel Stephens <nigel@mips.com>
384 * mips.igen: New mips16e model and include m16e.igen.
385 (check_u64): Add mips16e tag.
386 * m16e.igen: New file for MIPS16e instructions.
387 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
388 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
390 * configure: Regenerate.
392 2005-05-26 David Ung <davidu@mips.com>
394 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
395 tags to all instructions which are applicable to the new ISAs.
396 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
398 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
400 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
402 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
403 * configure: Regenerate.
405 2005-03-23 Mark Kettenis <kettenis@gnu.org>
407 * configure: Regenerate.
409 2005-01-14 Andrew Cagney <cagney@gnu.org>
411 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
412 explicit call to AC_CONFIG_HEADER.
413 * configure: Regenerate.
415 2005-01-12 Andrew Cagney <cagney@gnu.org>
417 * configure.ac: Update to use ../common/common.m4.
418 * configure: Re-generate.
420 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
422 * configure: Regenerated to track ../common/aclocal.m4 changes.
424 2005-01-07 Andrew Cagney <cagney@gnu.org>
426 * configure.ac: Rename configure.in, require autoconf 2.59.
427 * configure: Re-generate.
429 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
431 * configure: Regenerate for ../common/aclocal.m4 update.
433 2004-09-24 Monika Chaddha <monika@acmet.com>
435 Committed by Andrew Cagney.
436 * m16.igen (CMP, CMPI): Fix assembler.
438 2004-08-18 Chris Demetriou <cgd@broadcom.com>
440 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
441 * configure: Regenerate.
443 2004-06-25 Chris Demetriou <cgd@broadcom.com>
445 * configure.in (sim_m16_machine): Include mipsIII.
446 * configure: Regenerate.
448 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
450 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
452 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
454 2004-04-10 Chris Demetriou <cgd@broadcom.com>
456 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
458 2004-04-09 Chris Demetriou <cgd@broadcom.com>
460 * mips.igen (check_fmt): Remove.
461 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
462 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
463 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
464 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
465 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
466 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
467 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
468 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
469 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
470 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
472 2004-04-09 Chris Demetriou <cgd@broadcom.com>
474 * sb1.igen (check_sbx): New function.
475 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
477 2004-03-29 Chris Demetriou <cgd@broadcom.com>
478 Richard Sandiford <rsandifo@redhat.com>
480 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
481 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
482 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
483 separate implementations for mipsIV and mipsV. Use new macros to
484 determine whether the restrictions apply.
486 2004-01-19 Chris Demetriou <cgd@broadcom.com>
488 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
489 (check_mult_hilo): Improve comments.
490 (check_div_hilo): Likewise. Also, fork off a new version
491 to handle mips32/mips64 (since there are no hazards to check
494 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
496 * mips.igen (do_dmultx): Fix check for negative operands.
498 2003-05-16 Ian Lance Taylor <ian@airs.com>
500 * Makefile.in (SHELL): Make sure this is defined.
501 (various): Use $(SHELL) whenever we invoke move-if-change.
503 2003-05-03 Chris Demetriou <cgd@broadcom.com>
505 * cp1.c: Tweak attribution slightly.
508 * mdmx.igen: Likewise.
509 * mips3d.igen: Likewise.
510 * sb1.igen: Likewise.
512 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
514 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
517 2003-02-27 Andrew Cagney <cagney@redhat.com>
519 * interp.c (sim_open): Rename _bfd to bfd.
520 (sim_create_inferior): Ditto.
522 2003-01-14 Chris Demetriou <cgd@broadcom.com>
524 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
526 2003-01-14 Chris Demetriou <cgd@broadcom.com>
528 * mips.igen (EI, DI): Remove.
530 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
532 * Makefile.in (tmp-run-multi): Fix mips16 filter.
534 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
535 Andrew Cagney <ac131313@redhat.com>
536 Gavin Romig-Koch <gavin@redhat.com>
537 Graydon Hoare <graydon@redhat.com>
538 Aldy Hernandez <aldyh@redhat.com>
539 Dave Brolley <brolley@redhat.com>
540 Chris Demetriou <cgd@broadcom.com>
542 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
543 (sim_mach_default): New variable.
544 (mips64vr-*-*, mips64vrel-*-*): New configurations.
545 Add a new simulator generator, MULTI.
546 * configure: Regenerate.
547 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
548 (multi-run.o): New dependency.
549 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
550 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
551 (tmp-multi): Combine them.
552 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
553 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
554 (distclean-extra): New rule.
555 * sim-main.h: Include bfd.h.
556 (MIPS_MACH): New macro.
557 * mips.igen (vr4120, vr5400, vr5500): New models.
558 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
559 * vr.igen: Replace with new version.
561 2003-01-04 Chris Demetriou <cgd@broadcom.com>
563 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
564 * configure: Regenerate.
566 2002-12-31 Chris Demetriou <cgd@broadcom.com>
568 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
569 * mips.igen: Remove all invocations of check_branch_bug and
572 2002-12-16 Chris Demetriou <cgd@broadcom.com>
574 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
576 2002-07-30 Chris Demetriou <cgd@broadcom.com>
578 * mips.igen (do_load_double, do_store_double): New functions.
579 (LDC1, SDC1): Rename to...
580 (LDC1b, SDC1b): respectively.
581 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
583 2002-07-29 Michael Snyder <msnyder@redhat.com>
585 * cp1.c (fp_recip2): Modify initialization expression so that
586 GCC will recognize it as constant.
588 2002-06-18 Chris Demetriou <cgd@broadcom.com>
590 * mdmx.c (SD_): Delete.
591 (Unpredictable): Re-define, for now, to directly invoke
592 unpredictable_action().
593 (mdmx_acc_op): Fix error in .ob immediate handling.
595 2002-06-18 Andrew Cagney <cagney@redhat.com>
597 * interp.c (sim_firmware_command): Initialize `address'.
599 2002-06-16 Andrew Cagney <ac131313@redhat.com>
601 * configure: Regenerated to track ../common/aclocal.m4 changes.
603 2002-06-14 Chris Demetriou <cgd@broadcom.com>
604 Ed Satterthwaite <ehs@broadcom.com>
606 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
607 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
608 * mips.igen: Include mips3d.igen.
609 (mips3d): New model name for MIPS-3D ASE instructions.
610 (CVT.W.fmt): Don't use this instruction for word (source) format
612 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
613 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
614 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
615 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
616 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
617 (RSquareRoot1, RSquareRoot2): New macros.
618 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
619 (fp_rsqrt2): New functions.
620 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
621 * configure: Regenerate.
623 2002-06-13 Chris Demetriou <cgd@broadcom.com>
624 Ed Satterthwaite <ehs@broadcom.com>
626 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
627 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
628 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
629 (convert): Note that this function is not used for paired-single
631 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
632 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
633 (check_fmt_p): Enable paired-single support.
634 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
635 (PUU.PS): New instructions.
636 (CVT.S.fmt): Don't use this instruction for paired-single format
638 * sim-main.h (FP_formats): New value 'fmt_ps.'
639 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
640 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
642 2002-06-12 Chris Demetriou <cgd@broadcom.com>
644 * mips.igen: Fix formatting of function calls in
647 2002-06-12 Chris Demetriou <cgd@broadcom.com>
649 * mips.igen (MOVN, MOVZ): Trace result.
650 (TNEI): Print "tnei" as the opcode name in traces.
651 (CEIL.W): Add disassembly string for traces.
652 (RSQRT.fmt): Make location of disassembly string consistent
653 with other instructions.
655 2002-06-12 Chris Demetriou <cgd@broadcom.com>
657 * mips.igen (X): Delete unused function.
659 2002-06-08 Andrew Cagney <cagney@redhat.com>
661 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
663 2002-06-07 Chris Demetriou <cgd@broadcom.com>
664 Ed Satterthwaite <ehs@broadcom.com>
666 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
667 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
668 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
669 (fp_nmsub): New prototypes.
670 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
671 (NegMultiplySub): New defines.
672 * mips.igen (RSQRT.fmt): Use RSquareRoot().
673 (MADD.D, MADD.S): Replace with...
674 (MADD.fmt): New instruction.
675 (MSUB.D, MSUB.S): Replace with...
676 (MSUB.fmt): New instruction.
677 (NMADD.D, NMADD.S): Replace with...
678 (NMADD.fmt): New instruction.
679 (NMSUB.D, MSUB.S): Replace with...
680 (NMSUB.fmt): New instruction.
682 2002-06-07 Chris Demetriou <cgd@broadcom.com>
683 Ed Satterthwaite <ehs@broadcom.com>
685 * cp1.c: Fix more comment spelling and formatting.
686 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
687 (denorm_mode): New function.
688 (fpu_unary, fpu_binary): Round results after operation, collect
689 status from rounding operations, and update the FCSR.
690 (convert): Collect status from integer conversions and rounding
691 operations, and update the FCSR. Adjust NaN values that result
692 from conversions. Convert to use sim_io_eprintf rather than
693 fprintf, and remove some debugging code.
694 * cp1.h (fenr_FS): New define.
696 2002-06-07 Chris Demetriou <cgd@broadcom.com>
698 * cp1.c (convert): Remove unusable debugging code, and move MIPS
699 rounding mode to sim FP rounding mode flag conversion code into...
700 (rounding_mode): New function.
702 2002-06-07 Chris Demetriou <cgd@broadcom.com>
704 * cp1.c: Clean up formatting of a few comments.
705 (value_fpr): Reformat switch statement.
707 2002-06-06 Chris Demetriou <cgd@broadcom.com>
708 Ed Satterthwaite <ehs@broadcom.com>
711 * sim-main.h: Include cp1.h.
712 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
713 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
714 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
715 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
716 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
717 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
718 * cp1.c: Don't include sim-fpu.h; already included by
719 sim-main.h. Clean up formatting of some comments.
720 (NaN, Equal, Less): Remove.
721 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
722 (fp_cmp): New functions.
723 * mips.igen (do_c_cond_fmt): Remove.
724 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
725 Compare. Add result tracing.
726 (CxC1): Remove, replace with...
727 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
728 (DMxC1): Remove, replace with...
729 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
730 (MxC1): Remove, replace with...
731 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
733 2002-06-04 Chris Demetriou <cgd@broadcom.com>
735 * sim-main.h (FGRIDX): Remove, replace all uses with...
736 (FGR_BASE): New macro.
737 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
738 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
739 (NR_FGR, FGR): Likewise.
740 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
741 * mips.igen: Likewise.
743 2002-06-04 Chris Demetriou <cgd@broadcom.com>
745 * cp1.c: Add an FSF Copyright notice to this file.
747 2002-06-04 Chris Demetriou <cgd@broadcom.com>
748 Ed Satterthwaite <ehs@broadcom.com>
750 * cp1.c (Infinity): Remove.
751 * sim-main.h (Infinity): Likewise.
753 * cp1.c (fp_unary, fp_binary): New functions.
754 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
755 (fp_sqrt): New functions, implemented in terms of the above.
756 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
757 (Recip, SquareRoot): Remove (replaced by functions above).
758 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
759 (fp_recip, fp_sqrt): New prototypes.
760 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
761 (Recip, SquareRoot): Replace prototypes with #defines which
762 invoke the functions above.
764 2002-06-03 Chris Demetriou <cgd@broadcom.com>
766 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
767 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
768 file, remove PARAMS from prototypes.
769 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
770 simulator state arguments.
771 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
772 pass simulator state arguments.
773 * cp1.c (SD): Redefine as CPU_STATE(cpu).
774 (store_fpr, convert): Remove 'sd' argument.
775 (value_fpr): Likewise. Convert to use 'SD' instead.
777 2002-06-03 Chris Demetriou <cgd@broadcom.com>
779 * cp1.c (Min, Max): Remove #if 0'd functions.
780 * sim-main.h (Min, Max): Remove.
782 2002-06-03 Chris Demetriou <cgd@broadcom.com>
784 * cp1.c: fix formatting of switch case and default labels.
785 * interp.c: Likewise.
786 * sim-main.c: Likewise.
788 2002-06-03 Chris Demetriou <cgd@broadcom.com>
790 * cp1.c: Clean up comments which describe FP formats.
791 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
793 2002-06-03 Chris Demetriou <cgd@broadcom.com>
794 Ed Satterthwaite <ehs@broadcom.com>
796 * configure.in (mipsisa64sb1*-*-*): New target for supporting
797 Broadcom SiByte SB-1 processor configurations.
798 * configure: Regenerate.
799 * sb1.igen: New file.
800 * mips.igen: Include sb1.igen.
802 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
803 * mdmx.igen: Add "sb1" model to all appropriate functions and
805 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
806 (ob_func, ob_acc): Reference the above.
807 (qh_acc): Adjust to keep the same size as ob_acc.
808 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
809 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
811 2002-06-03 Chris Demetriou <cgd@broadcom.com>
813 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
815 2002-06-02 Chris Demetriou <cgd@broadcom.com>
816 Ed Satterthwaite <ehs@broadcom.com>
818 * mips.igen (mdmx): New (pseudo-)model.
819 * mdmx.c, mdmx.igen: New files.
820 * Makefile.in (SIM_OBJS): Add mdmx.o.
821 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
823 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
824 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
825 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
826 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
827 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
828 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
829 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
830 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
831 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
832 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
833 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
834 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
835 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
836 (qh_fmtsel): New macros.
837 (_sim_cpu): New member "acc".
838 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
839 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
841 2002-05-01 Chris Demetriou <cgd@broadcom.com>
843 * interp.c: Use 'deprecated' rather than 'depreciated.'
844 * sim-main.h: Likewise.
846 2002-05-01 Chris Demetriou <cgd@broadcom.com>
848 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
849 which wouldn't compile anyway.
850 * sim-main.h (unpredictable_action): New function prototype.
851 (Unpredictable): Define to call igen function unpredictable().
852 (NotWordValue): New macro to call igen function not_word_value().
853 (UndefinedResult): Remove.
854 * interp.c (undefined_result): Remove.
855 (unpredictable_action): New function.
856 * mips.igen (not_word_value, unpredictable): New functions.
857 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
858 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
859 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
860 NotWordValue() to check for unpredictable inputs, then
861 Unpredictable() to handle them.
863 2002-02-24 Chris Demetriou <cgd@broadcom.com>
865 * mips.igen: Fix formatting of calls to Unpredictable().
867 2002-04-20 Andrew Cagney <ac131313@redhat.com>
869 * interp.c (sim_open): Revert previous change.
871 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
873 * interp.c (sim_open): Disable chunk of code that wrote code in
874 vector table entries.
876 2002-03-19 Chris Demetriou <cgd@broadcom.com>
878 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
879 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
882 2002-03-19 Chris Demetriou <cgd@broadcom.com>
884 * cp1.c: Fix many formatting issues.
886 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
888 * cp1.c (fpu_format_name): New function to replace...
889 (DOFMT): This. Delete, and update all callers.
890 (fpu_rounding_mode_name): New function to replace...
891 (RMMODE): This. Delete, and update all callers.
893 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
895 * interp.c: Move FPU support routines from here to...
896 * cp1.c: Here. New file.
897 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
900 2002-03-12 Chris Demetriou <cgd@broadcom.com>
902 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
903 * mips.igen (mips32, mips64): New models, add to all instructions
904 and functions as appropriate.
905 (loadstore_ea, check_u64): New variant for model mips64.
906 (check_fmt_p): New variant for models mipsV and mips64, remove
907 mipsV model marking fro other variant.
910 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
911 for mips32 and mips64.
912 (DCLO, DCLZ): New instructions for mips64.
914 2002-03-07 Chris Demetriou <cgd@broadcom.com>
916 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
917 immediate or code as a hex value with the "%#lx" format.
918 (ANDI): Likewise, and fix printed instruction name.
920 2002-03-05 Chris Demetriou <cgd@broadcom.com>
922 * sim-main.h (UndefinedResult, Unpredictable): New macros
923 which currently do nothing.
925 2002-03-05 Chris Demetriou <cgd@broadcom.com>
927 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
928 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
929 (status_CU3): New definitions.
931 * sim-main.h (ExceptionCause): Add new values for MIPS32
932 and MIPS64: MDMX, MCheck, CacheErr. Update comments
933 for DebugBreakPoint and NMIReset to note their status in
935 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
936 (SignalExceptionCacheErr): New exception macros.
938 2002-03-05 Chris Demetriou <cgd@broadcom.com>
940 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
941 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
943 (SignalExceptionCoProcessorUnusable): Take as argument the
944 unusable coprocessor number.
946 2002-03-05 Chris Demetriou <cgd@broadcom.com>
948 * mips.igen: Fix formatting of all SignalException calls.
950 2002-03-05 Chris Demetriou <cgd@broadcom.com>
952 * sim-main.h (SIGNEXTEND): Remove.
954 2002-03-04 Chris Demetriou <cgd@broadcom.com>
956 * mips.igen: Remove gencode comment from top of file, fix
957 spelling in another comment.
959 2002-03-04 Chris Demetriou <cgd@broadcom.com>
961 * mips.igen (check_fmt, check_fmt_p): New functions to check
962 whether specific floating point formats are usable.
963 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
964 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
965 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
966 Use the new functions.
967 (do_c_cond_fmt): Remove format checks...
968 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
970 2002-03-03 Chris Demetriou <cgd@broadcom.com>
972 * mips.igen: Fix formatting of check_fpu calls.
974 2002-03-03 Chris Demetriou <cgd@broadcom.com>
976 * mips.igen (FLOOR.L.fmt): Store correct destination register.
978 2002-03-03 Chris Demetriou <cgd@broadcom.com>
980 * mips.igen: Remove whitespace at end of lines.
982 2002-03-02 Chris Demetriou <cgd@broadcom.com>
984 * mips.igen (loadstore_ea): New function to do effective
985 address calculations.
986 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
987 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
988 CACHE): Use loadstore_ea to do effective address computations.
990 2002-03-02 Chris Demetriou <cgd@broadcom.com>
992 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
993 * mips.igen (LL, CxC1, MxC1): Likewise.
995 2002-03-02 Chris Demetriou <cgd@broadcom.com>
997 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
998 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
999 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1000 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1001 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1002 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1003 Don't split opcode fields by hand, use the opcode field values
1006 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1008 * mips.igen (do_divu): Fix spacing.
1010 * mips.igen (do_dsllv): Move to be right before DSLLV,
1011 to match the rest of the do_<shift> functions.
1013 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1015 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1016 DSRL32, do_dsrlv): Trace inputs and results.
1018 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1020 * mips.igen (CACHE): Provide instruction-printing string.
1022 * interp.c (signal_exception): Comment tokens after #endif.
1024 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1026 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1027 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1028 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1029 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1030 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1031 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1032 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1033 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1035 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1037 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1038 instruction-printing string.
1039 (LWU): Use '64' as the filter flag.
1041 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1043 * mips.igen (SDXC1): Fix instruction-printing string.
1045 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1047 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1048 filter flags "32,f".
1050 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1052 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1055 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1057 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1058 add a comma) so that it more closely match the MIPS ISA
1059 documentation opcode partitioning.
1060 (PREF): Put useful names on opcode fields, and include
1061 instruction-printing string.
1063 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1065 * mips.igen (check_u64): New function which in the future will
1066 check whether 64-bit instructions are usable and signal an
1067 exception if not. Currently a no-op.
1068 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1069 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1070 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1071 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1073 * mips.igen (check_fpu): New function which in the future will
1074 check whether FPU instructions are usable and signal an exception
1075 if not. Currently a no-op.
1076 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1077 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1078 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1079 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1080 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1081 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1082 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1083 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1085 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1087 * mips.igen (do_load_left, do_load_right): Move to be immediately
1089 (do_store_left, do_store_right): Move to be immediately following
1092 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1094 * mips.igen (mipsV): New model name. Also, add it to
1095 all instructions and functions where it is appropriate.
1097 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1099 * mips.igen: For all functions and instructions, list model
1100 names that support that instruction one per line.
1102 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1104 * mips.igen: Add some additional comments about supported
1105 models, and about which instructions go where.
1106 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1107 order as is used in the rest of the file.
1109 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1111 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1112 indicating that ALU32_END or ALU64_END are there to check
1114 (DADD): Likewise, but also remove previous comment about
1117 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1119 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1120 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1121 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1122 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1123 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1124 fields (i.e., add and move commas) so that they more closely
1125 match the MIPS ISA documentation opcode partitioning.
1127 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1129 * mips.igen (ADDI): Print immediate value.
1130 (BREAK): Print code.
1131 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1132 (SLL): Print "nop" specially, and don't run the code
1133 that does the shift for the "nop" case.
1135 2001-11-17 Fred Fish <fnf@redhat.com>
1137 * sim-main.h (float_operation): Move enum declaration outside
1138 of _sim_cpu struct declaration.
1140 2001-04-12 Jim Blandy <jimb@redhat.com>
1142 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1143 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1145 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1146 PENDING_FILL, and you can get the intended effect gracefully by
1147 calling PENDING_SCHED directly.
1149 2001-02-23 Ben Elliston <bje@redhat.com>
1151 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1152 already defined elsewhere.
1154 2001-02-19 Ben Elliston <bje@redhat.com>
1156 * sim-main.h (sim_monitor): Return an int.
1157 * interp.c (sim_monitor): Add return values.
1158 (signal_exception): Handle error conditions from sim_monitor.
1160 2001-02-08 Ben Elliston <bje@redhat.com>
1162 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1163 (store_memory): Likewise, pass cia to sim_core_write*.
1165 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1167 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1168 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1170 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1172 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1173 * Makefile.in: Don't delete *.igen when cleaning directory.
1175 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1177 * m16.igen (break): Call SignalException not sim_engine_halt.
1179 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1181 From Jason Eckhardt:
1182 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1184 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1186 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1188 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1190 * mips.igen (do_dmultx): Fix typo.
1192 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1194 * configure: Regenerated to track ../common/aclocal.m4 changes.
1196 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1198 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1200 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1202 * sim-main.h (GPR_CLEAR): Define macro.
1204 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1206 * interp.c (decode_coproc): Output long using %lx and not %s.
1208 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1210 * interp.c (sim_open): Sort & extend dummy memory regions for
1211 --board=jmr3904 for eCos.
1213 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1215 * configure: Regenerated.
1217 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1219 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1220 calls, conditional on the simulator being in verbose mode.
1222 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1224 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1225 cache don't get ReservedInstruction traps.
1227 1999-11-29 Mark Salter <msalter@cygnus.com>
1229 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1230 to clear status bits in sdisr register. This is how the hardware works.
1232 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1233 being used by cygmon.
1235 1999-11-11 Andrew Haley <aph@cygnus.com>
1237 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1240 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1242 * mips.igen (MULT): Correct previous mis-applied patch.
1244 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1246 * mips.igen (delayslot32): Handle sequence like
1247 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1248 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1249 (MULT): Actually pass the third register...
1251 1999-09-03 Mark Salter <msalter@cygnus.com>
1253 * interp.c (sim_open): Added more memory aliases for additional
1254 hardware being touched by cygmon on jmr3904 board.
1256 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1258 * configure: Regenerated to track ../common/aclocal.m4 changes.
1260 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1262 * interp.c (sim_store_register): Handle case where client - GDB -
1263 specifies that a 4 byte register is 8 bytes in size.
1264 (sim_fetch_register): Ditto.
1266 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1268 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1269 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1270 (idt_monitor_base): Base address for IDT monitor traps.
1271 (pmon_monitor_base): Ditto for PMON.
1272 (lsipmon_monitor_base): Ditto for LSI PMON.
1273 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1274 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1275 (sim_firmware_command): New function.
1276 (mips_option_handler): Call it for OPTION_FIRMWARE.
1277 (sim_open): Allocate memory for idt_monitor region. If "--board"
1278 option was given, add no monitor by default. Add BREAK hooks only if
1279 monitors are also there.
1281 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1283 * interp.c (sim_monitor): Flush output before reading input.
1285 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1287 * tconfig.in (SIM_HANDLES_LMA): Always define.
1289 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1291 From Mark Salter <msalter@cygnus.com>:
1292 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1293 (sim_open): Add setup for BSP board.
1295 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1297 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1298 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1299 them as unimplemented.
1301 1999-05-08 Felix Lee <flee@cygnus.com>
1303 * configure: Regenerated to track ../common/aclocal.m4 changes.
1305 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1307 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1309 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1311 * configure.in: Any mips64vr5*-*-* target should have
1312 -DTARGET_ENABLE_FR=1.
1313 (default_endian): Any mips64vr*el-*-* target should default to
1315 * configure: Re-generate.
1317 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1319 * mips.igen (ldl): Extend from _16_, not 32.
1321 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1323 * interp.c (sim_store_register): Force registers written to by GDB
1324 into an un-interpreted state.
1326 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1328 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1329 CPU, start periodic background I/O polls.
1330 (tx3904sio_poll): New function: periodic I/O poller.
1332 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1334 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1336 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1338 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1341 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1343 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1344 (load_word): Call SIM_CORE_SIGNAL hook on error.
1345 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1346 starting. For exception dispatching, pass PC instead of NULL_CIA.
1347 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1348 * sim-main.h (COP0_BADVADDR): Define.
1349 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1350 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1351 (_sim_cpu): Add exc_* fields to store register value snapshots.
1352 * mips.igen (*): Replace memory-related SignalException* calls
1353 with references to SIM_CORE_SIGNAL hook.
1355 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1357 * sim-main.c (*): Minor warning cleanups.
1359 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1361 * m16.igen (DADDIU5): Correct type-o.
1363 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1365 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1368 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1370 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1372 (interp.o): Add dependency on itable.h
1373 (oengine.c, gencode): Delete remaining references.
1374 (BUILT_SRC_FROM_GEN): Clean up.
1376 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1379 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1380 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1381 tmp-run-hack) : New.
1382 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1383 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1384 Drop the "64" qualifier to get the HACK generator working.
1385 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1386 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1387 qualifier to get the hack generator working.
1388 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1389 (DSLL): Use do_dsll.
1390 (DSLLV): Use do_dsllv.
1391 (DSRA): Use do_dsra.
1392 (DSRL): Use do_dsrl.
1393 (DSRLV): Use do_dsrlv.
1394 (BC1): Move *vr4100 to get the HACK generator working.
1395 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1396 get the HACK generator working.
1397 (MACC) Rename to get the HACK generator working.
1398 (DMACC,MACCS,DMACCS): Add the 64.
1400 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1402 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1403 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1405 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1407 * mips/interp.c (DEBUG): Cleanups.
1409 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1411 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1412 (tx3904sio_tickle): fflush after a stdout character output.
1414 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1416 * interp.c (sim_close): Uninstall modules.
1418 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1420 * sim-main.h, interp.c (sim_monitor): Change to global
1423 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1425 * configure.in (vr4100): Only include vr4100 instructions in
1427 * configure: Re-generate.
1428 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1430 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1432 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1433 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1436 * configure.in (sim_default_gen, sim_use_gen): Replace with
1438 (--enable-sim-igen): Delete config option. Always using IGEN.
1439 * configure: Re-generate.
1441 * Makefile.in (gencode): Kill, kill, kill.
1444 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1446 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1447 bit mips16 igen simulator.
1448 * configure: Re-generate.
1450 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1451 as part of vr4100 ISA.
1452 * vr.igen: Mark all instructions as 64 bit only.
1454 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1456 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1459 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1461 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1462 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1463 * configure: Re-generate.
1465 * m16.igen (BREAK): Define breakpoint instruction.
1466 (JALX32): Mark instruction as mips16 and not r3900.
1467 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1469 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1471 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1473 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1474 insn as a debug breakpoint.
1476 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1478 (PENDING_SCHED): Clean up trace statement.
1479 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1480 (PENDING_FILL): Delay write by only one cycle.
1481 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1483 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1485 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1487 (pending_tick): Move incrementing of index to FOR statement.
1488 (pending_tick): Only update PENDING_OUT after a write has occured.
1490 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1492 * configure: Re-generate.
1494 * interp.c (sim_engine_run OLD): Delete explicit call to
1495 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1497 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1499 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1500 interrupt level number to match changed SignalExceptionInterrupt
1503 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1505 * interp.c: #include "itable.h" if WITH_IGEN.
1506 (get_insn_name): New function.
1507 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1508 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1510 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1512 * configure: Rebuilt to inhale new common/aclocal.m4.
1514 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1516 * dv-tx3904sio.c: Include sim-assert.h.
1518 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1520 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1521 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1522 Reorganize target-specific sim-hardware checks.
1523 * configure: rebuilt.
1524 * interp.c (sim_open): For tx39 target boards, set
1525 OPERATING_ENVIRONMENT, add tx3904sio devices.
1526 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1527 ROM executables. Install dv-sockser into sim-modules list.
1529 * dv-tx3904irc.c: Compiler warning clean-up.
1530 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1531 frequent hw-trace messages.
1533 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1535 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1537 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1539 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1541 * vr.igen: New file.
1542 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1543 * mips.igen: Define vr4100 model. Include vr.igen.
1544 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1546 * mips.igen (check_mf_hilo): Correct check.
1548 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1550 * sim-main.h (interrupt_event): Add prototype.
1552 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1553 register_ptr, register_value.
1554 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1556 * sim-main.h (tracefh): Make extern.
1558 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1560 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1561 Reduce unnecessarily high timer event frequency.
1562 * dv-tx3904cpu.c: Ditto for interrupt event.
1564 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1566 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1568 (interrupt_event): Made non-static.
1570 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1571 interchange of configuration values for external vs. internal
1574 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1576 * mips.igen (BREAK): Moved code to here for
1577 simulator-reserved break instructions.
1578 * gencode.c (build_instruction): Ditto.
1579 * interp.c (signal_exception): Code moved from here. Non-
1580 reserved instructions now use exception vector, rather
1582 * sim-main.h: Moved magic constants to here.
1584 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1586 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1587 register upon non-zero interrupt event level, clear upon zero
1589 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1590 by passing zero event value.
1591 (*_io_{read,write}_buffer): Endianness fixes.
1592 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1593 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1595 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1596 serial I/O and timer module at base address 0xFFFF0000.
1598 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1600 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1603 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1605 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1607 * configure: Update.
1609 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1611 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1612 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1613 * configure.in: Include tx3904tmr in hw_device list.
1614 * configure: Rebuilt.
1615 * interp.c (sim_open): Instantiate three timer instances.
1616 Fix address typo of tx3904irc instance.
1618 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1620 * interp.c (signal_exception): SystemCall exception now uses
1621 the exception vector.
1623 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1625 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1628 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1630 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1632 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1634 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1636 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1637 sim-main.h. Declare a struct hw_descriptor instead of struct
1638 hw_device_descriptor.
1640 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1642 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1643 right bits and then re-align left hand bytes to correct byte
1644 lanes. Fix incorrect computation in do_store_left when loading
1645 bytes from second word.
1647 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1649 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1650 * interp.c (sim_open): Only create a device tree when HW is
1653 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1654 * interp.c (signal_exception): Ditto.
1656 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1658 * gencode.c: Mark BEGEZALL as LIKELY.
1660 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1662 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1663 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1665 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1667 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1668 modules. Recognize TX39 target with "mips*tx39" pattern.
1669 * configure: Rebuilt.
1670 * sim-main.h (*): Added many macros defining bits in
1671 TX39 control registers.
1672 (SignalInterrupt): Send actual PC instead of NULL.
1673 (SignalNMIReset): New exception type.
1674 * interp.c (board): New variable for future use to identify
1675 a particular board being simulated.
1676 (mips_option_handler,mips_options): Added "--board" option.
1677 (interrupt_event): Send actual PC.
1678 (sim_open): Make memory layout conditional on board setting.
1679 (signal_exception): Initial implementation of hardware interrupt
1680 handling. Accept another break instruction variant for simulator
1682 (decode_coproc): Implement RFE instruction for TX39.
1683 (mips.igen): Decode RFE instruction as such.
1684 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1685 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1686 bbegin to implement memory map.
1687 * dv-tx3904cpu.c: New file.
1688 * dv-tx3904irc.c: New file.
1690 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1692 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1694 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1696 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1697 with calls to check_div_hilo.
1699 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1701 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1702 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1703 Add special r3900 version of do_mult_hilo.
1704 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1705 with calls to check_mult_hilo.
1706 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1707 with calls to check_div_hilo.
1709 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1711 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1712 Document a replacement.
1714 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1716 * interp.c (sim_monitor): Make mon_printf work.
1718 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1720 * sim-main.h (INSN_NAME): New arg `cpu'.
1722 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1724 * configure: Regenerated to track ../common/aclocal.m4 changes.
1726 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1728 * configure: Regenerated to track ../common/aclocal.m4 changes.
1731 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1733 * acconfig.h: New file.
1734 * configure.in: Reverted change of Apr 24; use sinclude again.
1736 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1738 * configure: Regenerated to track ../common/aclocal.m4 changes.
1741 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1743 * configure.in: Don't call sinclude.
1745 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1747 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1749 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1751 * mips.igen (ERET): Implement.
1753 * interp.c (decode_coproc): Return sign-extended EPC.
1755 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1757 * interp.c (signal_exception): Do not ignore Trap.
1758 (signal_exception): On TRAP, restart at exception address.
1759 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1760 (signal_exception): Update.
1761 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1762 so that TRAP instructions are caught.
1764 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1766 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1767 contains HI/LO access history.
1768 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1769 (HIACCESS, LOACCESS): Delete, replace with
1770 (HIHISTORY, LOHISTORY): New macros.
1771 (CHECKHILO): Delete all, moved to mips.igen
1773 * gencode.c (build_instruction): Do not generate checks for
1774 correct HI/LO register usage.
1776 * interp.c (old_engine_run): Delete checks for correct HI/LO
1779 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1780 check_mf_cycles): New functions.
1781 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1782 do_divu, domultx, do_mult, do_multu): Use.
1784 * tx.igen ("madd", "maddu"): Use.
1786 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1788 * mips.igen (DSRAV): Use function do_dsrav.
1789 (SRAV): Use new function do_srav.
1791 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1792 (B): Sign extend 11 bit immediate.
1793 (EXT-B*): Shift 16 bit immediate left by 1.
1794 (ADDIU*): Don't sign extend immediate value.
1796 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1798 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1800 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1803 * mips.igen (delayslot32, nullify_next_insn): New functions.
1804 (m16.igen): Always include.
1805 (do_*): Add more tracing.
1807 * m16.igen (delayslot16): Add NIA argument, could be called by a
1808 32 bit MIPS16 instruction.
1810 * interp.c (ifetch16): Move function from here.
1811 * sim-main.c (ifetch16): To here.
1813 * sim-main.c (ifetch16, ifetch32): Update to match current
1814 implementations of LH, LW.
1815 (signal_exception): Don't print out incorrect hex value of illegal
1818 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1820 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1823 * m16.igen: Implement MIPS16 instructions.
1825 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1826 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1827 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1828 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1829 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1830 bodies of corresponding code from 32 bit insn to these. Also used
1831 by MIPS16 versions of functions.
1833 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1834 (IMEM16): Drop NR argument from macro.
1836 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1838 * Makefile.in (SIM_OBJS): Add sim-main.o.
1840 * sim-main.h (address_translation, load_memory, store_memory,
1841 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1843 (pr_addr, pr_uword64): Declare.
1844 (sim-main.c): Include when H_REVEALS_MODULE_P.
1846 * interp.c (address_translation, load_memory, store_memory,
1847 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1849 * sim-main.c: To here. Fix compilation problems.
1851 * configure.in: Enable inlining.
1852 * configure: Re-config.
1854 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1856 * configure: Regenerated to track ../common/aclocal.m4 changes.
1858 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1860 * mips.igen: Include tx.igen.
1861 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1862 * tx.igen: New file, contains MADD and MADDU.
1864 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1865 the hardwired constant `7'.
1866 (store_memory): Ditto.
1867 (LOADDRMASK): Move definition to sim-main.h.
1869 mips.igen (MTC0): Enable for r3900.
1872 mips.igen (do_load_byte): Delete.
1873 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1874 do_store_right): New functions.
1875 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1877 configure.in: Let the tx39 use igen again.
1880 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1882 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1883 not an address sized quantity. Return zero for cache sizes.
1885 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1887 * mips.igen (r3900): r3900 does not support 64 bit integer
1890 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1892 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1894 * configure : Rebuild.
1896 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1898 * configure: Regenerated to track ../common/aclocal.m4 changes.
1900 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1902 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1904 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1906 * configure: Regenerated to track ../common/aclocal.m4 changes.
1907 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1909 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1911 * configure: Regenerated to track ../common/aclocal.m4 changes.
1913 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1915 * interp.c (Max, Min): Comment out functions. Not yet used.
1917 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1919 * configure: Regenerated to track ../common/aclocal.m4 changes.
1921 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1923 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1924 configurable settings for stand-alone simulator.
1926 * configure.in: Added X11 search, just in case.
1928 * configure: Regenerated.
1930 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1932 * interp.c (sim_write, sim_read, load_memory, store_memory):
1933 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1935 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1937 * sim-main.h (GETFCC): Return an unsigned value.
1939 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1941 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1942 (DADD): Result destination is RD not RT.
1944 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1946 * sim-main.h (HIACCESS, LOACCESS): Always define.
1948 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1950 * interp.c (sim_info): Delete.
1952 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1954 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1955 (mips_option_handler): New argument `cpu'.
1956 (sim_open): Update call to sim_add_option_table.
1958 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1960 * mips.igen (CxC1): Add tracing.
1962 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1964 * sim-main.h (Max, Min): Declare.
1966 * interp.c (Max, Min): New functions.
1968 * mips.igen (BC1): Add tracing.
1970 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1972 * interp.c Added memory map for stack in vr4100
1974 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1976 * interp.c (load_memory): Add missing "break"'s.
1978 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1980 * interp.c (sim_store_register, sim_fetch_register): Pass in
1981 length parameter. Return -1.
1983 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1985 * interp.c: Added hardware init hook, fixed warnings.
1987 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1989 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1991 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1993 * interp.c (ifetch16): New function.
1995 * sim-main.h (IMEM32): Rename IMEM.
1996 (IMEM16_IMMED): Define.
1998 (DELAY_SLOT): Update.
2000 * m16run.c (sim_engine_run): New file.
2002 * m16.igen: All instructions except LB.
2003 (LB): Call do_load_byte.
2004 * mips.igen (do_load_byte): New function.
2005 (LB): Call do_load_byte.
2007 * mips.igen: Move spec for insn bit size and high bit from here.
2008 * Makefile.in (tmp-igen, tmp-m16): To here.
2010 * m16.dc: New file, decode mips16 instructions.
2012 * Makefile.in (SIM_NO_ALL): Define.
2013 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2015 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2017 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2018 point unit to 32 bit registers.
2019 * configure: Re-generate.
2021 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2023 * configure.in (sim_use_gen): Make IGEN the default simulator
2024 generator for generic 32 and 64 bit mips targets.
2025 * configure: Re-generate.
2027 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2029 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2032 * interp.c (sim_fetch_register, sim_store_register): Read/write
2033 FGR from correct location.
2034 (sim_open): Set size of FGR's according to
2035 WITH_TARGET_FLOATING_POINT_BITSIZE.
2037 * sim-main.h (FGR): Store floating point registers in a separate
2040 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2042 * configure: Regenerated to track ../common/aclocal.m4 changes.
2044 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2046 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2048 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2050 * interp.c (pending_tick): New function. Deliver pending writes.
2052 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2053 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2054 it can handle mixed sized quantites and single bits.
2056 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2058 * interp.c (oengine.h): Do not include when building with IGEN.
2059 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2060 (sim_info): Ditto for PROCESSOR_64BIT.
2061 (sim_monitor): Replace ut_reg with unsigned_word.
2062 (*): Ditto for t_reg.
2063 (LOADDRMASK): Define.
2064 (sim_open): Remove defunct check that host FP is IEEE compliant,
2065 using software to emulate floating point.
2066 (value_fpr, ...): Always compile, was conditional on HASFPU.
2068 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2070 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2073 * interp.c (SD, CPU): Define.
2074 (mips_option_handler): Set flags in each CPU.
2075 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2076 (sim_close): Do not clear STATE, deleted anyway.
2077 (sim_write, sim_read): Assume CPU zero's vm should be used for
2079 (sim_create_inferior): Set the PC for all processors.
2080 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2082 (mips16_entry): Pass correct nr of args to store_word, load_word.
2083 (ColdReset): Cold reset all cpu's.
2084 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2085 (sim_monitor, load_memory, store_memory, signal_exception): Use
2086 `CPU' instead of STATE_CPU.
2089 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2092 * sim-main.h (signal_exception): Add sim_cpu arg.
2093 (SignalException*): Pass both SD and CPU to signal_exception.
2094 * interp.c (signal_exception): Update.
2096 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2098 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2099 address_translation): Ditto
2100 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2102 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2104 * configure: Regenerated to track ../common/aclocal.m4 changes.
2106 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2108 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2110 * mips.igen (model): Map processor names onto BFD name.
2112 * sim-main.h (CPU_CIA): Delete.
2113 (SET_CIA, GET_CIA): Define
2115 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2117 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2120 * configure.in (default_endian): Configure a big-endian simulator
2122 * configure: Re-generate.
2124 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2126 * configure: Regenerated to track ../common/aclocal.m4 changes.
2128 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2130 * interp.c (sim_monitor): Handle Densan monitor outbyte
2131 and inbyte functions.
2133 1997-12-29 Felix Lee <flee@cygnus.com>
2135 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2137 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2139 * Makefile.in (tmp-igen): Arrange for $zero to always be
2140 reset to zero after every instruction.
2142 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2144 * configure: Regenerated to track ../common/aclocal.m4 changes.
2147 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2149 * mips.igen (MSUB): Fix to work like MADD.
2150 * gencode.c (MSUB): Similarly.
2152 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2154 * configure: Regenerated to track ../common/aclocal.m4 changes.
2156 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2158 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2160 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2162 * sim-main.h (sim-fpu.h): Include.
2164 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2165 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2166 using host independant sim_fpu module.
2168 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2170 * interp.c (signal_exception): Report internal errors with SIGABRT
2173 * sim-main.h (C0_CONFIG): New register.
2174 (signal.h): No longer include.
2176 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2178 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2180 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2182 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184 * mips.igen: Tag vr5000 instructions.
2185 (ANDI): Was missing mipsIV model, fix assembler syntax.
2186 (do_c_cond_fmt): New function.
2187 (C.cond.fmt): Handle mips I-III which do not support CC field
2189 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2190 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2192 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2193 vr5000 which saves LO in a GPR separatly.
2195 * configure.in (enable-sim-igen): For vr5000, select vr5000
2196 specific instructions.
2197 * configure: Re-generate.
2199 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2201 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2203 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2204 fmt_uninterpreted_64 bit cases to switch. Convert to
2207 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2209 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2210 as specified in IV3.2 spec.
2211 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2213 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2215 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2216 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2217 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2218 PENDING_FILL versions of instructions. Simplify.
2220 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2222 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2224 (MTHI, MFHI): Disable code checking HI-LO.
2226 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2228 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2230 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2232 * gencode.c (build_mips16_operands): Replace IPC with cia.
2234 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2235 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2237 (UndefinedResult): Replace function with macro/function
2239 (sim_engine_run): Don't save PC in IPC.
2241 * sim-main.h (IPC): Delete.
2244 * interp.c (signal_exception, store_word, load_word,
2245 address_translation, load_memory, store_memory, cache_op,
2246 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2247 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2248 current instruction address - cia - argument.
2249 (sim_read, sim_write): Call address_translation directly.
2250 (sim_engine_run): Rename variable vaddr to cia.
2251 (signal_exception): Pass cia to sim_monitor
2253 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2254 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2255 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2257 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2258 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2261 * interp.c (signal_exception): Pass restart address to
2264 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2265 idecode.o): Add dependency.
2267 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2269 (DELAY_SLOT): Update NIA not PC with branch address.
2270 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2272 * mips.igen: Use CIA not PC in branch calculations.
2273 (illegal): Call SignalException.
2274 (BEQ, ADDIU): Fix assembler.
2276 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2278 * m16.igen (JALX): Was missing.
2280 * configure.in (enable-sim-igen): New configuration option.
2281 * configure: Re-generate.
2283 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2285 * interp.c (load_memory, store_memory): Delete parameter RAW.
2286 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2287 bypassing {load,store}_memory.
2289 * sim-main.h (ByteSwapMem): Delete definition.
2291 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2293 * interp.c (sim_do_command, sim_commands): Delete mips specific
2294 commands. Handled by module sim-options.
2296 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2297 (WITH_MODULO_MEMORY): Define.
2299 * interp.c (sim_info): Delete code printing memory size.
2301 * interp.c (mips_size): Nee sim_size, delete function.
2303 (monitor, monitor_base, monitor_size): Delete global variables.
2304 (sim_open, sim_close): Delete code creating monitor and other
2305 memory regions. Use sim-memopts module, via sim_do_commandf, to
2306 manage memory regions.
2307 (load_memory, store_memory): Use sim-core for memory model.
2309 * interp.c (address_translation): Delete all memory map code
2310 except line forcing 32 bit addresses.
2312 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2314 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2317 * interp.c (logfh, logfile): Delete globals.
2318 (sim_open, sim_close): Delete code opening & closing log file.
2319 (mips_option_handler): Delete -l and -n options.
2320 (OPTION mips_options): Ditto.
2322 * interp.c (OPTION mips_options): Rename option trace to dinero.
2323 (mips_option_handler): Update.
2325 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2327 * interp.c (fetch_str): New function.
2328 (sim_monitor): Rewrite using sim_read & sim_write.
2329 (sim_open): Check magic number.
2330 (sim_open): Write monitor vectors into memory using sim_write.
2331 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2332 (sim_read, sim_write): Simplify - transfer data one byte at a
2334 (load_memory, store_memory): Clarify meaning of parameter RAW.
2336 * sim-main.h (isHOST): Defete definition.
2337 (isTARGET): Mark as depreciated.
2338 (address_translation): Delete parameter HOST.
2340 * interp.c (address_translation): Delete parameter HOST.
2342 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2346 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2347 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2349 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2351 * mips.igen: Add model filter field to records.
2353 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2355 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2357 interp.c (sim_engine_run): Do not compile function sim_engine_run
2358 when WITH_IGEN == 1.
2360 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2361 target architecture.
2363 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2364 igen. Replace with configuration variables sim_igen_flags /
2367 * m16.igen: New file. Copy mips16 insns here.
2368 * mips.igen: From here.
2370 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2372 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2374 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2376 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2378 * gencode.c (build_instruction): Follow sim_write's lead in using
2379 BigEndianMem instead of !ByteSwapMem.
2381 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2383 * configure.in (sim_gen): Dependent on target, select type of
2384 generator. Always select old style generator.
2386 configure: Re-generate.
2388 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2390 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2391 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2392 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2393 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2394 SIM_@sim_gen@_*, set by autoconf.
2396 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2398 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2400 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2401 CURRENT_FLOATING_POINT instead.
2403 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2404 (address_translation): Raise exception InstructionFetch when
2405 translation fails and isINSTRUCTION.
2407 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2408 sim_engine_run): Change type of of vaddr and paddr to
2410 (address_translation, prefetch, load_memory, store_memory,
2411 cache_op): Change type of vAddr and pAddr to address_word.
2413 * gencode.c (build_instruction): Change type of vaddr and paddr to
2416 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2418 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2419 macro to obtain result of ALU op.
2421 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2423 * interp.c (sim_info): Call profile_print.
2425 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2427 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2429 * sim-main.h (WITH_PROFILE): Do not define, defined in
2430 common/sim-config.h. Use sim-profile module.
2431 (simPROFILE): Delete defintion.
2433 * interp.c (PROFILE): Delete definition.
2434 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2435 (sim_close): Delete code writing profile histogram.
2436 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2438 (sim_engine_run): Delete code profiling the PC.
2440 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2442 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2444 * interp.c (sim_monitor): Make register pointers of type
2447 * sim-main.h: Make registers of type unsigned_word not
2450 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2452 * interp.c (sync_operation): Rename from SyncOperation, make
2453 global, add SD argument.
2454 (prefetch): Rename from Prefetch, make global, add SD argument.
2455 (decode_coproc): Make global.
2457 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2459 * gencode.c (build_instruction): Generate DecodeCoproc not
2460 decode_coproc calls.
2462 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2463 (SizeFGR): Move to sim-main.h
2464 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2465 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2466 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2468 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2469 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2470 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2471 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2472 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2473 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2475 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2477 (sim-alu.h): Include.
2478 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2479 (sim_cia): Typedef to instruction_address.
2481 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2483 * Makefile.in (interp.o): Rename generated file engine.c to
2488 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2490 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2492 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2494 * gencode.c (build_instruction): For "FPSQRT", output correct
2495 number of arguments to Recip.
2497 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2499 * Makefile.in (interp.o): Depends on sim-main.h
2501 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2503 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2504 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2505 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2506 STATE, DSSTATE): Define
2507 (GPR, FGRIDX, ..): Define.
2509 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2510 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2511 (GPR, FGRIDX, ...): Delete macros.
2513 * interp.c: Update names to match defines from sim-main.h
2515 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2517 * interp.c (sim_monitor): Add SD argument.
2518 (sim_warning): Delete. Replace calls with calls to
2520 (sim_error): Delete. Replace calls with sim_io_error.
2521 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2522 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2523 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2525 (mips_size): Rename from sim_size. Add SD argument.
2527 * interp.c (simulator): Delete global variable.
2528 (callback): Delete global variable.
2529 (mips_option_handler, sim_open, sim_write, sim_read,
2530 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2531 sim_size,sim_monitor): Use sim_io_* not callback->*.
2532 (sim_open): ZALLOC simulator struct.
2533 (PROFILE): Do not define.
2535 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2537 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2538 support.h with corresponding code.
2540 * sim-main.h (word64, uword64), support.h: Move definition to
2542 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2545 * Makefile.in: Update dependencies
2546 * interp.c: Do not include.
2548 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2550 * interp.c (address_translation, load_memory, store_memory,
2551 cache_op): Rename to from AddressTranslation et.al., make global,
2554 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2557 * interp.c (SignalException): Rename to signal_exception, make
2560 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2562 * sim-main.h (SignalException, SignalExceptionInterrupt,
2563 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2564 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2565 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2568 * interp.c, support.h: Use.
2570 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2572 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2573 to value_fpr / store_fpr. Add SD argument.
2574 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2575 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2577 * sim-main.h (ValueFPR, StoreFPR): Define.
2579 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2581 * interp.c (sim_engine_run): Check consistency between configure
2582 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2585 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2586 (mips_fpu): Configure WITH_FLOATING_POINT.
2587 (mips_endian): Configure WITH_TARGET_ENDIAN.
2588 * configure: Update.
2590 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2592 * configure: Regenerated to track ../common/aclocal.m4 changes.
2594 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2596 * configure: Regenerated.
2598 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2600 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2602 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2604 * gencode.c (print_igen_insn_models): Assume certain architectures
2605 include all mips* instructions.
2606 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2609 * Makefile.in (tmp.igen): Add target. Generate igen input from
2612 * gencode.c (FEATURE_IGEN): Define.
2613 (main): Add --igen option. Generate output in igen format.
2614 (process_instructions): Format output according to igen option.
2615 (print_igen_insn_format): New function.
2616 (print_igen_insn_models): New function.
2617 (process_instructions): Only issue warnings and ignore
2618 instructions when no FEATURE_IGEN.
2620 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2622 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2625 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2627 * configure: Regenerated to track ../common/aclocal.m4 changes.
2629 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2631 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2632 SIM_RESERVED_BITS): Delete, moved to common.
2633 (SIM_EXTRA_CFLAGS): Update.
2635 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2637 * configure.in: Configure non-strict memory alignment.
2638 * configure: Regenerated to track ../common/aclocal.m4 changes.
2640 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2642 * configure: Regenerated to track ../common/aclocal.m4 changes.
2644 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2646 * gencode.c (SDBBP,DERET): Added (3900) insns.
2647 (RFE): Turn on for 3900.
2648 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2649 (dsstate): Made global.
2650 (SUBTARGET_R3900): Added.
2651 (CANCELDELAYSLOT): New.
2652 (SignalException): Ignore SystemCall rather than ignore and
2653 terminate. Add DebugBreakPoint handling.
2654 (decode_coproc): New insns RFE, DERET; and new registers Debug
2655 and DEPC protected by SUBTARGET_R3900.
2656 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2658 * Makefile.in,configure.in: Add mips subtarget option.
2659 * configure: Update.
2661 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2663 * gencode.c: Add r3900 (tx39).
2666 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2668 * gencode.c (build_instruction): Don't need to subtract 4 for
2671 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2673 * interp.c: Correct some HASFPU problems.
2675 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2677 * configure: Regenerated to track ../common/aclocal.m4 changes.
2679 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2681 * interp.c (mips_options): Fix samples option short form, should
2684 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2686 * interp.c (sim_info): Enable info code. Was just returning.
2688 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2690 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2693 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2695 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2697 (build_instruction): Ditto for LL.
2699 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2701 * configure: Regenerated to track ../common/aclocal.m4 changes.
2703 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2705 * configure: Regenerated to track ../common/aclocal.m4 changes.
2708 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2710 * interp.c (sim_open): Add call to sim_analyze_program, update
2713 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2715 * interp.c (sim_kill): Delete.
2716 (sim_create_inferior): Add ABFD argument. Set PC from same.
2717 (sim_load): Move code initializing trap handlers from here.
2718 (sim_open): To here.
2719 (sim_load): Delete, use sim-hload.c.
2721 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2723 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725 * configure: Regenerated to track ../common/aclocal.m4 changes.
2728 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2730 * interp.c (sim_open): Add ABFD argument.
2731 (sim_load): Move call to sim_config from here.
2732 (sim_open): To here. Check return status.
2734 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2736 * gencode.c (build_instruction): Two arg MADD should
2737 not assign result to $0.
2739 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2741 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2742 * sim/mips/configure.in: Regenerate.
2744 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2746 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2747 signed8, unsigned8 et.al. types.
2749 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2750 hosts when selecting subreg.
2752 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2754 * interp.c (sim_engine_run): Reset the ZERO register to zero
2755 regardless of FEATURE_WARN_ZERO.
2756 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2758 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2760 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2761 (SignalException): For BreakPoints ignore any mode bits and just
2763 (SignalException): Always set the CAUSE register.
2765 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2767 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2768 exception has been taken.
2770 * interp.c: Implement the ERET and mt/f sr instructions.
2772 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2774 * interp.c (SignalException): Don't bother restarting an
2777 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2779 * interp.c (SignalException): Really take an interrupt.
2780 (interrupt_event): Only deliver interrupts when enabled.
2782 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2784 * interp.c (sim_info): Only print info when verbose.
2785 (sim_info) Use sim_io_printf for output.
2787 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2789 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2792 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2794 * interp.c (sim_do_command): Check for common commands if a
2795 simulator specific command fails.
2797 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2799 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2800 and simBE when DEBUG is defined.
2802 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2804 * interp.c (interrupt_event): New function. Pass exception event
2805 onto exception handler.
2807 * configure.in: Check for stdlib.h.
2808 * configure: Regenerate.
2810 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2811 variable declaration.
2812 (build_instruction): Initialize memval1.
2813 (build_instruction): Add UNUSED attribute to byte, bigend,
2815 (build_operands): Ditto.
2817 * interp.c: Fix GCC warnings.
2818 (sim_get_quit_code): Delete.
2820 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2821 * Makefile.in: Ditto.
2822 * configure: Re-generate.
2824 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2826 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2828 * interp.c (mips_option_handler): New function parse argumes using
2830 (myname): Replace with STATE_MY_NAME.
2831 (sim_open): Delete check for host endianness - performed by
2833 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2834 (sim_open): Move much of the initialization from here.
2835 (sim_load): To here. After the image has been loaded and
2837 (sim_open): Move ColdReset from here.
2838 (sim_create_inferior): To here.
2839 (sim_open): Make FP check less dependant on host endianness.
2841 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2843 * interp.c (sim_set_callbacks): Delete.
2845 * interp.c (membank, membank_base, membank_size): Replace with
2846 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2847 (sim_open): Remove call to callback->init. gdb/run do this.
2851 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2853 * interp.c (big_endian_p): Delete, replaced by
2854 current_target_byte_order.
2856 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2858 * interp.c (host_read_long, host_read_word, host_swap_word,
2859 host_swap_long): Delete. Using common sim-endian.
2860 (sim_fetch_register, sim_store_register): Use H2T.
2861 (pipeline_ticks): Delete. Handled by sim-events.
2863 (sim_engine_run): Update.
2865 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2867 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2869 (SignalException): To here. Signal using sim_engine_halt.
2870 (sim_stop_reason): Delete, moved to common.
2872 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2874 * interp.c (sim_open): Add callback argument.
2875 (sim_set_callbacks): Delete SIM_DESC argument.
2878 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2880 * Makefile.in (SIM_OBJS): Add common modules.
2882 * interp.c (sim_set_callbacks): Also set SD callback.
2883 (set_endianness, xfer_*, swap_*): Delete.
2884 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2885 Change to functions using sim-endian macros.
2886 (control_c, sim_stop): Delete, use common version.
2887 (simulate): Convert into.
2888 (sim_engine_run): This function.
2889 (sim_resume): Delete.
2891 * interp.c (simulation): New variable - the simulator object.
2892 (sim_kind): Delete global - merged into simulation.
2893 (sim_load): Cleanup. Move PC assignment from here.
2894 (sim_create_inferior): To here.
2896 * sim-main.h: New file.
2897 * interp.c (sim-main.h): Include.
2899 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2901 * configure: Regenerated to track ../common/aclocal.m4 changes.
2903 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2905 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2907 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2909 * gencode.c (build_instruction): DIV instructions: check
2910 for division by zero and integer overflow before using
2911 host's division operation.
2913 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2915 * Makefile.in (SIM_OBJS): Add sim-load.o.
2916 * interp.c: #include bfd.h.
2917 (target_byte_order): Delete.
2918 (sim_kind, myname, big_endian_p): New static locals.
2919 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2920 after argument parsing. Recognize -E arg, set endianness accordingly.
2921 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2922 load file into simulator. Set PC from bfd.
2923 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2924 (set_endianness): Use big_endian_p instead of target_byte_order.
2926 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2928 * interp.c (sim_size): Delete prototype - conflicts with
2929 definition in remote-sim.h. Correct definition.
2931 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2933 * configure: Regenerated to track ../common/aclocal.m4 changes.
2936 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2938 * interp.c (sim_open): New arg `kind'.
2940 * configure: Regenerated to track ../common/aclocal.m4 changes.
2942 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2944 * configure: Regenerated to track ../common/aclocal.m4 changes.
2946 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2948 * interp.c (sim_open): Set optind to 0 before calling getopt.
2950 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2952 * configure: Regenerated to track ../common/aclocal.m4 changes.
2954 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2956 * interp.c : Replace uses of pr_addr with pr_uword64
2957 where the bit length is always 64 independent of SIM_ADDR.
2958 (pr_uword64) : added.
2960 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2962 * configure: Re-generate.
2964 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2966 * configure: Regenerate to track ../common/aclocal.m4 changes.
2968 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2970 * interp.c (sim_open): New SIM_DESC result. Argument is now
2972 (other sim_*): New SIM_DESC argument.
2974 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2976 * interp.c: Fix printing of addresses for non-64-bit targets.
2977 (pr_addr): Add function to print address based on size.
2979 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2981 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2983 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2985 * gencode.c (build_mips16_operands): Correct computation of base
2986 address for extended PC relative instruction.
2988 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2990 * interp.c (mips16_entry): Add support for floating point cases.
2991 (SignalException): Pass floating point cases to mips16_entry.
2992 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2994 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2996 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2997 and then set the state to fmt_uninterpreted.
2998 (COP_SW): Temporarily set the state to fmt_word while calling
3001 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3003 * gencode.c (build_instruction): The high order may be set in the
3004 comparison flags at any ISA level, not just ISA 4.
3006 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3008 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3009 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3010 * configure.in: sinclude ../common/aclocal.m4.
3011 * configure: Regenerated.
3013 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3015 * configure: Rebuild after change to aclocal.m4.
3017 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3019 * configure configure.in Makefile.in: Update to new configure
3020 scheme which is more compatible with WinGDB builds.
3021 * configure.in: Improve comment on how to run autoconf.
3022 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3023 * Makefile.in: Use autoconf substitution to install common
3026 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3028 * gencode.c (build_instruction): Use BigEndianCPU instead of
3031 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3033 * interp.c (sim_monitor): Make output to stdout visible in
3034 wingdb's I/O log window.
3036 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3038 * support.h: Undo previous change to SIGTRAP
3041 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3043 * interp.c (store_word, load_word): New static functions.
3044 (mips16_entry): New static function.
3045 (SignalException): Look for mips16 entry and exit instructions.
3046 (simulate): Use the correct index when setting fpr_state after
3047 doing a pending move.
3049 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3051 * interp.c: Fix byte-swapping code throughout to work on
3052 both little- and big-endian hosts.
3054 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3056 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3057 with gdb/config/i386/xm-windows.h.
3059 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3061 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3062 that messes up arithmetic shifts.
3064 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3066 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3067 SIGTRAP and SIGQUIT for _WIN32.
3069 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3071 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3072 force a 64 bit multiplication.
3073 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3074 destination register is 0, since that is the default mips16 nop
3077 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3079 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3080 (build_endian_shift): Don't check proc64.
3081 (build_instruction): Always set memval to uword64. Cast op2 to
3082 uword64 when shifting it left in memory instructions. Always use
3083 the same code for stores--don't special case proc64.
3085 * gencode.c (build_mips16_operands): Fix base PC value for PC
3087 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3089 * interp.c (simJALDELAYSLOT): Define.
3090 (JALDELAYSLOT): Define.
3091 (INDELAYSLOT, INJALDELAYSLOT): Define.
3092 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3094 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3096 * interp.c (sim_open): add flush_cache as a PMON routine
3097 (sim_monitor): handle flush_cache by ignoring it
3099 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3101 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3103 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3104 (BigEndianMem): Rename to ByteSwapMem and change sense.
3105 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3106 BigEndianMem references to !ByteSwapMem.
3107 (set_endianness): New function, with prototype.
3108 (sim_open): Call set_endianness.
3109 (sim_info): Use simBE instead of BigEndianMem.
3110 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3111 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3112 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3113 ifdefs, keeping the prototype declaration.
3114 (swap_word): Rewrite correctly.
3115 (ColdReset): Delete references to CONFIG. Delete endianness related
3116 code; moved to set_endianness.
3118 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3120 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3121 * interp.c (CHECKHILO): Define away.
3122 (simSIGINT): New macro.
3123 (membank_size): Increase from 1MB to 2MB.
3124 (control_c): New function.
3125 (sim_resume): Rename parameter signal to signal_number. Add local
3126 variable prev. Call signal before and after simulate.
3127 (sim_stop_reason): Add simSIGINT support.
3128 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3130 (sim_warning): Delete call to SignalException. Do call printf_filtered
3132 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3133 a call to sim_warning.
3135 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3137 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3138 16 bit instructions.
3140 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3142 Add support for mips16 (16 bit MIPS implementation):
3143 * gencode.c (inst_type): Add mips16 instruction encoding types.
3144 (GETDATASIZEINSN): Define.
3145 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3146 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3148 (MIPS16_DECODE): New table, for mips16 instructions.
3149 (bitmap_val): New static function.
3150 (struct mips16_op): Define.
3151 (mips16_op_table): New table, for mips16 operands.
3152 (build_mips16_operands): New static function.
3153 (process_instructions): If PC is odd, decode a mips16
3154 instruction. Break out instruction handling into new
3155 build_instruction function.
3156 (build_instruction): New static function, broken out of
3157 process_instructions. Check modifiers rather than flags for SHIFT
3158 bit count and m[ft]{hi,lo} direction.
3159 (usage): Pass program name to fprintf.
3160 (main): Remove unused variable this_option_optind. Change
3161 ``*loptarg++'' to ``loptarg++''.
3162 (my_strtoul): Parenthesize && within ||.
3163 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3164 (simulate): If PC is odd, fetch a 16 bit instruction, and
3165 increment PC by 2 rather than 4.
3166 * configure.in: Add case for mips16*-*-*.
3167 * configure: Rebuild.
3169 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3171 * interp.c: Allow -t to enable tracing in standalone simulator.
3172 Fix garbage output in trace file and error messages.
3174 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3176 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3177 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3178 * configure.in: Simplify using macros in ../common/aclocal.m4.
3179 * configure: Regenerated.
3180 * tconfig.in: New file.
3182 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3184 * interp.c: Fix bugs in 64-bit port.
3185 Use ansi function declarations for msvc compiler.
3186 Initialize and test file pointer in trace code.
3187 Prevent duplicate definition of LAST_EMED_REGNUM.
3189 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3191 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3193 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3195 * interp.c (SignalException): Check for explicit terminating
3197 * gencode.c: Pass instruction value through SignalException()
3198 calls for Trap, Breakpoint and Syscall.
3200 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3202 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3203 only used on those hosts that provide it.
3204 * configure.in: Add sqrt() to list of functions to be checked for.
3205 * config.in: Re-generated.
3206 * configure: Re-generated.
3208 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3210 * gencode.c (process_instructions): Call build_endian_shift when
3211 expanding STORE RIGHT, to fix swr.
3212 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3213 clear the high bits.
3214 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3215 Fix float to int conversions to produce signed values.
3217 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3219 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3220 (process_instructions): Correct handling of nor instruction.
3221 Correct shift count for 32 bit shift instructions. Correct sign
3222 extension for arithmetic shifts to not shift the number of bits in
3223 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3224 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3226 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3227 It's OK to have a mult follow a mult. What's not OK is to have a
3228 mult follow an mfhi.
3229 (Convert): Comment out incorrect rounding code.
3231 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3233 * interp.c (sim_monitor): Improved monitor printf
3234 simulation. Tidied up simulator warnings, and added "--log" option
3235 for directing warning message output.
3236 * gencode.c: Use sim_warning() rather than WARNING macro.
3238 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3240 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3241 getopt1.o, rather than on gencode.c. Link objects together.
3242 Don't link against -liberty.
3243 (gencode.o, getopt.o, getopt1.o): New targets.
3244 * gencode.c: Include <ctype.h> and "ansidecl.h".
3245 (AND): Undefine after including "ansidecl.h".
3246 (ULONG_MAX): Define if not defined.
3247 (OP_*): Don't define macros; now defined in opcode/mips.h.
3248 (main): Call my_strtoul rather than strtoul.
3249 (my_strtoul): New static function.
3251 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3253 * gencode.c (process_instructions): Generate word64 and uword64
3254 instead of `long long' and `unsigned long long' data types.
3255 * interp.c: #include sysdep.h to get signals, and define default
3257 * (Convert): Work around for Visual-C++ compiler bug with type
3259 * support.h: Make things compile under Visual-C++ by using
3260 __int64 instead of `long long'. Change many refs to long long
3261 into word64/uword64 typedefs.
3263 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3265 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3266 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3268 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3269 (AC_PROG_INSTALL): Added.
3270 (AC_PROG_CC): Moved to before configure.host call.
3271 * configure: Rebuilt.
3273 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3275 * configure.in: Define @SIMCONF@ depending on mips target.
3276 * configure: Rebuild.
3277 * Makefile.in (run): Add @SIMCONF@ to control simulator
3279 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3280 * interp.c: Remove some debugging, provide more detailed error
3281 messages, update memory accesses to use LOADDRMASK.
3283 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3285 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3286 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3288 * configure: Rebuild.
3289 * config.in: New file, generated by autoheader.
3290 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3291 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3292 HAVE_ANINT and HAVE_AINT, as appropriate.
3293 * Makefile.in (run): Use @LIBS@ rather than -lm.
3294 (interp.o): Depend upon config.h.
3295 (Makefile): Just rebuild Makefile.
3296 (clean): Remove stamp-h.
3297 (mostlyclean): Make the same as clean, not as distclean.
3298 (config.h, stamp-h): New targets.
3300 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3302 * interp.c (ColdReset): Fix boolean test. Make all simulator
3305 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3307 * interp.c (xfer_direct_word, xfer_direct_long,
3308 swap_direct_word, swap_direct_long, xfer_big_word,
3309 xfer_big_long, xfer_little_word, xfer_little_long,
3310 swap_word,swap_long): Added.
3311 * interp.c (ColdReset): Provide function indirection to
3312 host<->simulated_target transfer routines.
3313 * interp.c (sim_store_register, sim_fetch_register): Updated to
3314 make use of indirected transfer routines.
3316 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3318 * gencode.c (process_instructions): Ensure FP ABS instruction
3320 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3321 system call support.
3323 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3325 * interp.c (sim_do_command): Complain if callback structure not
3328 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3330 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3331 support for Sun hosts.
3332 * Makefile.in (gencode): Ensure the host compiler and libraries
3333 used for cross-hosted build.
3335 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3337 * interp.c, gencode.c: Some more (TODO) tidying.
3339 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3341 * gencode.c, interp.c: Replaced explicit long long references with
3342 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3343 * support.h (SET64LO, SET64HI): Macros added.
3345 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3347 * configure: Regenerate with autoconf 2.7.
3349 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3351 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3352 * support.h: Remove superfluous "1" from #if.
3353 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3355 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3357 * interp.c (StoreFPR): Control UndefinedResult() call on
3358 WARN_RESULT manifest.
3360 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3362 * gencode.c: Tidied instruction decoding, and added FP instruction
3365 * interp.c: Added dineroIII, and BSD profiling support. Also
3366 run-time FP handling.
3368 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3370 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3371 gencode.c, interp.c, support.h: created.