1 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
3 * interp.c (sim_close): Uninstall modules.
6 Tue Dec 1 18:40:30 1998 Andrew Cagney <cagney@b1.cygnus.com>
8 * sky-libvpe.c (FCmp): Abort when no result.
11 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
13 * sim-main.h, interp.c (sim_monitor): Change to global
16 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
18 * configure.in (vr4100): Only include vr4100 instructions in
20 * configure: Re-generate.
21 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
23 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
25 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
26 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
29 * configure.in (sim_default_gen, sim_use_gen): Replace with
31 (--enable-sim-igen): Delete config option. Always using IGEN.
32 * configure: Re-generate.
34 * Makefile.in (gencode): Kill, kill, kill.
37 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
39 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
40 bit mips16 igen simulator.
41 * configure: Re-generate.
43 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
44 as part of vr4100 ISA.
45 * vr.igen: Mark all instructions as 64 bit only.
47 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
49 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
53 Mon Nov 23 16:51:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
55 * configure.in (tx19): Reconize target mips-tx19-elf.
56 * configure: Re-generate.
59 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
61 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
62 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
63 * configure: Re-generate.
65 * m16.igen (BREAK): Define breakpoint instruction.
66 (JALX32): Mark instruction as mips16 and not r3900.
67 * mips.igen (C.cond.fmt): Fix typo in instruction format.
69 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
72 Mon Nov 16 11:44:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
74 * r5900.igen (CVT.W.S): Always round towards zero.
77 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
79 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
80 insn as a debug breakpoint.
82 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
84 (PENDING_SCHED): Clean up trace statement.
85 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
86 (PENDING_FILL): Delay write by only one cycle.
87 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
89 * sim-main.c (pending_tick): Clean up trace statements. Add trace
91 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
93 (pending_tick): Move incrementing of index to FOR statement.
94 (pending_tick): Only update PENDING_OUT after a write has occured.
96 * configure.in: Add explicit mips-lsi-* target. Use gencode to
98 * configure: Re-generate.
100 * interp.c (sim_engine_run OLD): Delete explicit call to
101 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
104 Wed Nov 11 16:53:57 1998 Andrew Cagney <cagney@b1.cygnus.com>
106 * r5900.igen (RSQRT): Set both I/SI and D/SD when div-0.
108 Thu Nov 5 10:29:42 EST 1998 Frank Ch. Eigler <fche@cygnus.com>
110 * r5900.igen (r59fp_opdiv): Correct erroneous FGR[FD] reference.
112 Thu Nov 5 19:40:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
114 * r5900.igen (DIV): Do not clear clear SO/SU when already set.
116 * r5900.igen (RSQRT.S): Do not compute 1/srqt(abs(T)) when T
117 negative, compute S/sqrt(abs(T)) instead. Correctly set FCSR
120 * r5900.igen (RSQRT.S): Handle overflow/underflow better. Check
122 (r59fp_store): Clarify "bad value" abort messages.
125 start-sanitize-tx3904
126 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
128 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
129 interrupt level number to match changed SignalExceptionInterrupt
134 Thu Oct 29 12:47:46 1998 Frank Ch. Eigler <fche@cygnus.com>
136 * sim-main.c (tlb_try_match): Include physical address in
137 scratchpad non-mapping warning.
141 Thu Oct 29 11:06:30 EST 1998 Frank Ch. Eigler <fche@cygnus.com>
143 * r5900.igen: Fix PSRLVW, MULTU1, PADSBH instructions,
144 as per customer patch.
147 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
149 * interp.c: #include "itable.h" if WITH_IGEN.
150 (get_insn_name): New function.
151 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
152 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
155 Tue Sep 22 10:35:37 1998 Frank Ch. Eigler <fche@cygnus.com>
157 * sim-main.c (tlb_try_match): Specially match virtual
158 pages mapped to scratchpad RAM, an unimplemented feature.
162 Fri Sep 18 11:31:16 1998 Frank Ch. Eigler <fche@cygnus.com>
164 * r5900.igen (prot3w): Correct rotation sequence; patch
168 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
170 * configure: Rebuilt to inhale new common/aclocal.m4.
173 Thu Sep 10 11:50:54 1998 Doug Evans <devans@canuck.cygnus.com>
175 * r5900.igen (plzcw): Make `i' signed.
177 Wed Sep 9 15:02:10 1998 Doug Evans <devans@canuck.cygnus.com>
179 * sim-main.h (COP0_COUNT,COP0_COMPARE,status_IM7): New macros.
180 * sky-engine.c (cpu_issue): Increment COP0_COUNT and signal an
181 interrupt if == COP0_COMPARE and interrupt masks/enables allow it.
182 * interp.c (signal_exception, sky version): Handle INT 2.
184 Wed Sep 9 11:28:20 1998 Ron Unrau <runrau@cygnus.com>
186 * sim-main.h: track COP0 registers
187 * interp.c (sim_{fetch,store}_register): read/write COP0 registers
189 Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
191 * r5900.igen (mtsab): Correct typo in input register.
193 * sim-main.h (TMP_*): New macros for accessing local 128-bit
194 temporary for multimedia instructions.
195 * r5900.igen (*): Convert most instructions to use new TMP
196 macros to store output result during computation.
199 start-sanitize-tx3904
200 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
202 * dv-tx3904sio.c: Include sim-assert.h.
204 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
206 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
207 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
208 Reorganize target-specific sim-hardware checks.
209 * configure: rebuilt.
210 * interp.c (sim_open): For tx39 target boards, set
211 OPERATING_ENVIRONMENT, add tx3904sio devices.
212 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
213 ROM executables. Install dv-sockser into sim-modules list.
215 * dv-tx3904irc.c: Compiler warning clean-up.
216 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
217 frequent hw-trace messages.
221 Tue Aug 11 13:52:16 1998 Frank Ch. Eigler <fche@cygnus.com>
223 * interp.c (signal_exception): Set IP3 bit in CAUSE on
227 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
229 * vr.igen (MulAcc): Identify as a vr4100 specific function.
231 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
233 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
236 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
237 * mips.igen: Define vr4100 model. Include vr.igen.
238 start-sanitize-cygnus
239 * vr5400.igen: Move instructions to vr.igen
240 * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen.
242 start-sanitize-vr4320
243 * vr4320.igen: Move instructions to vr.igen.
244 * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen.
248 Fri Jul 24 16:01:03 1998 Ian Carmichael <iancarm@cygnus.com>
250 * interp.c (MONITOR_SIZE): Make 1MB monitor for SKY.
251 * mips.igen (BREAK): Fix 0xffff2 monitor call. Slightly less
252 confusing message if not enough --load-next options appear.
254 * sky-pke.h (VUx_MEMx_SRCADDR_START): Move to 0x19800000 range.
255 * sim-main.c (GDB_COMM_AREA): Move to 0x19810000.
256 * sky-gdb.c (init_fifo_bp_cache): Use VIO_BASE when reading GDB area.
257 (resume_handler): Same.
258 (suspend_handler): Same.
260 Wed Jul 22 13:04:13 1998 Frank Ch. Eigler <fche@cygnus.com>
262 * mips.igen (break): Implement LOAD_INSTRUCTION ("break 0xffff1")
263 to trigger multi-phase load.
265 * sim-main.c: Include sim-assert.h for ASSERT macro.
266 * sim-main.h (PRINTF_INSTRUCTION): Correct bit pattern for
269 Tue Jul 21 18:37:36 1998 Ian Carmichael <iancarm@cygnus.com>
272 * interp.c (sim_open): Initialize TLB.
273 * interp.c (signal_exceptions): New 5900 handling.
274 * r5900.igen (TLBWR, TLBWI, TLBR, TLBP): Make these work.
275 * sim-main.c (tlb_try_match, tlb_lookup): New functions.
276 (address_translation): Use the TLB.
277 * sim-main.h (r4000_tlb_entry_t): New type.
278 (TLB_*): New constants.
279 (COP0_*): New register names.
281 Sky character I/O device.
282 * sky-psio.c: New file.
283 * sky-psio.h: New file.
284 * Makefile.in: Add sky-psio.o.
288 Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
290 * r5900.igen (r59fp_overflow): Replace argument ANS with argument
293 (r59fp_store): Update calls.
294 (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
297 start-sanitize-branchbug4011
298 Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com>
300 * interp.c (OPTION_BRANCH_BUG_4011): Add.
301 (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
302 (mips_options): Define the option.
303 * mips.igen (check_4011_branch_bug): New.
304 (mark_4011_branch_bug): New.
305 (all branch insn): Call mark_branch_bug, and check_branch_bug.
306 * sim-main.h (branchbug4011_option, branchbug4011_last_target,
307 branchbug4011_last_cia, BRANCHBUG4011_OPTION,
308 BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
309 check_branch_bug, mark_branch_bug): Define.
311 end-sanitize-branchbug4011
312 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
314 * mips.igen (check_mf_hilo): Correct check.
317 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
319 * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
320 COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
321 purpose registers, add 8 COP0 break-point registers, add 64 COP0
322 performance registers.
324 * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
325 MFP* instructions. Just transfer value to/from corresponding
328 * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
329 status is always true.
330 (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
331 (EI, DI): Set/clear Status-EIE bit.
335 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
337 * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
341 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
344 * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
346 * sky-gdb.c: Include "sim-assert.h".
349 * sim-main.h (interrupt_event): Add prototype.
351 start-sanitize-tx3904
352 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
353 register_ptr, register_value.
354 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
357 * sim-main.h (tracefh): Make extern.
359 start-sanitize-tx3904
360 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
362 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
363 Reduce unnecessarily high timer event frequency.
364 * dv-tx3904cpu.c: Ditto for interrupt event.
368 Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com>
370 * interp.c (decode_coproc): Removed COP2 branches.
371 * r5900.igen: Moved COP2 branch instructions here.
372 * mips.igen: Restricted COPz == COP2 bit pattern to
373 exclude COP2 branches.
376 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
378 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
380 (interrupt_event): Made non-static.
381 start-sanitize-tx3904
383 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
384 interchange of configuration values for external vs. internal
388 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
390 * mips.igen (BREAK): Moved code to here for
391 simulator-reserved break instructions.
392 * gencode.c (build_instruction): Ditto.
393 * interp.c (signal_exception): Code moved from here. Non-
394 reserved instructions now use exception vector, rather
396 * sim-main.h: Moved magic constants to here.
398 start-sanitize-tx3904
399 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
401 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
402 register upon non-zero interrupt event level, clear upon zero
404 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
405 by passing zero event value.
406 (*_io_{read,write}_buffer): Endianness fixes.
407 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
408 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
410 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
411 serial I/O and timer module at base address 0xFFFF0000.
414 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
416 * mips.igen (SWC1) : Correct the handling of ReverseEndian
419 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
421 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
425 start-sanitize-tx3904
426 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
428 * dv-tx3904tmr.c: New file - implements tx3904 timer.
429 * dv-tx3904{irc,cpu}.c: Mild reformatting.
430 * configure.in: Include tx3904tmr in hw_device list.
431 * configure: Rebuilt.
432 * interp.c (sim_open): Instantiate three timer instances.
433 Fix address typo of tx3904irc instance.
437 Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
439 * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
440 Select corresponding check_mt_hilo function.
441 (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
444 * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
448 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
450 * interp.c (signal_exception): SystemCall exception now uses
451 the exception vector.
453 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
455 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
459 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
461 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
465 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
467 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
469 start-sanitize-tx3904
470 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
472 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
474 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
475 sim-main.h. Declare a struct hw_descriptor instead of struct
476 hw_device_descriptor.
479 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
481 * mips.igen (do_store_left, do_load_left): Compute nr of left and
482 right bits and then re-align left hand bytes to correct byte
483 lanes. Fix incorrect computation in do_store_left when loading
484 bytes from second word.
486 start-sanitize-tx3904
487 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
489 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
490 * interp.c (sim_open): Only create a device tree when HW is
493 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
494 * interp.c (signal_exception): Ditto.
497 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
499 * gencode.c: Mark BEGEZALL as LIKELY.
501 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
503 * sim-main.h (ALU32_END): Sign extend 32 bit results.
504 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
507 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
509 * interp.c (sim_fetch_register): Convert internal r5900 regs to
513 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
515 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
516 modules. Recognize TX39 target with "mips*tx39" pattern.
517 * configure: Rebuilt.
518 * sim-main.h (*): Added many macros defining bits in
519 TX39 control registers.
520 (SignalInterrupt): Send actual PC instead of NULL.
521 (SignalNMIReset): New exception type.
522 * interp.c (board): New variable for future use to identify
523 a particular board being simulated.
524 (mips_option_handler,mips_options): Added "--board" option.
525 (interrupt_event): Send actual PC.
526 (sim_open): Make memory layout conditional on board setting.
527 (signal_exception): Initial implementation of hardware interrupt
528 handling. Accept another break instruction variant for simulator
530 (decode_coproc): Implement RFE instruction for TX39.
531 (mips.igen): Decode RFE instruction as such.
532 start-sanitize-tx3904
533 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
534 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
535 bbegin to implement memory map.
536 * dv-tx3904cpu.c: New file.
537 * dv-tx3904irc.c: New file.
540 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
542 * mips.igen (check_mt_hilo): Create a separate r3900 version.
545 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
547 * r5900.igen: Replace the calls and the definition of the
548 function check_op_hilo_hi1lo1 with the pair
549 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
552 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
554 * tx.igen (madd,maddu): Replace calls to check_op_hilo
555 with calls to check_div_hilo.
557 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
559 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
560 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
561 Add special r3900 version of do_mult_hilo.
562 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
563 with calls to check_mult_hilo.
564 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
565 with calls to check_div_hilo.
567 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
569 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
570 Document a replacement.
572 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
574 * interp.c (sim_monitor): Make mon_printf work.
576 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
578 * sim-main.h (INSN_NAME): New arg `cpu'.
581 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
583 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
588 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
590 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
591 * r5900.igen (r59fp_overflow): Use.
593 * r5900.igen (r59fp_op3): Rename to
594 (r59fp_mula): This, delete opm argument.
595 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
596 (r59fp_mula): Overflowing product propogates through to result.
597 (r59fp_mula): ACC to the MAX propogates to result.
598 (r59fp_mula): Underflow during multiply only sets SU.
601 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
603 * configure: Regenerated to track ../common/aclocal.m4 changes.
605 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
607 * configure: Regenerated to track ../common/aclocal.m4 changes.
610 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
612 * acconfig.h: New file.
613 * configure.in: Reverted change of Apr 24; use sinclude again.
615 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
617 * configure: Regenerated to track ../common/aclocal.m4 changes.
620 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
622 * configure.in: Don't call sinclude.
624 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
626 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
628 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
630 * mips.igen (ERET): Implement.
632 * interp.c (decode_coproc): Return sign-extended EPC.
634 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
636 * interp.c (signal_exception): Do not ignore Trap.
637 (signal_exception): On TRAP, restart at exception address.
638 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
639 (signal_exception): Update.
640 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
641 so that TRAP instructions are caught.
643 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
645 * sim-main.h (struct hilo_access, struct hilo_history): Define,
646 contains HI/LO access history.
647 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
648 (HIACCESS, LOACCESS): Delete, replace with
649 (HIHISTORY, LOHISTORY): New macros.
650 (start-sanitize-r5900):
651 (struct sim_5900_cpu): Make hi1access, lo1access of type
653 (HI1ACCESS, LO1ACCESS): Delete, replace with
654 (HI1HISTORY, LO1HISTORY): New macros.
655 (end-sanitize-r5900):
656 (CHECKHILO): Delete all, moved to mips.igen
658 * gencode.c (build_instruction): Do not generate checks for
659 correct HI/LO register usage.
661 * interp.c (old_engine_run): Delete checks for correct HI/LO
664 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
665 check_mf_cycles): New functions.
666 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
667 do_divu, domultx, do_mult, do_multu): Use.
669 * tx.igen ("madd", "maddu"): Use.
670 (start-sanitize-r5900):
672 r5900.igen: Update all HI/LO checks.
673 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
674 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
675 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
676 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
677 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
679 (end-sanitize-r5900):
682 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
684 * interp.c (decode_coproc): Correct CMFC2/QMTC2
687 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
688 instead of a single 128-bit access.
692 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
694 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
695 * interp.c (cop_[ls]q): Fixes corresponding to above.
699 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
701 * interp.c (decode_coproc): Adapt COP2 micro interlock to
702 clarified specs. Reset "M" bit; exit also on "E" bit.
706 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
708 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
709 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
711 * r5900.igen (r59fp_unpack): New function.
712 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
713 RSQRT.S, SQRT.S): Use.
714 (r59fp_zero): New function.
715 (r59fp_overflow): Generate r5900 specific overflow value.
716 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
718 (CVT.S.W, CVT.W.S): Exchange implementations.
720 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
724 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
726 * configure.in (tx19, sim_use_gen): Switch to igen.
727 * configure: Re-build.
731 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
733 * interp.c (decode_coproc): Make COP2 branch code compile after
734 igen signature changes.
737 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
739 * mips.igen (DSRAV): Use function do_dsrav.
740 (SRAV): Use new function do_srav.
742 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
743 (B): Sign extend 11 bit immediate.
744 (EXT-B*): Shift 16 bit immediate left by 1.
745 (ADDIU*): Don't sign extend immediate value.
747 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
749 * m16run.c (sim_engine_run): Restore CIA after handling an event.
752 * mips.igen (mtc0): Valid tx19 instruction.
755 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
758 * mips.igen (delayslot32, nullify_next_insn): New functions.
759 (m16.igen): Always include.
760 (do_*): Add more tracing.
762 * m16.igen (delayslot16): Add NIA argument, could be called by a
763 32 bit MIPS16 instruction.
765 * interp.c (ifetch16): Move function from here.
766 * sim-main.c (ifetch16): To here.
768 * sim-main.c (ifetch16, ifetch32): Update to match current
769 implementations of LH, LW.
770 (signal_exception): Don't print out incorrect hex value of illegal
773 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
775 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
778 * m16.igen: Implement MIPS16 instructions.
780 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
781 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
782 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
783 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
784 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
785 bodies of corresponding code from 32 bit insn to these. Also used
786 by MIPS16 versions of functions.
788 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
789 (IMEM16): Drop NR argument from macro.
792 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
794 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
795 of VU lower instruction.
799 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
801 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
804 * sim-main.h: Removed attempt at allowing 128-bit access.
808 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
810 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
812 * interp.c (decode_coproc): Refer to VU CIA as a "special"
813 register, not as a "misc" register. Aha. Add activity
814 assertions after VCALLMS* instructions.
818 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
820 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
821 to upper code of generated VU instruction.
825 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
827 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
829 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
832 * r5900.igen (SQC2): Thinko.
836 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
838 * interp.c (*): Adapt code to merged VU device & state structs.
839 (decode_coproc): Execute COP2 each macroinstruction without
840 pipelining, by stepping VU to completion state. Adapted to
841 read_vu_*_reg style of register access.
843 * mips.igen ([SL]QC2): Removed these COP2 instructions.
845 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
847 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
850 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
852 * Makefile.in (SIM_OBJS): Add sim-main.o.
854 * sim-main.h (address_translation, load_memory, store_memory,
855 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
857 (pr_addr, pr_uword64): Declare.
858 (sim-main.c): Include when H_REVEALS_MODULE_P.
860 * interp.c (address_translation, load_memory, store_memory,
861 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
863 * sim-main.c: To here. Fix compilation problems.
865 * configure.in: Enable inlining.
866 * configure: Re-config.
868 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
870 * configure: Regenerated to track ../common/aclocal.m4 changes.
872 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
874 * mips.igen: Include tx.igen.
875 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
876 * tx.igen: New file, contains MADD and MADDU.
878 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
879 the hardwired constant `7'.
880 (store_memory): Ditto.
881 (LOADDRMASK): Move definition to sim-main.h.
883 mips.igen (MTC0): Enable for r3900.
886 mips.igen (do_load_byte): Delete.
887 (do_load, do_store, do_load_left, do_load_write, do_store_left,
888 do_store_right): New functions.
889 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
891 configure.in: Let the tx39 use igen again.
894 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
896 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
897 not an address sized quantity. Return zero for cache sizes.
899 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
901 * mips.igen (r3900): r3900 does not support 64 bit integer
905 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
907 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
911 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
913 * interp.c (decode_coproc): Continuing COP2 work.
914 (cop_[ls]q): Make sky-target-only.
916 * sim-main.h (COP_[LS]Q): Make sky-target-only.
918 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
920 * configure.in (mipstx39*-*-*): Use gencode simulator rather
922 * configure : Rebuild.
925 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
927 * interp.c (decode_coproc): Added a missing TARGET_SKY check
928 around COP2 implementation skeleton.
932 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
934 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
936 * interp.c (sim_{load,store}_register): Use new vu[01]_device
937 static to access VU registers.
938 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
939 decoding. Work in progress.
941 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
942 overlapping/redundant bit pattern.
943 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
946 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
949 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
950 access to coprocessor registers.
952 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
954 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
956 * configure: Regenerated to track ../common/aclocal.m4 changes.
958 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
960 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
962 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
964 * configure: Regenerated to track ../common/aclocal.m4 changes.
965 * config.in: Regenerated to track ../common/aclocal.m4 changes.
967 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
969 * configure: Regenerated to track ../common/aclocal.m4 changes.
971 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
973 * interp.c (Max, Min): Comment out functions. Not yet used.
975 start-sanitize-vr4320
976 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
978 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
981 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
983 * configure: Regenerated to track ../common/aclocal.m4 changes.
985 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
987 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
988 configurable settings for stand-alone simulator.
991 * configure.in: Added --with-sim-gpu2 option to specify path of
992 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
993 links/compiles stand-alone simulator with this library.
995 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
997 * configure.in: Added X11 search, just in case.
999 * configure: Regenerated.
1001 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1003 * interp.c (sim_write, sim_read, load_memory, store_memory):
1004 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1006 start-sanitize-vr4320
1007 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
1009 * vr4320.igen (clz,dclz) : Added.
1010 (dmac): Replaced 99, with LO.
1013 start-sanitize-cygnus
1014 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
1016 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
1019 start-sanitize-vr4320
1020 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
1022 * vr4320.igen: New file.
1023 * Makefile.in (vr4320.igen) : Added.
1024 * configure.in (mips64vr4320-*-*): Added.
1025 * configure : Rebuilt.
1026 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
1027 Add the vr4320 model entry and mark the vr4320 insn as necessary.
1030 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1032 * sim-main.h (GETFCC): Return an unsigned value.
1034 start-sanitize-r5900
1035 * r5900.igen: Use an unsigned array index variable `i'.
1036 (QFSRV): Ditto for variable bytes.
1039 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1041 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1042 (DADD): Result destination is RD not RT.
1044 start-sanitize-r5900
1045 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
1046 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
1050 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1052 * sim-main.h (HIACCESS, LOACCESS): Always define.
1054 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1056 * interp.c (sim_info): Delete.
1058 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1060 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1061 (mips_option_handler): New argument `cpu'.
1062 (sim_open): Update call to sim_add_option_table.
1064 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1066 * mips.igen (CxC1): Add tracing.
1068 start-sanitize-r5900
1069 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1071 * r5900.igen (StoreFP): Delete.
1072 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
1074 (rsqrt.s, sqrt.s): Implement.
1075 (r59cond): New function.
1076 (C.COND.S): Call r59cond in assembler line.
1077 (cvt.w.s, cvt.s.w): Implement.
1079 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
1082 * sim-main.h: Define an enum of r5900 FCSR bit fields.
1085 start-sanitize-r5900
1086 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
1088 * r5900.igen: Add tracing to all p* instructions.
1090 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
1092 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
1093 to get gdb talking to re-aranged sim_cpu register structure.
1096 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1098 * sim-main.h (Max, Min): Declare.
1100 * interp.c (Max, Min): New functions.
1102 * mips.igen (BC1): Add tracing.
1104 start-sanitize-cygnus
1105 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
1107 * mdmx.igen: Tag all functions as requiring either with mdmx or
1111 start-sanitize-r5900
1112 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1114 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
1116 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
1118 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
1120 * r5900.igen: Rewrite.
1122 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
1124 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
1125 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
1128 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1130 * interp.c Added memory map for stack in vr4100
1132 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1134 * interp.c (load_memory): Add missing "break"'s.
1136 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1138 * interp.c (sim_store_register, sim_fetch_register): Pass in
1139 length parameter. Return -1.
1141 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1143 * interp.c: Added hardware init hook, fixed warnings.
1145 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1147 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1149 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1151 * interp.c (ifetch16): New function.
1153 * sim-main.h (IMEM32): Rename IMEM.
1154 (IMEM16_IMMED): Define.
1156 (DELAY_SLOT): Update.
1158 * m16run.c (sim_engine_run): New file.
1160 * m16.igen: All instructions except LB.
1161 (LB): Call do_load_byte.
1162 * mips.igen (do_load_byte): New function.
1163 (LB): Call do_load_byte.
1165 * mips.igen: Move spec for insn bit size and high bit from here.
1166 * Makefile.in (tmp-igen, tmp-m16): To here.
1168 * m16.dc: New file, decode mips16 instructions.
1170 * Makefile.in (SIM_NO_ALL): Define.
1171 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1174 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
1178 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1180 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1181 point unit to 32 bit registers.
1182 * configure: Re-generate.
1184 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1186 * configure.in (sim_use_gen): Make IGEN the default simulator
1187 generator for generic 32 and 64 bit mips targets.
1188 * configure: Re-generate.
1190 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1192 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1195 * interp.c (sim_fetch_register, sim_store_register): Read/write
1196 FGR from correct location.
1197 (sim_open): Set size of FGR's according to
1198 WITH_TARGET_FLOATING_POINT_BITSIZE.
1200 * sim-main.h (FGR): Store floating point registers in a separate
1203 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1205 * configure: Regenerated to track ../common/aclocal.m4 changes.
1207 start-sanitize-cygnus
1208 * mdmx.igen: Mark all instructions as 64bit/fp specific.
1211 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1213 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1215 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1217 * interp.c (pending_tick): New function. Deliver pending writes.
1219 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1220 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1221 it can handle mixed sized quantites and single bits.
1223 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1225 * interp.c (oengine.h): Do not include when building with IGEN.
1226 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1227 (sim_info): Ditto for PROCESSOR_64BIT.
1228 (sim_monitor): Replace ut_reg with unsigned_word.
1229 (*): Ditto for t_reg.
1230 (LOADDRMASK): Define.
1231 (sim_open): Remove defunct check that host FP is IEEE compliant,
1232 using software to emulate floating point.
1233 (value_fpr, ...): Always compile, was conditional on HASFPU.
1235 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1237 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1240 * interp.c (SD, CPU): Define.
1241 (mips_option_handler): Set flags in each CPU.
1242 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1243 (sim_close): Do not clear STATE, deleted anyway.
1244 (sim_write, sim_read): Assume CPU zero's vm should be used for
1246 (sim_create_inferior): Set the PC for all processors.
1247 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1249 (mips16_entry): Pass correct nr of args to store_word, load_word.
1250 (ColdReset): Cold reset all cpu's.
1251 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1252 (sim_monitor, load_memory, store_memory, signal_exception): Use
1253 `CPU' instead of STATE_CPU.
1256 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1259 * sim-main.h (signal_exception): Add sim_cpu arg.
1260 (SignalException*): Pass both SD and CPU to signal_exception.
1261 * interp.c (signal_exception): Update.
1263 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1265 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1266 address_translation): Ditto
1267 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1269 start-sanitize-cygnus
1270 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
1272 (ByteAlign): Use StoreFPR, pass args in correct order.
1275 start-sanitize-r5900
1276 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1278 * configure.in (sim_igen_filter): For r5900, configure as SMP.
1281 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1283 * configure: Regenerated to track ../common/aclocal.m4 changes.
1285 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1287 start-sanitize-r5900
1288 * configure.in (sim_igen_filter): For r5900, use igen.
1289 * configure: Re-generate.
1292 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1294 * mips.igen (model): Map processor names onto BFD name.
1296 * sim-main.h (CPU_CIA): Delete.
1297 (SET_CIA, GET_CIA): Define
1299 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1301 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1304 * configure.in (default_endian): Configure a big-endian simulator
1306 * configure: Re-generate.
1308 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1310 * configure: Regenerated to track ../common/aclocal.m4 changes.
1312 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1314 * interp.c (sim_monitor): Handle Densan monitor outbyte
1315 and inbyte functions.
1317 1997-12-29 Felix Lee <flee@cygnus.com>
1319 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1321 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1323 * Makefile.in (tmp-igen): Arrange for $zero to always be
1324 reset to zero after every instruction.
1326 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1328 * configure: Regenerated to track ../common/aclocal.m4 changes.
1331 start-sanitize-cygnus
1332 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1334 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1337 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
1339 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1340 vr5400 with the vr5000 as the default.
1343 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1345 * mips.igen (MSUB): Fix to work like MADD.
1346 * gencode.c (MSUB): Similarly.
1348 start-sanitize-cygnus
1349 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
1351 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1355 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1357 * configure: Regenerated to track ../common/aclocal.m4 changes.
1359 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1361 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1363 start-sanitize-cygnus
1364 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1365 (value_cc, store_cc): Implement.
1367 * sim-main.h: Add 8*3*8 bit accumulator.
1369 * vr5400.igen: Move mdmx instructins from here
1370 * mdmx.igen: To here - new file. Add/fix missing instructions.
1371 * mips.igen: Include mdmx.igen.
1372 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1375 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1377 * sim-main.h (sim-fpu.h): Include.
1379 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1380 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1381 using host independant sim_fpu module.
1383 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1385 * interp.c (signal_exception): Report internal errors with SIGABRT
1388 * sim-main.h (C0_CONFIG): New register.
1389 (signal.h): No longer include.
1391 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1393 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1395 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1397 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1399 * mips.igen: Tag vr5000 instructions.
1400 (ANDI): Was missing mipsIV model, fix assembler syntax.
1401 (do_c_cond_fmt): New function.
1402 (C.cond.fmt): Handle mips I-III which do not support CC field
1404 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1405 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1407 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1408 vr5000 which saves LO in a GPR separatly.
1410 * configure.in (enable-sim-igen): For vr5000, select vr5000
1411 specific instructions.
1412 * configure: Re-generate.
1414 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1416 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1418 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1419 fmt_uninterpreted_64 bit cases to switch. Convert to
1422 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1424 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1425 as specified in IV3.2 spec.
1426 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1428 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1430 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1431 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1432 (start-sanitize-r5900):
1433 (LWXC1, SWXC1): Delete from r5900 instruction set.
1434 (end-sanitize-r5900):
1435 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1436 PENDING_FILL versions of instructions. Simplify.
1438 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1440 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1442 (MTHI, MFHI): Disable code checking HI-LO.
1444 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1446 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1448 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1450 * gencode.c (build_mips16_operands): Replace IPC with cia.
1452 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1453 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1455 (UndefinedResult): Replace function with macro/function
1457 (sim_engine_run): Don't save PC in IPC.
1459 * sim-main.h (IPC): Delete.
1461 start-sanitize-cygnus
1462 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1463 (do_select): Rename function select.
1466 * interp.c (signal_exception, store_word, load_word,
1467 address_translation, load_memory, store_memory, cache_op,
1468 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1469 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1470 current instruction address - cia - argument.
1471 (sim_read, sim_write): Call address_translation directly.
1472 (sim_engine_run): Rename variable vaddr to cia.
1473 (signal_exception): Pass cia to sim_monitor
1475 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1476 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1477 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1479 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1480 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1483 * interp.c (signal_exception): Pass restart address to
1486 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1487 idecode.o): Add dependency.
1489 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1491 (DELAY_SLOT): Update NIA not PC with branch address.
1492 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1494 * mips.igen: Use CIA not PC in branch calculations.
1495 (illegal): Call SignalException.
1496 (BEQ, ADDIU): Fix assembler.
1498 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1500 * m16.igen (JALX): Was missing.
1502 * configure.in (enable-sim-igen): New configuration option.
1503 * configure: Re-generate.
1505 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1507 * interp.c (load_memory, store_memory): Delete parameter RAW.
1508 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1509 bypassing {load,store}_memory.
1511 * sim-main.h (ByteSwapMem): Delete definition.
1513 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1515 * interp.c (sim_do_command, sim_commands): Delete mips specific
1516 commands. Handled by module sim-options.
1518 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1519 (WITH_MODULO_MEMORY): Define.
1521 * interp.c (sim_info): Delete code printing memory size.
1523 * interp.c (mips_size): Nee sim_size, delete function.
1525 (monitor, monitor_base, monitor_size): Delete global variables.
1526 (sim_open, sim_close): Delete code creating monitor and other
1527 memory regions. Use sim-memopts module, via sim_do_commandf, to
1528 manage memory regions.
1529 (load_memory, store_memory): Use sim-core for memory model.
1531 * interp.c (address_translation): Delete all memory map code
1532 except line forcing 32 bit addresses.
1534 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1536 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1539 * interp.c (logfh, logfile): Delete globals.
1540 (sim_open, sim_close): Delete code opening & closing log file.
1541 (mips_option_handler): Delete -l and -n options.
1542 (OPTION mips_options): Ditto.
1544 * interp.c (OPTION mips_options): Rename option trace to dinero.
1545 (mips_option_handler): Update.
1547 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1549 * interp.c (fetch_str): New function.
1550 (sim_monitor): Rewrite using sim_read & sim_write.
1551 (sim_open): Check magic number.
1552 (sim_open): Write monitor vectors into memory using sim_write.
1553 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1554 (sim_read, sim_write): Simplify - transfer data one byte at a
1556 (load_memory, store_memory): Clarify meaning of parameter RAW.
1558 * sim-main.h (isHOST): Defete definition.
1559 (isTARGET): Mark as depreciated.
1560 (address_translation): Delete parameter HOST.
1562 * interp.c (address_translation): Delete parameter HOST.
1565 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1567 * gencode.c: Add tx49 configury and insns.
1568 * configure.in: Add tx49 configury.
1569 * configure: Update.
1572 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1576 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1577 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1579 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1581 * mips.igen: Add model filter field to records.
1583 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1585 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1587 interp.c (sim_engine_run): Do not compile function sim_engine_run
1588 when WITH_IGEN == 1.
1590 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1591 target architecture.
1593 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1594 igen. Replace with configuration variables sim_igen_flags /
1597 start-sanitize-r5900
1598 * r5900.igen: New file. Copy r5900 insns here.
1600 start-sanitize-cygnus
1601 * vr5400.igen: New file.
1603 * m16.igen: New file. Copy mips16 insns here.
1604 * mips.igen: From here.
1606 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1608 start-sanitize-cygnus
1609 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1611 * configure.in: Add mips64vr5400 target.
1612 * configure: Re-generate.
1615 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1617 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1619 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1621 * gencode.c (build_instruction): Follow sim_write's lead in using
1622 BigEndianMem instead of !ByteSwapMem.
1624 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1626 * configure.in (sim_gen): Dependent on target, select type of
1627 generator. Always select old style generator.
1629 configure: Re-generate.
1631 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1633 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1634 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1635 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1636 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1637 SIM_@sim_gen@_*, set by autoconf.
1639 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1643 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1644 CURRENT_FLOATING_POINT instead.
1646 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1647 (address_translation): Raise exception InstructionFetch when
1648 translation fails and isINSTRUCTION.
1650 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1651 sim_engine_run): Change type of of vaddr and paddr to
1653 (address_translation, prefetch, load_memory, store_memory,
1654 cache_op): Change type of vAddr and pAddr to address_word.
1656 * gencode.c (build_instruction): Change type of vaddr and paddr to
1659 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1661 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1662 macro to obtain result of ALU op.
1664 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1666 * interp.c (sim_info): Call profile_print.
1668 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1670 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1672 * sim-main.h (WITH_PROFILE): Do not define, defined in
1673 common/sim-config.h. Use sim-profile module.
1674 (simPROFILE): Delete defintion.
1676 * interp.c (PROFILE): Delete definition.
1677 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1678 (sim_close): Delete code writing profile histogram.
1679 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1681 (sim_engine_run): Delete code profiling the PC.
1683 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1685 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1687 * interp.c (sim_monitor): Make register pointers of type
1690 * sim-main.h: Make registers of type unsigned_word not
1693 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1695 start-sanitize-r5900
1696 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1697 ...): Move to sim-main.h
1700 * interp.c (sync_operation): Rename from SyncOperation, make
1701 global, add SD argument.
1702 (prefetch): Rename from Prefetch, make global, add SD argument.
1703 (decode_coproc): Make global.
1705 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1707 * gencode.c (build_instruction): Generate DecodeCoproc not
1708 decode_coproc calls.
1710 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1711 (SizeFGR): Move to sim-main.h
1712 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1713 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1714 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1716 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1717 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1718 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1719 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1720 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1721 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1723 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1725 (sim-alu.h): Include.
1726 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1727 (sim_cia): Typedef to instruction_address.
1729 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1731 * Makefile.in (interp.o): Rename generated file engine.c to
1736 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1738 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1740 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1742 * gencode.c (build_instruction): For "FPSQRT", output correct
1743 number of arguments to Recip.
1745 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1747 * Makefile.in (interp.o): Depends on sim-main.h
1749 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1751 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1752 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1753 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1754 STATE, DSSTATE): Define
1755 (GPR, FGRIDX, ..): Define.
1757 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1758 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1759 (GPR, FGRIDX, ...): Delete macros.
1761 * interp.c: Update names to match defines from sim-main.h
1763 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1765 * interp.c (sim_monitor): Add SD argument.
1766 (sim_warning): Delete. Replace calls with calls to
1768 (sim_error): Delete. Replace calls with sim_io_error.
1769 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1770 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1771 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1773 (mips_size): Rename from sim_size. Add SD argument.
1775 * interp.c (simulator): Delete global variable.
1776 (callback): Delete global variable.
1777 (mips_option_handler, sim_open, sim_write, sim_read,
1778 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1779 sim_size,sim_monitor): Use sim_io_* not callback->*.
1780 (sim_open): ZALLOC simulator struct.
1781 (PROFILE): Do not define.
1783 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1785 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1786 support.h with corresponding code.
1788 * sim-main.h (word64, uword64), support.h: Move definition to
1790 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1793 * Makefile.in: Update dependencies
1794 * interp.c: Do not include.
1796 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1798 * interp.c (address_translation, load_memory, store_memory,
1799 cache_op): Rename to from AddressTranslation et.al., make global,
1802 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1805 * interp.c (SignalException): Rename to signal_exception, make
1808 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1810 * sim-main.h (SignalException, SignalExceptionInterrupt,
1811 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1812 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1813 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1816 * interp.c, support.h: Use.
1818 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1820 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1821 to value_fpr / store_fpr. Add SD argument.
1822 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1823 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1825 * sim-main.h (ValueFPR, StoreFPR): Define.
1827 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1829 * interp.c (sim_engine_run): Check consistency between configure
1830 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1833 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1834 (mips_fpu): Configure WITH_FLOATING_POINT.
1835 (mips_endian): Configure WITH_TARGET_ENDIAN.
1836 * configure: Update.
1838 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840 * configure: Regenerated to track ../common/aclocal.m4 changes.
1842 start-sanitize-r5900
1843 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1845 * interp.c (MAX_REG): Allow up-to 128 registers.
1846 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1847 (REGISTER_SA): Ditto.
1848 (sim_open): Initialize register_widths for r5900 specific
1850 (sim_fetch_register, sim_store_register): Check for request of
1851 r5900 specific SA register. Check for request for hi 64 bits of
1852 r5900 specific registers.
1855 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1857 * configure: Regenerated.
1859 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1861 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1863 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1865 * gencode.c (print_igen_insn_models): Assume certain architectures
1866 include all mips* instructions.
1867 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1870 * Makefile.in (tmp.igen): Add target. Generate igen input from
1873 * gencode.c (FEATURE_IGEN): Define.
1874 (main): Add --igen option. Generate output in igen format.
1875 (process_instructions): Format output according to igen option.
1876 (print_igen_insn_format): New function.
1877 (print_igen_insn_models): New function.
1878 (process_instructions): Only issue warnings and ignore
1879 instructions when no FEATURE_IGEN.
1881 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1883 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1886 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1888 * configure: Regenerated to track ../common/aclocal.m4 changes.
1890 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1892 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1893 SIM_RESERVED_BITS): Delete, moved to common.
1894 (SIM_EXTRA_CFLAGS): Update.
1896 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1898 * configure.in: Configure non-strict memory alignment.
1899 * configure: Regenerated to track ../common/aclocal.m4 changes.
1901 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1903 * configure: Regenerated to track ../common/aclocal.m4 changes.
1905 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1907 * gencode.c (SDBBP,DERET): Added (3900) insns.
1908 (RFE): Turn on for 3900.
1909 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1910 (dsstate): Made global.
1911 (SUBTARGET_R3900): Added.
1912 (CANCELDELAYSLOT): New.
1913 (SignalException): Ignore SystemCall rather than ignore and
1914 terminate. Add DebugBreakPoint handling.
1915 (decode_coproc): New insns RFE, DERET; and new registers Debug
1916 and DEPC protected by SUBTARGET_R3900.
1917 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1919 * Makefile.in,configure.in: Add mips subtarget option.
1920 * configure: Update.
1922 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1924 * gencode.c: Add r3900 (tx39).
1927 * gencode.c: Fix some configuration problems by improving
1928 the relationship between tx19 and tx39.
1931 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1933 * gencode.c (build_instruction): Don't need to subtract 4 for
1936 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1938 * interp.c: Correct some HASFPU problems.
1940 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1942 * configure: Regenerated to track ../common/aclocal.m4 changes.
1944 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1946 * interp.c (mips_options): Fix samples option short form, should
1949 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1951 * interp.c (sim_info): Enable info code. Was just returning.
1953 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1955 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1958 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1960 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1962 (build_instruction): Ditto for LL.
1965 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1967 * mips/configure.in, mips/gencode: Add tx19/r1900.
1970 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1972 * configure: Regenerated to track ../common/aclocal.m4 changes.
1974 start-sanitize-r5900
1975 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1977 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1978 for overflow due to ABS of MININT, set result to MAXINT.
1979 (build_instruction): For "psrlvw", signextend bit 31.
1982 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1984 * configure: Regenerated to track ../common/aclocal.m4 changes.
1987 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1989 * interp.c (sim_open): Add call to sim_analyze_program, update
1992 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1994 * interp.c (sim_kill): Delete.
1995 (sim_create_inferior): Add ABFD argument. Set PC from same.
1996 (sim_load): Move code initializing trap handlers from here.
1997 (sim_open): To here.
1998 (sim_load): Delete, use sim-hload.c.
2000 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2002 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2004 * configure: Regenerated to track ../common/aclocal.m4 changes.
2007 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2009 * interp.c (sim_open): Add ABFD argument.
2010 (sim_load): Move call to sim_config from here.
2011 (sim_open): To here. Check return status.
2013 start-sanitize-r5900
2014 * gencode.c (build_instruction): Do not define x8000000000000000,
2015 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
2018 start-sanitize-r5900
2019 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2021 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
2022 "pdivuw" check for overflow due to signed divide by -1.
2025 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2027 * gencode.c (build_instruction): Two arg MADD should
2028 not assign result to $0.
2030 start-sanitize-r5900
2031 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
2033 * gencode.c (build_instruction): For "ppac5" use unsigned
2034 arrithmetic so that the sign bit doesn't smear when right shifted.
2035 (build_instruction): For "pdiv" perform sign extension when
2036 storing results in HI and LO.
2037 (build_instructions): For "pdiv" and "pdivbw" check for
2039 (build_instruction): For "pmfhl.slw" update hi part of dest
2040 register as well as low part.
2041 (build_instruction): For "pmfhl" portably handle long long values.
2042 (build_instruction): For "pmfhl.sh" correctly negative values.
2043 Store half words 2 and three in the correct place.
2044 (build_instruction): For "psllvw", sign extend value after shift.
2047 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2049 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2050 * sim/mips/configure.in: Regenerate.
2052 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2054 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2055 signed8, unsigned8 et.al. types.
2057 start-sanitize-r5900
2058 * gencode.c (build_instruction): For PMULTU* do not sign extend
2059 registers. Make generated code easier to debug.
2062 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2063 hosts when selecting subreg.
2065 start-sanitize-r5900
2066 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
2068 * gencode.c (type_for_data_len): For 32bit operations concerned
2069 with overflow, perform op using 64bits.
2070 (build_instruction): For PADD, always compute operation using type
2071 returned by type_for_data_len.
2072 (build_instruction): For PSUBU, when overflow, saturate to zero as
2076 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2078 start-sanitize-r5900
2079 * gencode.c (build_instruction): Handle "pext5" according to
2080 version 1.95 of the r5900 ISA.
2082 * gencode.c (build_instruction): Handle "ppac5" according to
2083 version 1.95 of the r5900 ISA.
2086 * interp.c (sim_engine_run): Reset the ZERO register to zero
2087 regardless of FEATURE_WARN_ZERO.
2088 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2090 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2092 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2093 (SignalException): For BreakPoints ignore any mode bits and just
2095 (SignalException): Always set the CAUSE register.
2097 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2099 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2100 exception has been taken.
2102 * interp.c: Implement the ERET and mt/f sr instructions.
2104 start-sanitize-r5900
2105 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
2107 * gencode.c (build_instruction): For paddu, extract unsigned
2110 * gencode.c (build_instruction): Saturate padds instead of padd
2114 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2116 * interp.c (SignalException): Don't bother restarting an
2119 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2121 * interp.c (SignalException): Really take an interrupt.
2122 (interrupt_event): Only deliver interrupts when enabled.
2124 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2126 * interp.c (sim_info): Only print info when verbose.
2127 (sim_info) Use sim_io_printf for output.
2129 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2131 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2134 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2136 * interp.c (sim_do_command): Check for common commands if a
2137 simulator specific command fails.
2139 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2141 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2142 and simBE when DEBUG is defined.
2144 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2146 * interp.c (interrupt_event): New function. Pass exception event
2147 onto exception handler.
2149 * configure.in: Check for stdlib.h.
2150 * configure: Regenerate.
2152 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2153 variable declaration.
2154 (build_instruction): Initialize memval1.
2155 (build_instruction): Add UNUSED attribute to byte, bigend,
2157 (build_operands): Ditto.
2159 * interp.c: Fix GCC warnings.
2160 (sim_get_quit_code): Delete.
2162 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2163 * Makefile.in: Ditto.
2164 * configure: Re-generate.
2166 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2168 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2170 * interp.c (mips_option_handler): New function parse argumes using
2172 (myname): Replace with STATE_MY_NAME.
2173 (sim_open): Delete check for host endianness - performed by
2175 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2176 (sim_open): Move much of the initialization from here.
2177 (sim_load): To here. After the image has been loaded and
2179 (sim_open): Move ColdReset from here.
2180 (sim_create_inferior): To here.
2181 (sim_open): Make FP check less dependant on host endianness.
2183 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2185 * interp.c (sim_set_callbacks): Delete.
2187 * interp.c (membank, membank_base, membank_size): Replace with
2188 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2189 (sim_open): Remove call to callback->init. gdb/run do this.
2193 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2195 * interp.c (big_endian_p): Delete, replaced by
2196 current_target_byte_order.
2198 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2200 * interp.c (host_read_long, host_read_word, host_swap_word,
2201 host_swap_long): Delete. Using common sim-endian.
2202 (sim_fetch_register, sim_store_register): Use H2T.
2203 (pipeline_ticks): Delete. Handled by sim-events.
2205 (sim_engine_run): Update.
2207 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2209 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2211 (SignalException): To here. Signal using sim_engine_halt.
2212 (sim_stop_reason): Delete, moved to common.
2214 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2216 * interp.c (sim_open): Add callback argument.
2217 (sim_set_callbacks): Delete SIM_DESC argument.
2220 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2222 * Makefile.in (SIM_OBJS): Add common modules.
2224 * interp.c (sim_set_callbacks): Also set SD callback.
2225 (set_endianness, xfer_*, swap_*): Delete.
2226 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2227 Change to functions using sim-endian macros.
2228 (control_c, sim_stop): Delete, use common version.
2229 (simulate): Convert into.
2230 (sim_engine_run): This function.
2231 (sim_resume): Delete.
2233 * interp.c (simulation): New variable - the simulator object.
2234 (sim_kind): Delete global - merged into simulation.
2235 (sim_load): Cleanup. Move PC assignment from here.
2236 (sim_create_inferior): To here.
2238 * sim-main.h: New file.
2239 * interp.c (sim-main.h): Include.
2241 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2243 * configure: Regenerated to track ../common/aclocal.m4 changes.
2245 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2247 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2249 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2251 * gencode.c (build_instruction): DIV instructions: check
2252 for division by zero and integer overflow before using
2253 host's division operation.
2255 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2257 * Makefile.in (SIM_OBJS): Add sim-load.o.
2258 * interp.c: #include bfd.h.
2259 (target_byte_order): Delete.
2260 (sim_kind, myname, big_endian_p): New static locals.
2261 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2262 after argument parsing. Recognize -E arg, set endianness accordingly.
2263 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2264 load file into simulator. Set PC from bfd.
2265 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2266 (set_endianness): Use big_endian_p instead of target_byte_order.
2268 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2270 * interp.c (sim_size): Delete prototype - conflicts with
2271 definition in remote-sim.h. Correct definition.
2273 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2275 * configure: Regenerated to track ../common/aclocal.m4 changes.
2278 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2280 * interp.c (sim_open): New arg `kind'.
2282 * configure: Regenerated to track ../common/aclocal.m4 changes.
2284 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2286 * configure: Regenerated to track ../common/aclocal.m4 changes.
2288 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2290 * interp.c (sim_open): Set optind to 0 before calling getopt.
2292 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2294 * configure: Regenerated to track ../common/aclocal.m4 changes.
2296 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2298 * interp.c : Replace uses of pr_addr with pr_uword64
2299 where the bit length is always 64 independent of SIM_ADDR.
2300 (pr_uword64) : added.
2302 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2304 * configure: Re-generate.
2306 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2308 * configure: Regenerate to track ../common/aclocal.m4 changes.
2310 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2312 * interp.c (sim_open): New SIM_DESC result. Argument is now
2314 (other sim_*): New SIM_DESC argument.
2316 start-sanitize-r5900
2317 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
2319 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2320 Change values to avoid overloading DOUBLEWORD which is tested
2322 * gencode.c: reinstate "offending code".
2325 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2327 * interp.c: Fix printing of addresses for non-64-bit targets.
2328 (pr_addr): Add function to print address based on size.
2329 start-sanitize-r5900
2330 * gencode.c: #ifdef out offending code until a permanent fix
2331 can be added. Code is causing build errors for non-5900 mips targets.
2334 start-sanitize-r5900
2335 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
2337 * gencode.c (process_instructions): Correct test for ISA dependent
2338 architecture bits in isa field of MIPS_DECODE.
2341 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2343 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2345 start-sanitize-r5900
2346 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2348 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2352 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2354 * gencode.c (build_mips16_operands): Correct computation of base
2355 address for extended PC relative instruction.
2357 start-sanitize-r5900
2358 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2360 * Makefile.in, configure, configure.in, gencode.c,
2361 interp.c, support.h: add r5900.
2364 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2366 * interp.c (mips16_entry): Add support for floating point cases.
2367 (SignalException): Pass floating point cases to mips16_entry.
2368 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2370 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2372 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2373 and then set the state to fmt_uninterpreted.
2374 (COP_SW): Temporarily set the state to fmt_word while calling
2377 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2379 * gencode.c (build_instruction): The high order may be set in the
2380 comparison flags at any ISA level, not just ISA 4.
2382 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2384 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2385 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2386 * configure.in: sinclude ../common/aclocal.m4.
2387 * configure: Regenerated.
2389 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2391 * configure: Rebuild after change to aclocal.m4.
2393 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2395 * configure configure.in Makefile.in: Update to new configure
2396 scheme which is more compatible with WinGDB builds.
2397 * configure.in: Improve comment on how to run autoconf.
2398 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2399 * Makefile.in: Use autoconf substitution to install common
2402 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2404 * gencode.c (build_instruction): Use BigEndianCPU instead of
2407 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2409 * interp.c (sim_monitor): Make output to stdout visible in
2410 wingdb's I/O log window.
2412 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2414 * support.h: Undo previous change to SIGTRAP
2417 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2419 * interp.c (store_word, load_word): New static functions.
2420 (mips16_entry): New static function.
2421 (SignalException): Look for mips16 entry and exit instructions.
2422 (simulate): Use the correct index when setting fpr_state after
2423 doing a pending move.
2425 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2427 * interp.c: Fix byte-swapping code throughout to work on
2428 both little- and big-endian hosts.
2430 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2432 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2433 with gdb/config/i386/xm-windows.h.
2435 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2437 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2438 that messes up arithmetic shifts.
2440 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2442 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2443 SIGTRAP and SIGQUIT for _WIN32.
2445 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2447 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2448 force a 64 bit multiplication.
2449 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2450 destination register is 0, since that is the default mips16 nop
2453 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2455 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2456 (build_endian_shift): Don't check proc64.
2457 (build_instruction): Always set memval to uword64. Cast op2 to
2458 uword64 when shifting it left in memory instructions. Always use
2459 the same code for stores--don't special case proc64.
2461 * gencode.c (build_mips16_operands): Fix base PC value for PC
2463 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2465 * interp.c (simJALDELAYSLOT): Define.
2466 (JALDELAYSLOT): Define.
2467 (INDELAYSLOT, INJALDELAYSLOT): Define.
2468 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2470 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2472 * interp.c (sim_open): add flush_cache as a PMON routine
2473 (sim_monitor): handle flush_cache by ignoring it
2475 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2477 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2479 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2480 (BigEndianMem): Rename to ByteSwapMem and change sense.
2481 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2482 BigEndianMem references to !ByteSwapMem.
2483 (set_endianness): New function, with prototype.
2484 (sim_open): Call set_endianness.
2485 (sim_info): Use simBE instead of BigEndianMem.
2486 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2487 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2488 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2489 ifdefs, keeping the prototype declaration.
2490 (swap_word): Rewrite correctly.
2491 (ColdReset): Delete references to CONFIG. Delete endianness related
2492 code; moved to set_endianness.
2494 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2496 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2497 * interp.c (CHECKHILO): Define away.
2498 (simSIGINT): New macro.
2499 (membank_size): Increase from 1MB to 2MB.
2500 (control_c): New function.
2501 (sim_resume): Rename parameter signal to signal_number. Add local
2502 variable prev. Call signal before and after simulate.
2503 (sim_stop_reason): Add simSIGINT support.
2504 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2506 (sim_warning): Delete call to SignalException. Do call printf_filtered
2508 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2509 a call to sim_warning.
2511 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2513 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2514 16 bit instructions.
2516 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2518 Add support for mips16 (16 bit MIPS implementation):
2519 * gencode.c (inst_type): Add mips16 instruction encoding types.
2520 (GETDATASIZEINSN): Define.
2521 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2522 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2524 (MIPS16_DECODE): New table, for mips16 instructions.
2525 (bitmap_val): New static function.
2526 (struct mips16_op): Define.
2527 (mips16_op_table): New table, for mips16 operands.
2528 (build_mips16_operands): New static function.
2529 (process_instructions): If PC is odd, decode a mips16
2530 instruction. Break out instruction handling into new
2531 build_instruction function.
2532 (build_instruction): New static function, broken out of
2533 process_instructions. Check modifiers rather than flags for SHIFT
2534 bit count and m[ft]{hi,lo} direction.
2535 (usage): Pass program name to fprintf.
2536 (main): Remove unused variable this_option_optind. Change
2537 ``*loptarg++'' to ``loptarg++''.
2538 (my_strtoul): Parenthesize && within ||.
2539 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2540 (simulate): If PC is odd, fetch a 16 bit instruction, and
2541 increment PC by 2 rather than 4.
2542 * configure.in: Add case for mips16*-*-*.
2543 * configure: Rebuild.
2545 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2547 * interp.c: Allow -t to enable tracing in standalone simulator.
2548 Fix garbage output in trace file and error messages.
2550 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2552 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2553 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2554 * configure.in: Simplify using macros in ../common/aclocal.m4.
2555 * configure: Regenerated.
2556 * tconfig.in: New file.
2558 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2560 * interp.c: Fix bugs in 64-bit port.
2561 Use ansi function declarations for msvc compiler.
2562 Initialize and test file pointer in trace code.
2563 Prevent duplicate definition of LAST_EMED_REGNUM.
2565 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2567 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2569 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2571 * interp.c (SignalException): Check for explicit terminating
2573 * gencode.c: Pass instruction value through SignalException()
2574 calls for Trap, Breakpoint and Syscall.
2576 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2578 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2579 only used on those hosts that provide it.
2580 * configure.in: Add sqrt() to list of functions to be checked for.
2581 * config.in: Re-generated.
2582 * configure: Re-generated.
2584 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2586 * gencode.c (process_instructions): Call build_endian_shift when
2587 expanding STORE RIGHT, to fix swr.
2588 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2589 clear the high bits.
2590 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2591 Fix float to int conversions to produce signed values.
2593 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2595 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2596 (process_instructions): Correct handling of nor instruction.
2597 Correct shift count for 32 bit shift instructions. Correct sign
2598 extension for arithmetic shifts to not shift the number of bits in
2599 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2600 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2602 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2603 It's OK to have a mult follow a mult. What's not OK is to have a
2604 mult follow an mfhi.
2605 (Convert): Comment out incorrect rounding code.
2607 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2609 * interp.c (sim_monitor): Improved monitor printf
2610 simulation. Tidied up simulator warnings, and added "--log" option
2611 for directing warning message output.
2612 * gencode.c: Use sim_warning() rather than WARNING macro.
2614 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2616 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2617 getopt1.o, rather than on gencode.c. Link objects together.
2618 Don't link against -liberty.
2619 (gencode.o, getopt.o, getopt1.o): New targets.
2620 * gencode.c: Include <ctype.h> and "ansidecl.h".
2621 (AND): Undefine after including "ansidecl.h".
2622 (ULONG_MAX): Define if not defined.
2623 (OP_*): Don't define macros; now defined in opcode/mips.h.
2624 (main): Call my_strtoul rather than strtoul.
2625 (my_strtoul): New static function.
2627 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2629 * gencode.c (process_instructions): Generate word64 and uword64
2630 instead of `long long' and `unsigned long long' data types.
2631 * interp.c: #include sysdep.h to get signals, and define default
2633 * (Convert): Work around for Visual-C++ compiler bug with type
2635 * support.h: Make things compile under Visual-C++ by using
2636 __int64 instead of `long long'. Change many refs to long long
2637 into word64/uword64 typedefs.
2639 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2641 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2642 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2644 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2645 (AC_PROG_INSTALL): Added.
2646 (AC_PROG_CC): Moved to before configure.host call.
2647 * configure: Rebuilt.
2649 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2651 * configure.in: Define @SIMCONF@ depending on mips target.
2652 * configure: Rebuild.
2653 * Makefile.in (run): Add @SIMCONF@ to control simulator
2655 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2656 * interp.c: Remove some debugging, provide more detailed error
2657 messages, update memory accesses to use LOADDRMASK.
2659 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2661 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2662 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2664 * configure: Rebuild.
2665 * config.in: New file, generated by autoheader.
2666 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2667 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2668 HAVE_ANINT and HAVE_AINT, as appropriate.
2669 * Makefile.in (run): Use @LIBS@ rather than -lm.
2670 (interp.o): Depend upon config.h.
2671 (Makefile): Just rebuild Makefile.
2672 (clean): Remove stamp-h.
2673 (mostlyclean): Make the same as clean, not as distclean.
2674 (config.h, stamp-h): New targets.
2676 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2678 * interp.c (ColdReset): Fix boolean test. Make all simulator
2681 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2683 * interp.c (xfer_direct_word, xfer_direct_long,
2684 swap_direct_word, swap_direct_long, xfer_big_word,
2685 xfer_big_long, xfer_little_word, xfer_little_long,
2686 swap_word,swap_long): Added.
2687 * interp.c (ColdReset): Provide function indirection to
2688 host<->simulated_target transfer routines.
2689 * interp.c (sim_store_register, sim_fetch_register): Updated to
2690 make use of indirected transfer routines.
2692 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2694 * gencode.c (process_instructions): Ensure FP ABS instruction
2696 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2697 system call support.
2699 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2701 * interp.c (sim_do_command): Complain if callback structure not
2704 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2706 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2707 support for Sun hosts.
2708 * Makefile.in (gencode): Ensure the host compiler and libraries
2709 used for cross-hosted build.
2711 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2713 * interp.c, gencode.c: Some more (TODO) tidying.
2715 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2717 * gencode.c, interp.c: Replaced explicit long long references with
2718 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2719 * support.h (SET64LO, SET64HI): Macros added.
2721 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2723 * configure: Regenerate with autoconf 2.7.
2725 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2727 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2728 * support.h: Remove superfluous "1" from #if.
2729 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2731 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2733 * interp.c (StoreFPR): Control UndefinedResult() call on
2734 WARN_RESULT manifest.
2736 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2738 * gencode.c: Tidied instruction decoding, and added FP instruction
2741 * interp.c: Added dineroIII, and BSD profiling support. Also
2742 run-time FP handling.
2744 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2746 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2747 gencode.c, interp.c, support.h: created.
projects / external / binutils.git / blob