1 2004-04-09 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (check_fmt): Remove.
4 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
5 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
6 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
7 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
8 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
9 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
10 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
11 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
12 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
13 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
15 2004-04-09 Chris Demetriou <cgd@broadcom.com>
17 * sb1.igen (check_sbx): New function.
18 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
20 2004-03-29 Chris Demetriou <cgd@broadcom.com>
21 Richard Sandiford <rsandifo@redhat.com>
23 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
24 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
25 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
26 separate implementations for mipsIV and mipsV. Use new macros to
27 determine whether the restrictions apply.
29 2004-01-19 Chris Demetriou <cgd@broadcom.com>
31 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
32 (check_mult_hilo): Improve comments.
33 (check_div_hilo): Likewise. Also, fork off a new version
34 to handle mips32/mips64 (since there are no hazards to check
37 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
39 * mips.igen (do_dmultx): Fix check for negative operands.
41 2003-05-16 Ian Lance Taylor <ian@airs.com>
43 * Makefile.in (SHELL): Make sure this is defined.
44 (various): Use $(SHELL) whenever we invoke move-if-change.
46 2003-05-03 Chris Demetriou <cgd@broadcom.com>
48 * cp1.c: Tweak attribution slightly.
51 * mdmx.igen: Likewise.
52 * mips3d.igen: Likewise.
55 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
57 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
60 2003-02-27 Andrew Cagney <cagney@redhat.com>
62 * interp.c (sim_open): Rename _bfd to bfd.
63 (sim_create_inferior): Ditto.
65 2003-01-14 Chris Demetriou <cgd@broadcom.com>
67 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
69 2003-01-14 Chris Demetriou <cgd@broadcom.com>
71 * mips.igen (EI, DI): Remove.
73 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
75 * Makefile.in (tmp-run-multi): Fix mips16 filter.
77 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
78 Andrew Cagney <ac131313@redhat.com>
79 Gavin Romig-Koch <gavin@redhat.com>
80 Graydon Hoare <graydon@redhat.com>
81 Aldy Hernandez <aldyh@redhat.com>
82 Dave Brolley <brolley@redhat.com>
83 Chris Demetriou <cgd@broadcom.com>
85 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
86 (sim_mach_default): New variable.
87 (mips64vr-*-*, mips64vrel-*-*): New configurations.
88 Add a new simulator generator, MULTI.
89 * configure: Regenerate.
90 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
91 (multi-run.o): New dependency.
92 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
93 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
94 (tmp-multi): Combine them.
95 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
96 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
97 (distclean-extra): New rule.
98 * sim-main.h: Include bfd.h.
99 (MIPS_MACH): New macro.
100 * mips.igen (vr4120, vr5400, vr5500): New models.
101 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
102 * vr.igen: Replace with new version.
104 2003-01-04 Chris Demetriou <cgd@broadcom.com>
106 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
107 * configure: Regenerate.
109 2002-12-31 Chris Demetriou <cgd@broadcom.com>
111 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
112 * mips.igen: Remove all invocations of check_branch_bug and
115 2002-12-16 Chris Demetriou <cgd@broadcom.com>
117 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
119 2002-07-30 Chris Demetriou <cgd@broadcom.com>
121 * mips.igen (do_load_double, do_store_double): New functions.
122 (LDC1, SDC1): Rename to...
123 (LDC1b, SDC1b): respectively.
124 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
126 2002-07-29 Michael Snyder <msnyder@redhat.com>
128 * cp1.c (fp_recip2): Modify initialization expression so that
129 GCC will recognize it as constant.
131 2002-06-18 Chris Demetriou <cgd@broadcom.com>
133 * mdmx.c (SD_): Delete.
134 (Unpredictable): Re-define, for now, to directly invoke
135 unpredictable_action().
136 (mdmx_acc_op): Fix error in .ob immediate handling.
138 2002-06-18 Andrew Cagney <cagney@redhat.com>
140 * interp.c (sim_firmware_command): Initialize `address'.
142 2002-06-16 Andrew Cagney <ac131313@redhat.com>
144 * configure: Regenerated to track ../common/aclocal.m4 changes.
146 2002-06-14 Chris Demetriou <cgd@broadcom.com>
147 Ed Satterthwaite <ehs@broadcom.com>
149 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
150 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
151 * mips.igen: Include mips3d.igen.
152 (mips3d): New model name for MIPS-3D ASE instructions.
153 (CVT.W.fmt): Don't use this instruction for word (source) format
155 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
156 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
157 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
158 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
159 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
160 (RSquareRoot1, RSquareRoot2): New macros.
161 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
162 (fp_rsqrt2): New functions.
163 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
164 * configure: Regenerate.
166 2002-06-13 Chris Demetriou <cgd@broadcom.com>
167 Ed Satterthwaite <ehs@broadcom.com>
169 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
170 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
171 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
172 (convert): Note that this function is not used for paired-single
174 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
175 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
176 (check_fmt_p): Enable paired-single support.
177 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
178 (PUU.PS): New instructions.
179 (CVT.S.fmt): Don't use this instruction for paired-single format
181 * sim-main.h (FP_formats): New value 'fmt_ps.'
182 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
183 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
185 2002-06-12 Chris Demetriou <cgd@broadcom.com>
187 * mips.igen: Fix formatting of function calls in
190 2002-06-12 Chris Demetriou <cgd@broadcom.com>
192 * mips.igen (MOVN, MOVZ): Trace result.
193 (TNEI): Print "tnei" as the opcode name in traces.
194 (CEIL.W): Add disassembly string for traces.
195 (RSQRT.fmt): Make location of disassembly string consistent
196 with other instructions.
198 2002-06-12 Chris Demetriou <cgd@broadcom.com>
200 * mips.igen (X): Delete unused function.
202 2002-06-08 Andrew Cagney <cagney@redhat.com>
204 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
206 2002-06-07 Chris Demetriou <cgd@broadcom.com>
207 Ed Satterthwaite <ehs@broadcom.com>
209 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
210 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
211 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
212 (fp_nmsub): New prototypes.
213 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
214 (NegMultiplySub): New defines.
215 * mips.igen (RSQRT.fmt): Use RSquareRoot().
216 (MADD.D, MADD.S): Replace with...
217 (MADD.fmt): New instruction.
218 (MSUB.D, MSUB.S): Replace with...
219 (MSUB.fmt): New instruction.
220 (NMADD.D, NMADD.S): Replace with...
221 (NMADD.fmt): New instruction.
222 (NMSUB.D, MSUB.S): Replace with...
223 (NMSUB.fmt): New instruction.
225 2002-06-07 Chris Demetriou <cgd@broadcom.com>
226 Ed Satterthwaite <ehs@broadcom.com>
228 * cp1.c: Fix more comment spelling and formatting.
229 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
230 (denorm_mode): New function.
231 (fpu_unary, fpu_binary): Round results after operation, collect
232 status from rounding operations, and update the FCSR.
233 (convert): Collect status from integer conversions and rounding
234 operations, and update the FCSR. Adjust NaN values that result
235 from conversions. Convert to use sim_io_eprintf rather than
236 fprintf, and remove some debugging code.
237 * cp1.h (fenr_FS): New define.
239 2002-06-07 Chris Demetriou <cgd@broadcom.com>
241 * cp1.c (convert): Remove unusable debugging code, and move MIPS
242 rounding mode to sim FP rounding mode flag conversion code into...
243 (rounding_mode): New function.
245 2002-06-07 Chris Demetriou <cgd@broadcom.com>
247 * cp1.c: Clean up formatting of a few comments.
248 (value_fpr): Reformat switch statement.
250 2002-06-06 Chris Demetriou <cgd@broadcom.com>
251 Ed Satterthwaite <ehs@broadcom.com>
254 * sim-main.h: Include cp1.h.
255 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
256 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
257 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
258 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
259 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
260 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
261 * cp1.c: Don't include sim-fpu.h; already included by
262 sim-main.h. Clean up formatting of some comments.
263 (NaN, Equal, Less): Remove.
264 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
265 (fp_cmp): New functions.
266 * mips.igen (do_c_cond_fmt): Remove.
267 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
268 Compare. Add result tracing.
269 (CxC1): Remove, replace with...
270 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
271 (DMxC1): Remove, replace with...
272 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
273 (MxC1): Remove, replace with...
274 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
276 2002-06-04 Chris Demetriou <cgd@broadcom.com>
278 * sim-main.h (FGRIDX): Remove, replace all uses with...
279 (FGR_BASE): New macro.
280 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
281 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
282 (NR_FGR, FGR): Likewise.
283 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
284 * mips.igen: Likewise.
286 2002-06-04 Chris Demetriou <cgd@broadcom.com>
288 * cp1.c: Add an FSF Copyright notice to this file.
290 2002-06-04 Chris Demetriou <cgd@broadcom.com>
291 Ed Satterthwaite <ehs@broadcom.com>
293 * cp1.c (Infinity): Remove.
294 * sim-main.h (Infinity): Likewise.
296 * cp1.c (fp_unary, fp_binary): New functions.
297 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
298 (fp_sqrt): New functions, implemented in terms of the above.
299 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
300 (Recip, SquareRoot): Remove (replaced by functions above).
301 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
302 (fp_recip, fp_sqrt): New prototypes.
303 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
304 (Recip, SquareRoot): Replace prototypes with #defines which
305 invoke the functions above.
307 2002-06-03 Chris Demetriou <cgd@broadcom.com>
309 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
310 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
311 file, remove PARAMS from prototypes.
312 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
313 simulator state arguments.
314 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
315 pass simulator state arguments.
316 * cp1.c (SD): Redefine as CPU_STATE(cpu).
317 (store_fpr, convert): Remove 'sd' argument.
318 (value_fpr): Likewise. Convert to use 'SD' instead.
320 2002-06-03 Chris Demetriou <cgd@broadcom.com>
322 * cp1.c (Min, Max): Remove #if 0'd functions.
323 * sim-main.h (Min, Max): Remove.
325 2002-06-03 Chris Demetriou <cgd@broadcom.com>
327 * cp1.c: fix formatting of switch case and default labels.
328 * interp.c: Likewise.
329 * sim-main.c: Likewise.
331 2002-06-03 Chris Demetriou <cgd@broadcom.com>
333 * cp1.c: Clean up comments which describe FP formats.
334 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
336 2002-06-03 Chris Demetriou <cgd@broadcom.com>
337 Ed Satterthwaite <ehs@broadcom.com>
339 * configure.in (mipsisa64sb1*-*-*): New target for supporting
340 Broadcom SiByte SB-1 processor configurations.
341 * configure: Regenerate.
342 * sb1.igen: New file.
343 * mips.igen: Include sb1.igen.
345 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
346 * mdmx.igen: Add "sb1" model to all appropriate functions and
348 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
349 (ob_func, ob_acc): Reference the above.
350 (qh_acc): Adjust to keep the same size as ob_acc.
351 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
352 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
354 2002-06-03 Chris Demetriou <cgd@broadcom.com>
356 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
358 2002-06-02 Chris Demetriou <cgd@broadcom.com>
359 Ed Satterthwaite <ehs@broadcom.com>
361 * mips.igen (mdmx): New (pseudo-)model.
362 * mdmx.c, mdmx.igen: New files.
363 * Makefile.in (SIM_OBJS): Add mdmx.o.
364 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
366 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
367 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
368 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
369 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
370 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
371 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
372 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
373 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
374 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
375 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
376 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
377 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
378 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
379 (qh_fmtsel): New macros.
380 (_sim_cpu): New member "acc".
381 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
382 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
384 2002-05-01 Chris Demetriou <cgd@broadcom.com>
386 * interp.c: Use 'deprecated' rather than 'depreciated.'
387 * sim-main.h: Likewise.
389 2002-05-01 Chris Demetriou <cgd@broadcom.com>
391 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
392 which wouldn't compile anyway.
393 * sim-main.h (unpredictable_action): New function prototype.
394 (Unpredictable): Define to call igen function unpredictable().
395 (NotWordValue): New macro to call igen function not_word_value().
396 (UndefinedResult): Remove.
397 * interp.c (undefined_result): Remove.
398 (unpredictable_action): New function.
399 * mips.igen (not_word_value, unpredictable): New functions.
400 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
401 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
402 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
403 NotWordValue() to check for unpredictable inputs, then
404 Unpredictable() to handle them.
406 2002-02-24 Chris Demetriou <cgd@broadcom.com>
408 * mips.igen: Fix formatting of calls to Unpredictable().
410 2002-04-20 Andrew Cagney <ac131313@redhat.com>
412 * interp.c (sim_open): Revert previous change.
414 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
416 * interp.c (sim_open): Disable chunk of code that wrote code in
417 vector table entries.
419 2002-03-19 Chris Demetriou <cgd@broadcom.com>
421 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
422 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
425 2002-03-19 Chris Demetriou <cgd@broadcom.com>
427 * cp1.c: Fix many formatting issues.
429 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
431 * cp1.c (fpu_format_name): New function to replace...
432 (DOFMT): This. Delete, and update all callers.
433 (fpu_rounding_mode_name): New function to replace...
434 (RMMODE): This. Delete, and update all callers.
436 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
438 * interp.c: Move FPU support routines from here to...
439 * cp1.c: Here. New file.
440 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
443 2002-03-12 Chris Demetriou <cgd@broadcom.com>
445 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
446 * mips.igen (mips32, mips64): New models, add to all instructions
447 and functions as appropriate.
448 (loadstore_ea, check_u64): New variant for model mips64.
449 (check_fmt_p): New variant for models mipsV and mips64, remove
450 mipsV model marking fro other variant.
453 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
454 for mips32 and mips64.
455 (DCLO, DCLZ): New instructions for mips64.
457 2002-03-07 Chris Demetriou <cgd@broadcom.com>
459 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
460 immediate or code as a hex value with the "%#lx" format.
461 (ANDI): Likewise, and fix printed instruction name.
463 2002-03-05 Chris Demetriou <cgd@broadcom.com>
465 * sim-main.h (UndefinedResult, Unpredictable): New macros
466 which currently do nothing.
468 2002-03-05 Chris Demetriou <cgd@broadcom.com>
470 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
471 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
472 (status_CU3): New definitions.
474 * sim-main.h (ExceptionCause): Add new values for MIPS32
475 and MIPS64: MDMX, MCheck, CacheErr. Update comments
476 for DebugBreakPoint and NMIReset to note their status in
478 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
479 (SignalExceptionCacheErr): New exception macros.
481 2002-03-05 Chris Demetriou <cgd@broadcom.com>
483 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
484 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
486 (SignalExceptionCoProcessorUnusable): Take as argument the
487 unusable coprocessor number.
489 2002-03-05 Chris Demetriou <cgd@broadcom.com>
491 * mips.igen: Fix formatting of all SignalException calls.
493 2002-03-05 Chris Demetriou <cgd@broadcom.com>
495 * sim-main.h (SIGNEXTEND): Remove.
497 2002-03-04 Chris Demetriou <cgd@broadcom.com>
499 * mips.igen: Remove gencode comment from top of file, fix
500 spelling in another comment.
502 2002-03-04 Chris Demetriou <cgd@broadcom.com>
504 * mips.igen (check_fmt, check_fmt_p): New functions to check
505 whether specific floating point formats are usable.
506 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
507 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
508 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
509 Use the new functions.
510 (do_c_cond_fmt): Remove format checks...
511 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
513 2002-03-03 Chris Demetriou <cgd@broadcom.com>
515 * mips.igen: Fix formatting of check_fpu calls.
517 2002-03-03 Chris Demetriou <cgd@broadcom.com>
519 * mips.igen (FLOOR.L.fmt): Store correct destination register.
521 2002-03-03 Chris Demetriou <cgd@broadcom.com>
523 * mips.igen: Remove whitespace at end of lines.
525 2002-03-02 Chris Demetriou <cgd@broadcom.com>
527 * mips.igen (loadstore_ea): New function to do effective
528 address calculations.
529 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
530 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
531 CACHE): Use loadstore_ea to do effective address computations.
533 2002-03-02 Chris Demetriou <cgd@broadcom.com>
535 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
536 * mips.igen (LL, CxC1, MxC1): Likewise.
538 2002-03-02 Chris Demetriou <cgd@broadcom.com>
540 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
541 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
542 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
543 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
544 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
545 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
546 Don't split opcode fields by hand, use the opcode field values
549 2002-03-01 Chris Demetriou <cgd@broadcom.com>
551 * mips.igen (do_divu): Fix spacing.
553 * mips.igen (do_dsllv): Move to be right before DSLLV,
554 to match the rest of the do_<shift> functions.
556 2002-03-01 Chris Demetriou <cgd@broadcom.com>
558 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
559 DSRL32, do_dsrlv): Trace inputs and results.
561 2002-03-01 Chris Demetriou <cgd@broadcom.com>
563 * mips.igen (CACHE): Provide instruction-printing string.
565 * interp.c (signal_exception): Comment tokens after #endif.
567 2002-02-28 Chris Demetriou <cgd@broadcom.com>
569 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
570 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
571 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
572 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
573 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
574 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
575 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
576 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
578 2002-02-28 Chris Demetriou <cgd@broadcom.com>
580 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
581 instruction-printing string.
582 (LWU): Use '64' as the filter flag.
584 2002-02-28 Chris Demetriou <cgd@broadcom.com>
586 * mips.igen (SDXC1): Fix instruction-printing string.
588 2002-02-28 Chris Demetriou <cgd@broadcom.com>
590 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
593 2002-02-27 Chris Demetriou <cgd@broadcom.com>
595 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
598 2002-02-27 Chris Demetriou <cgd@broadcom.com>
600 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
601 add a comma) so that it more closely match the MIPS ISA
602 documentation opcode partitioning.
603 (PREF): Put useful names on opcode fields, and include
604 instruction-printing string.
606 2002-02-27 Chris Demetriou <cgd@broadcom.com>
608 * mips.igen (check_u64): New function which in the future will
609 check whether 64-bit instructions are usable and signal an
610 exception if not. Currently a no-op.
611 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
612 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
613 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
614 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
616 * mips.igen (check_fpu): New function which in the future will
617 check whether FPU instructions are usable and signal an exception
618 if not. Currently a no-op.
619 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
620 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
621 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
622 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
623 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
624 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
625 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
626 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
628 2002-02-27 Chris Demetriou <cgd@broadcom.com>
630 * mips.igen (do_load_left, do_load_right): Move to be immediately
632 (do_store_left, do_store_right): Move to be immediately following
635 2002-02-27 Chris Demetriou <cgd@broadcom.com>
637 * mips.igen (mipsV): New model name. Also, add it to
638 all instructions and functions where it is appropriate.
640 2002-02-18 Chris Demetriou <cgd@broadcom.com>
642 * mips.igen: For all functions and instructions, list model
643 names that support that instruction one per line.
645 2002-02-11 Chris Demetriou <cgd@broadcom.com>
647 * mips.igen: Add some additional comments about supported
648 models, and about which instructions go where.
649 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
650 order as is used in the rest of the file.
652 2002-02-11 Chris Demetriou <cgd@broadcom.com>
654 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
655 indicating that ALU32_END or ALU64_END are there to check
657 (DADD): Likewise, but also remove previous comment about
660 2002-02-10 Chris Demetriou <cgd@broadcom.com>
662 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
663 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
664 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
665 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
666 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
667 fields (i.e., add and move commas) so that they more closely
668 match the MIPS ISA documentation opcode partitioning.
670 2002-02-10 Chris Demetriou <cgd@broadcom.com>
672 * mips.igen (ADDI): Print immediate value.
674 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
675 (SLL): Print "nop" specially, and don't run the code
676 that does the shift for the "nop" case.
678 2001-11-17 Fred Fish <fnf@redhat.com>
680 * sim-main.h (float_operation): Move enum declaration outside
681 of _sim_cpu struct declaration.
683 2001-04-12 Jim Blandy <jimb@redhat.com>
685 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
686 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
688 * sim-main.h (COCIDX): Remove definition; this isn't supported by
689 PENDING_FILL, and you can get the intended effect gracefully by
690 calling PENDING_SCHED directly.
692 2001-02-23 Ben Elliston <bje@redhat.com>
694 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
695 already defined elsewhere.
697 2001-02-19 Ben Elliston <bje@redhat.com>
699 * sim-main.h (sim_monitor): Return an int.
700 * interp.c (sim_monitor): Add return values.
701 (signal_exception): Handle error conditions from sim_monitor.
703 2001-02-08 Ben Elliston <bje@redhat.com>
705 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
706 (store_memory): Likewise, pass cia to sim_core_write*.
708 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
710 On advice from Chris G. Demetriou <cgd@sibyte.com>:
711 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
713 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
715 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
716 * Makefile.in: Don't delete *.igen when cleaning directory.
718 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
720 * m16.igen (break): Call SignalException not sim_engine_halt.
722 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
725 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
727 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
729 * mips.igen (MxC1, DMxC1): Fix printf formatting.
731 2000-05-24 Michael Hayes <mhayes@cygnus.com>
733 * mips.igen (do_dmultx): Fix typo.
735 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
737 * configure: Regenerated to track ../common/aclocal.m4 changes.
739 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
741 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
743 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
745 * sim-main.h (GPR_CLEAR): Define macro.
747 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
749 * interp.c (decode_coproc): Output long using %lx and not %s.
751 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
753 * interp.c (sim_open): Sort & extend dummy memory regions for
754 --board=jmr3904 for eCos.
756 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
758 * configure: Regenerated.
760 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
762 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
763 calls, conditional on the simulator being in verbose mode.
765 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
767 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
768 cache don't get ReservedInstruction traps.
770 1999-11-29 Mark Salter <msalter@cygnus.com>
772 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
773 to clear status bits in sdisr register. This is how the hardware works.
775 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
776 being used by cygmon.
778 1999-11-11 Andrew Haley <aph@cygnus.com>
780 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
783 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
785 * mips.igen (MULT): Correct previous mis-applied patch.
787 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
789 * mips.igen (delayslot32): Handle sequence like
790 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
791 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
792 (MULT): Actually pass the third register...
794 1999-09-03 Mark Salter <msalter@cygnus.com>
796 * interp.c (sim_open): Added more memory aliases for additional
797 hardware being touched by cygmon on jmr3904 board.
799 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
801 * configure: Regenerated to track ../common/aclocal.m4 changes.
803 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
805 * interp.c (sim_store_register): Handle case where client - GDB -
806 specifies that a 4 byte register is 8 bytes in size.
807 (sim_fetch_register): Ditto.
809 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
811 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
812 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
813 (idt_monitor_base): Base address for IDT monitor traps.
814 (pmon_monitor_base): Ditto for PMON.
815 (lsipmon_monitor_base): Ditto for LSI PMON.
816 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
817 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
818 (sim_firmware_command): New function.
819 (mips_option_handler): Call it for OPTION_FIRMWARE.
820 (sim_open): Allocate memory for idt_monitor region. If "--board"
821 option was given, add no monitor by default. Add BREAK hooks only if
822 monitors are also there.
824 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
826 * interp.c (sim_monitor): Flush output before reading input.
828 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
830 * tconfig.in (SIM_HANDLES_LMA): Always define.
832 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
834 From Mark Salter <msalter@cygnus.com>:
835 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
836 (sim_open): Add setup for BSP board.
838 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
840 * mips.igen (MULT, MULTU): Add syntax for two operand version.
841 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
842 them as unimplemented.
844 1999-05-08 Felix Lee <flee@cygnus.com>
846 * configure: Regenerated to track ../common/aclocal.m4 changes.
848 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
850 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
852 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
854 * configure.in: Any mips64vr5*-*-* target should have
855 -DTARGET_ENABLE_FR=1.
856 (default_endian): Any mips64vr*el-*-* target should default to
858 * configure: Re-generate.
860 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
862 * mips.igen (ldl): Extend from _16_, not 32.
864 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
866 * interp.c (sim_store_register): Force registers written to by GDB
867 into an un-interpreted state.
869 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
871 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
872 CPU, start periodic background I/O polls.
873 (tx3904sio_poll): New function: periodic I/O poller.
875 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
877 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
879 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
881 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
884 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
886 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
887 (load_word): Call SIM_CORE_SIGNAL hook on error.
888 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
889 starting. For exception dispatching, pass PC instead of NULL_CIA.
890 (decode_coproc): Use COP0_BADVADDR to store faulting address.
891 * sim-main.h (COP0_BADVADDR): Define.
892 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
893 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
894 (_sim_cpu): Add exc_* fields to store register value snapshots.
895 * mips.igen (*): Replace memory-related SignalException* calls
896 with references to SIM_CORE_SIGNAL hook.
898 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
900 * sim-main.c (*): Minor warning cleanups.
902 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
904 * m16.igen (DADDIU5): Correct type-o.
906 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
908 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
911 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
913 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
915 (interp.o): Add dependency on itable.h
916 (oengine.c, gencode): Delete remaining references.
917 (BUILT_SRC_FROM_GEN): Clean up.
919 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
922 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
923 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
925 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
926 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
927 Drop the "64" qualifier to get the HACK generator working.
928 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
929 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
930 qualifier to get the hack generator working.
931 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
933 (DSLLV): Use do_dsllv.
936 (DSRLV): Use do_dsrlv.
937 (BC1): Move *vr4100 to get the HACK generator working.
938 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
939 get the HACK generator working.
940 (MACC) Rename to get the HACK generator working.
941 (DMACC,MACCS,DMACCS): Add the 64.
943 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
945 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
946 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
948 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
950 * mips/interp.c (DEBUG): Cleanups.
952 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
954 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
955 (tx3904sio_tickle): fflush after a stdout character output.
957 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
959 * interp.c (sim_close): Uninstall modules.
961 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
963 * sim-main.h, interp.c (sim_monitor): Change to global
966 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
968 * configure.in (vr4100): Only include vr4100 instructions in
970 * configure: Re-generate.
971 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
973 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
975 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
976 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
979 * configure.in (sim_default_gen, sim_use_gen): Replace with
981 (--enable-sim-igen): Delete config option. Always using IGEN.
982 * configure: Re-generate.
984 * Makefile.in (gencode): Kill, kill, kill.
987 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
989 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
990 bit mips16 igen simulator.
991 * configure: Re-generate.
993 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
994 as part of vr4100 ISA.
995 * vr.igen: Mark all instructions as 64 bit only.
997 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
999 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1002 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1004 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1005 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1006 * configure: Re-generate.
1008 * m16.igen (BREAK): Define breakpoint instruction.
1009 (JALX32): Mark instruction as mips16 and not r3900.
1010 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1012 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1014 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1016 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1017 insn as a debug breakpoint.
1019 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1021 (PENDING_SCHED): Clean up trace statement.
1022 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1023 (PENDING_FILL): Delay write by only one cycle.
1024 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1026 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1028 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1030 (pending_tick): Move incrementing of index to FOR statement.
1031 (pending_tick): Only update PENDING_OUT after a write has occured.
1033 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1035 * configure: Re-generate.
1037 * interp.c (sim_engine_run OLD): Delete explicit call to
1038 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1040 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1042 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1043 interrupt level number to match changed SignalExceptionInterrupt
1046 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1048 * interp.c: #include "itable.h" if WITH_IGEN.
1049 (get_insn_name): New function.
1050 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1051 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1053 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1055 * configure: Rebuilt to inhale new common/aclocal.m4.
1057 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1059 * dv-tx3904sio.c: Include sim-assert.h.
1061 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1063 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1064 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1065 Reorganize target-specific sim-hardware checks.
1066 * configure: rebuilt.
1067 * interp.c (sim_open): For tx39 target boards, set
1068 OPERATING_ENVIRONMENT, add tx3904sio devices.
1069 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1070 ROM executables. Install dv-sockser into sim-modules list.
1072 * dv-tx3904irc.c: Compiler warning clean-up.
1073 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1074 frequent hw-trace messages.
1076 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1078 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1080 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1082 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1084 * vr.igen: New file.
1085 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1086 * mips.igen: Define vr4100 model. Include vr.igen.
1087 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1089 * mips.igen (check_mf_hilo): Correct check.
1091 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1093 * sim-main.h (interrupt_event): Add prototype.
1095 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1096 register_ptr, register_value.
1097 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1099 * sim-main.h (tracefh): Make extern.
1101 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1103 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1104 Reduce unnecessarily high timer event frequency.
1105 * dv-tx3904cpu.c: Ditto for interrupt event.
1107 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1109 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1111 (interrupt_event): Made non-static.
1113 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1114 interchange of configuration values for external vs. internal
1117 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1119 * mips.igen (BREAK): Moved code to here for
1120 simulator-reserved break instructions.
1121 * gencode.c (build_instruction): Ditto.
1122 * interp.c (signal_exception): Code moved from here. Non-
1123 reserved instructions now use exception vector, rather
1125 * sim-main.h: Moved magic constants to here.
1127 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1129 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1130 register upon non-zero interrupt event level, clear upon zero
1132 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1133 by passing zero event value.
1134 (*_io_{read,write}_buffer): Endianness fixes.
1135 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1136 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1138 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1139 serial I/O and timer module at base address 0xFFFF0000.
1141 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1143 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1146 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1148 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1150 * configure: Update.
1152 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1154 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1155 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1156 * configure.in: Include tx3904tmr in hw_device list.
1157 * configure: Rebuilt.
1158 * interp.c (sim_open): Instantiate three timer instances.
1159 Fix address typo of tx3904irc instance.
1161 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1163 * interp.c (signal_exception): SystemCall exception now uses
1164 the exception vector.
1166 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1168 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1171 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1173 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1175 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1177 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1179 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1180 sim-main.h. Declare a struct hw_descriptor instead of struct
1181 hw_device_descriptor.
1183 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1185 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1186 right bits and then re-align left hand bytes to correct byte
1187 lanes. Fix incorrect computation in do_store_left when loading
1188 bytes from second word.
1190 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1192 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1193 * interp.c (sim_open): Only create a device tree when HW is
1196 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1197 * interp.c (signal_exception): Ditto.
1199 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1201 * gencode.c: Mark BEGEZALL as LIKELY.
1203 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1205 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1206 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1208 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1210 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1211 modules. Recognize TX39 target with "mips*tx39" pattern.
1212 * configure: Rebuilt.
1213 * sim-main.h (*): Added many macros defining bits in
1214 TX39 control registers.
1215 (SignalInterrupt): Send actual PC instead of NULL.
1216 (SignalNMIReset): New exception type.
1217 * interp.c (board): New variable for future use to identify
1218 a particular board being simulated.
1219 (mips_option_handler,mips_options): Added "--board" option.
1220 (interrupt_event): Send actual PC.
1221 (sim_open): Make memory layout conditional on board setting.
1222 (signal_exception): Initial implementation of hardware interrupt
1223 handling. Accept another break instruction variant for simulator
1225 (decode_coproc): Implement RFE instruction for TX39.
1226 (mips.igen): Decode RFE instruction as such.
1227 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1228 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1229 bbegin to implement memory map.
1230 * dv-tx3904cpu.c: New file.
1231 * dv-tx3904irc.c: New file.
1233 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1235 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1237 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1239 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1240 with calls to check_div_hilo.
1242 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1244 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1245 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1246 Add special r3900 version of do_mult_hilo.
1247 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1248 with calls to check_mult_hilo.
1249 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1250 with calls to check_div_hilo.
1252 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1254 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1255 Document a replacement.
1257 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1259 * interp.c (sim_monitor): Make mon_printf work.
1261 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1263 * sim-main.h (INSN_NAME): New arg `cpu'.
1265 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1267 * configure: Regenerated to track ../common/aclocal.m4 changes.
1269 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1271 * configure: Regenerated to track ../common/aclocal.m4 changes.
1274 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1276 * acconfig.h: New file.
1277 * configure.in: Reverted change of Apr 24; use sinclude again.
1279 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1281 * configure: Regenerated to track ../common/aclocal.m4 changes.
1284 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1286 * configure.in: Don't call sinclude.
1288 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1290 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1292 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1294 * mips.igen (ERET): Implement.
1296 * interp.c (decode_coproc): Return sign-extended EPC.
1298 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1300 * interp.c (signal_exception): Do not ignore Trap.
1301 (signal_exception): On TRAP, restart at exception address.
1302 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1303 (signal_exception): Update.
1304 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1305 so that TRAP instructions are caught.
1307 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1309 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1310 contains HI/LO access history.
1311 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1312 (HIACCESS, LOACCESS): Delete, replace with
1313 (HIHISTORY, LOHISTORY): New macros.
1314 (CHECKHILO): Delete all, moved to mips.igen
1316 * gencode.c (build_instruction): Do not generate checks for
1317 correct HI/LO register usage.
1319 * interp.c (old_engine_run): Delete checks for correct HI/LO
1322 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1323 check_mf_cycles): New functions.
1324 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1325 do_divu, domultx, do_mult, do_multu): Use.
1327 * tx.igen ("madd", "maddu"): Use.
1329 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1331 * mips.igen (DSRAV): Use function do_dsrav.
1332 (SRAV): Use new function do_srav.
1334 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1335 (B): Sign extend 11 bit immediate.
1336 (EXT-B*): Shift 16 bit immediate left by 1.
1337 (ADDIU*): Don't sign extend immediate value.
1339 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1341 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1343 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1346 * mips.igen (delayslot32, nullify_next_insn): New functions.
1347 (m16.igen): Always include.
1348 (do_*): Add more tracing.
1350 * m16.igen (delayslot16): Add NIA argument, could be called by a
1351 32 bit MIPS16 instruction.
1353 * interp.c (ifetch16): Move function from here.
1354 * sim-main.c (ifetch16): To here.
1356 * sim-main.c (ifetch16, ifetch32): Update to match current
1357 implementations of LH, LW.
1358 (signal_exception): Don't print out incorrect hex value of illegal
1361 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1363 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1366 * m16.igen: Implement MIPS16 instructions.
1368 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1369 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1370 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1371 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1372 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1373 bodies of corresponding code from 32 bit insn to these. Also used
1374 by MIPS16 versions of functions.
1376 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1377 (IMEM16): Drop NR argument from macro.
1379 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1381 * Makefile.in (SIM_OBJS): Add sim-main.o.
1383 * sim-main.h (address_translation, load_memory, store_memory,
1384 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1386 (pr_addr, pr_uword64): Declare.
1387 (sim-main.c): Include when H_REVEALS_MODULE_P.
1389 * interp.c (address_translation, load_memory, store_memory,
1390 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1392 * sim-main.c: To here. Fix compilation problems.
1394 * configure.in: Enable inlining.
1395 * configure: Re-config.
1397 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1399 * configure: Regenerated to track ../common/aclocal.m4 changes.
1401 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1403 * mips.igen: Include tx.igen.
1404 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1405 * tx.igen: New file, contains MADD and MADDU.
1407 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1408 the hardwired constant `7'.
1409 (store_memory): Ditto.
1410 (LOADDRMASK): Move definition to sim-main.h.
1412 mips.igen (MTC0): Enable for r3900.
1415 mips.igen (do_load_byte): Delete.
1416 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1417 do_store_right): New functions.
1418 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1420 configure.in: Let the tx39 use igen again.
1423 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1425 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1426 not an address sized quantity. Return zero for cache sizes.
1428 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1430 * mips.igen (r3900): r3900 does not support 64 bit integer
1433 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1435 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1437 * configure : Rebuild.
1439 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1441 * configure: Regenerated to track ../common/aclocal.m4 changes.
1443 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1445 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1447 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1449 * configure: Regenerated to track ../common/aclocal.m4 changes.
1450 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1452 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1454 * configure: Regenerated to track ../common/aclocal.m4 changes.
1456 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1458 * interp.c (Max, Min): Comment out functions. Not yet used.
1460 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1462 * configure: Regenerated to track ../common/aclocal.m4 changes.
1464 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1466 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1467 configurable settings for stand-alone simulator.
1469 * configure.in: Added X11 search, just in case.
1471 * configure: Regenerated.
1473 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1475 * interp.c (sim_write, sim_read, load_memory, store_memory):
1476 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1478 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1480 * sim-main.h (GETFCC): Return an unsigned value.
1482 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1484 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1485 (DADD): Result destination is RD not RT.
1487 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1489 * sim-main.h (HIACCESS, LOACCESS): Always define.
1491 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1493 * interp.c (sim_info): Delete.
1495 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1497 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1498 (mips_option_handler): New argument `cpu'.
1499 (sim_open): Update call to sim_add_option_table.
1501 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1503 * mips.igen (CxC1): Add tracing.
1505 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1507 * sim-main.h (Max, Min): Declare.
1509 * interp.c (Max, Min): New functions.
1511 * mips.igen (BC1): Add tracing.
1513 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1515 * interp.c Added memory map for stack in vr4100
1517 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1519 * interp.c (load_memory): Add missing "break"'s.
1521 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1523 * interp.c (sim_store_register, sim_fetch_register): Pass in
1524 length parameter. Return -1.
1526 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1528 * interp.c: Added hardware init hook, fixed warnings.
1530 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1532 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1534 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1536 * interp.c (ifetch16): New function.
1538 * sim-main.h (IMEM32): Rename IMEM.
1539 (IMEM16_IMMED): Define.
1541 (DELAY_SLOT): Update.
1543 * m16run.c (sim_engine_run): New file.
1545 * m16.igen: All instructions except LB.
1546 (LB): Call do_load_byte.
1547 * mips.igen (do_load_byte): New function.
1548 (LB): Call do_load_byte.
1550 * mips.igen: Move spec for insn bit size and high bit from here.
1551 * Makefile.in (tmp-igen, tmp-m16): To here.
1553 * m16.dc: New file, decode mips16 instructions.
1555 * Makefile.in (SIM_NO_ALL): Define.
1556 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1558 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1560 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1561 point unit to 32 bit registers.
1562 * configure: Re-generate.
1564 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1566 * configure.in (sim_use_gen): Make IGEN the default simulator
1567 generator for generic 32 and 64 bit mips targets.
1568 * configure: Re-generate.
1570 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1572 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1575 * interp.c (sim_fetch_register, sim_store_register): Read/write
1576 FGR from correct location.
1577 (sim_open): Set size of FGR's according to
1578 WITH_TARGET_FLOATING_POINT_BITSIZE.
1580 * sim-main.h (FGR): Store floating point registers in a separate
1583 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1585 * configure: Regenerated to track ../common/aclocal.m4 changes.
1587 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1589 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1591 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1593 * interp.c (pending_tick): New function. Deliver pending writes.
1595 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1596 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1597 it can handle mixed sized quantites and single bits.
1599 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1601 * interp.c (oengine.h): Do not include when building with IGEN.
1602 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1603 (sim_info): Ditto for PROCESSOR_64BIT.
1604 (sim_monitor): Replace ut_reg with unsigned_word.
1605 (*): Ditto for t_reg.
1606 (LOADDRMASK): Define.
1607 (sim_open): Remove defunct check that host FP is IEEE compliant,
1608 using software to emulate floating point.
1609 (value_fpr, ...): Always compile, was conditional on HASFPU.
1611 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1613 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1616 * interp.c (SD, CPU): Define.
1617 (mips_option_handler): Set flags in each CPU.
1618 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1619 (sim_close): Do not clear STATE, deleted anyway.
1620 (sim_write, sim_read): Assume CPU zero's vm should be used for
1622 (sim_create_inferior): Set the PC for all processors.
1623 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1625 (mips16_entry): Pass correct nr of args to store_word, load_word.
1626 (ColdReset): Cold reset all cpu's.
1627 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1628 (sim_monitor, load_memory, store_memory, signal_exception): Use
1629 `CPU' instead of STATE_CPU.
1632 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1635 * sim-main.h (signal_exception): Add sim_cpu arg.
1636 (SignalException*): Pass both SD and CPU to signal_exception.
1637 * interp.c (signal_exception): Update.
1639 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1641 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1642 address_translation): Ditto
1643 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1645 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1647 * configure: Regenerated to track ../common/aclocal.m4 changes.
1649 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1651 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1653 * mips.igen (model): Map processor names onto BFD name.
1655 * sim-main.h (CPU_CIA): Delete.
1656 (SET_CIA, GET_CIA): Define
1658 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1660 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1663 * configure.in (default_endian): Configure a big-endian simulator
1665 * configure: Re-generate.
1667 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1669 * configure: Regenerated to track ../common/aclocal.m4 changes.
1671 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1673 * interp.c (sim_monitor): Handle Densan monitor outbyte
1674 and inbyte functions.
1676 1997-12-29 Felix Lee <flee@cygnus.com>
1678 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1680 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1682 * Makefile.in (tmp-igen): Arrange for $zero to always be
1683 reset to zero after every instruction.
1685 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1687 * configure: Regenerated to track ../common/aclocal.m4 changes.
1690 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1692 * mips.igen (MSUB): Fix to work like MADD.
1693 * gencode.c (MSUB): Similarly.
1695 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1697 * configure: Regenerated to track ../common/aclocal.m4 changes.
1699 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1701 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1703 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1705 * sim-main.h (sim-fpu.h): Include.
1707 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1708 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1709 using host independant sim_fpu module.
1711 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1713 * interp.c (signal_exception): Report internal errors with SIGABRT
1716 * sim-main.h (C0_CONFIG): New register.
1717 (signal.h): No longer include.
1719 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1721 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1723 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1725 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1727 * mips.igen: Tag vr5000 instructions.
1728 (ANDI): Was missing mipsIV model, fix assembler syntax.
1729 (do_c_cond_fmt): New function.
1730 (C.cond.fmt): Handle mips I-III which do not support CC field
1732 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1733 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1735 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1736 vr5000 which saves LO in a GPR separatly.
1738 * configure.in (enable-sim-igen): For vr5000, select vr5000
1739 specific instructions.
1740 * configure: Re-generate.
1742 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1744 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1746 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1747 fmt_uninterpreted_64 bit cases to switch. Convert to
1750 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1752 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1753 as specified in IV3.2 spec.
1754 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1756 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1758 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1759 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1760 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1761 PENDING_FILL versions of instructions. Simplify.
1763 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1765 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1767 (MTHI, MFHI): Disable code checking HI-LO.
1769 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1771 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1773 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1775 * gencode.c (build_mips16_operands): Replace IPC with cia.
1777 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1778 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1780 (UndefinedResult): Replace function with macro/function
1782 (sim_engine_run): Don't save PC in IPC.
1784 * sim-main.h (IPC): Delete.
1787 * interp.c (signal_exception, store_word, load_word,
1788 address_translation, load_memory, store_memory, cache_op,
1789 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1790 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1791 current instruction address - cia - argument.
1792 (sim_read, sim_write): Call address_translation directly.
1793 (sim_engine_run): Rename variable vaddr to cia.
1794 (signal_exception): Pass cia to sim_monitor
1796 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1797 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1798 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1800 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1801 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1804 * interp.c (signal_exception): Pass restart address to
1807 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1808 idecode.o): Add dependency.
1810 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1812 (DELAY_SLOT): Update NIA not PC with branch address.
1813 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1815 * mips.igen: Use CIA not PC in branch calculations.
1816 (illegal): Call SignalException.
1817 (BEQ, ADDIU): Fix assembler.
1819 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1821 * m16.igen (JALX): Was missing.
1823 * configure.in (enable-sim-igen): New configuration option.
1824 * configure: Re-generate.
1826 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1828 * interp.c (load_memory, store_memory): Delete parameter RAW.
1829 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1830 bypassing {load,store}_memory.
1832 * sim-main.h (ByteSwapMem): Delete definition.
1834 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1836 * interp.c (sim_do_command, sim_commands): Delete mips specific
1837 commands. Handled by module sim-options.
1839 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1840 (WITH_MODULO_MEMORY): Define.
1842 * interp.c (sim_info): Delete code printing memory size.
1844 * interp.c (mips_size): Nee sim_size, delete function.
1846 (monitor, monitor_base, monitor_size): Delete global variables.
1847 (sim_open, sim_close): Delete code creating monitor and other
1848 memory regions. Use sim-memopts module, via sim_do_commandf, to
1849 manage memory regions.
1850 (load_memory, store_memory): Use sim-core for memory model.
1852 * interp.c (address_translation): Delete all memory map code
1853 except line forcing 32 bit addresses.
1855 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1857 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1860 * interp.c (logfh, logfile): Delete globals.
1861 (sim_open, sim_close): Delete code opening & closing log file.
1862 (mips_option_handler): Delete -l and -n options.
1863 (OPTION mips_options): Ditto.
1865 * interp.c (OPTION mips_options): Rename option trace to dinero.
1866 (mips_option_handler): Update.
1868 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1870 * interp.c (fetch_str): New function.
1871 (sim_monitor): Rewrite using sim_read & sim_write.
1872 (sim_open): Check magic number.
1873 (sim_open): Write monitor vectors into memory using sim_write.
1874 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1875 (sim_read, sim_write): Simplify - transfer data one byte at a
1877 (load_memory, store_memory): Clarify meaning of parameter RAW.
1879 * sim-main.h (isHOST): Defete definition.
1880 (isTARGET): Mark as depreciated.
1881 (address_translation): Delete parameter HOST.
1883 * interp.c (address_translation): Delete parameter HOST.
1885 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1889 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1890 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1892 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1894 * mips.igen: Add model filter field to records.
1896 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1898 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1900 interp.c (sim_engine_run): Do not compile function sim_engine_run
1901 when WITH_IGEN == 1.
1903 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1904 target architecture.
1906 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1907 igen. Replace with configuration variables sim_igen_flags /
1910 * m16.igen: New file. Copy mips16 insns here.
1911 * mips.igen: From here.
1913 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1917 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1919 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1921 * gencode.c (build_instruction): Follow sim_write's lead in using
1922 BigEndianMem instead of !ByteSwapMem.
1924 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1926 * configure.in (sim_gen): Dependent on target, select type of
1927 generator. Always select old style generator.
1929 configure: Re-generate.
1931 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1933 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1934 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1935 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1936 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1937 SIM_@sim_gen@_*, set by autoconf.
1939 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1941 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1943 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1944 CURRENT_FLOATING_POINT instead.
1946 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1947 (address_translation): Raise exception InstructionFetch when
1948 translation fails and isINSTRUCTION.
1950 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1951 sim_engine_run): Change type of of vaddr and paddr to
1953 (address_translation, prefetch, load_memory, store_memory,
1954 cache_op): Change type of vAddr and pAddr to address_word.
1956 * gencode.c (build_instruction): Change type of vaddr and paddr to
1959 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1961 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1962 macro to obtain result of ALU op.
1964 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1966 * interp.c (sim_info): Call profile_print.
1968 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1970 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1972 * sim-main.h (WITH_PROFILE): Do not define, defined in
1973 common/sim-config.h. Use sim-profile module.
1974 (simPROFILE): Delete defintion.
1976 * interp.c (PROFILE): Delete definition.
1977 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1978 (sim_close): Delete code writing profile histogram.
1979 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1981 (sim_engine_run): Delete code profiling the PC.
1983 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1985 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1987 * interp.c (sim_monitor): Make register pointers of type
1990 * sim-main.h: Make registers of type unsigned_word not
1993 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1995 * interp.c (sync_operation): Rename from SyncOperation, make
1996 global, add SD argument.
1997 (prefetch): Rename from Prefetch, make global, add SD argument.
1998 (decode_coproc): Make global.
2000 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2002 * gencode.c (build_instruction): Generate DecodeCoproc not
2003 decode_coproc calls.
2005 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2006 (SizeFGR): Move to sim-main.h
2007 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2008 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2009 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2011 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2012 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2013 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2014 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2015 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2016 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2018 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2020 (sim-alu.h): Include.
2021 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2022 (sim_cia): Typedef to instruction_address.
2024 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2026 * Makefile.in (interp.o): Rename generated file engine.c to
2031 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2033 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2035 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2037 * gencode.c (build_instruction): For "FPSQRT", output correct
2038 number of arguments to Recip.
2040 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2042 * Makefile.in (interp.o): Depends on sim-main.h
2044 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2046 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2047 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2048 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2049 STATE, DSSTATE): Define
2050 (GPR, FGRIDX, ..): Define.
2052 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2053 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2054 (GPR, FGRIDX, ...): Delete macros.
2056 * interp.c: Update names to match defines from sim-main.h
2058 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2060 * interp.c (sim_monitor): Add SD argument.
2061 (sim_warning): Delete. Replace calls with calls to
2063 (sim_error): Delete. Replace calls with sim_io_error.
2064 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2065 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2066 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2068 (mips_size): Rename from sim_size. Add SD argument.
2070 * interp.c (simulator): Delete global variable.
2071 (callback): Delete global variable.
2072 (mips_option_handler, sim_open, sim_write, sim_read,
2073 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2074 sim_size,sim_monitor): Use sim_io_* not callback->*.
2075 (sim_open): ZALLOC simulator struct.
2076 (PROFILE): Do not define.
2078 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2080 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2081 support.h with corresponding code.
2083 * sim-main.h (word64, uword64), support.h: Move definition to
2085 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2088 * Makefile.in: Update dependencies
2089 * interp.c: Do not include.
2091 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2093 * interp.c (address_translation, load_memory, store_memory,
2094 cache_op): Rename to from AddressTranslation et.al., make global,
2097 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2100 * interp.c (SignalException): Rename to signal_exception, make
2103 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2105 * sim-main.h (SignalException, SignalExceptionInterrupt,
2106 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2107 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2108 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2111 * interp.c, support.h: Use.
2113 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2115 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2116 to value_fpr / store_fpr. Add SD argument.
2117 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2118 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2120 * sim-main.h (ValueFPR, StoreFPR): Define.
2122 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2124 * interp.c (sim_engine_run): Check consistency between configure
2125 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2128 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2129 (mips_fpu): Configure WITH_FLOATING_POINT.
2130 (mips_endian): Configure WITH_TARGET_ENDIAN.
2131 * configure: Update.
2133 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2135 * configure: Regenerated to track ../common/aclocal.m4 changes.
2137 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2139 * configure: Regenerated.
2141 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2143 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2145 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2147 * gencode.c (print_igen_insn_models): Assume certain architectures
2148 include all mips* instructions.
2149 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2152 * Makefile.in (tmp.igen): Add target. Generate igen input from
2155 * gencode.c (FEATURE_IGEN): Define.
2156 (main): Add --igen option. Generate output in igen format.
2157 (process_instructions): Format output according to igen option.
2158 (print_igen_insn_format): New function.
2159 (print_igen_insn_models): New function.
2160 (process_instructions): Only issue warnings and ignore
2161 instructions when no FEATURE_IGEN.
2163 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2165 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2168 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2170 * configure: Regenerated to track ../common/aclocal.m4 changes.
2172 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2174 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2175 SIM_RESERVED_BITS): Delete, moved to common.
2176 (SIM_EXTRA_CFLAGS): Update.
2178 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180 * configure.in: Configure non-strict memory alignment.
2181 * configure: Regenerated to track ../common/aclocal.m4 changes.
2183 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2185 * configure: Regenerated to track ../common/aclocal.m4 changes.
2187 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2189 * gencode.c (SDBBP,DERET): Added (3900) insns.
2190 (RFE): Turn on for 3900.
2191 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2192 (dsstate): Made global.
2193 (SUBTARGET_R3900): Added.
2194 (CANCELDELAYSLOT): New.
2195 (SignalException): Ignore SystemCall rather than ignore and
2196 terminate. Add DebugBreakPoint handling.
2197 (decode_coproc): New insns RFE, DERET; and new registers Debug
2198 and DEPC protected by SUBTARGET_R3900.
2199 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2201 * Makefile.in,configure.in: Add mips subtarget option.
2202 * configure: Update.
2204 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2206 * gencode.c: Add r3900 (tx39).
2209 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2211 * gencode.c (build_instruction): Don't need to subtract 4 for
2214 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2216 * interp.c: Correct some HASFPU problems.
2218 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2220 * configure: Regenerated to track ../common/aclocal.m4 changes.
2222 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2224 * interp.c (mips_options): Fix samples option short form, should
2227 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2229 * interp.c (sim_info): Enable info code. Was just returning.
2231 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2233 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2236 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2238 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2240 (build_instruction): Ditto for LL.
2242 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2244 * configure: Regenerated to track ../common/aclocal.m4 changes.
2246 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2248 * configure: Regenerated to track ../common/aclocal.m4 changes.
2251 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2253 * interp.c (sim_open): Add call to sim_analyze_program, update
2256 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2258 * interp.c (sim_kill): Delete.
2259 (sim_create_inferior): Add ABFD argument. Set PC from same.
2260 (sim_load): Move code initializing trap handlers from here.
2261 (sim_open): To here.
2262 (sim_load): Delete, use sim-hload.c.
2264 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2266 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2268 * configure: Regenerated to track ../common/aclocal.m4 changes.
2271 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2273 * interp.c (sim_open): Add ABFD argument.
2274 (sim_load): Move call to sim_config from here.
2275 (sim_open): To here. Check return status.
2277 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2279 * gencode.c (build_instruction): Two arg MADD should
2280 not assign result to $0.
2282 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2284 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2285 * sim/mips/configure.in: Regenerate.
2287 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2289 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2290 signed8, unsigned8 et.al. types.
2292 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2293 hosts when selecting subreg.
2295 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2297 * interp.c (sim_engine_run): Reset the ZERO register to zero
2298 regardless of FEATURE_WARN_ZERO.
2299 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2301 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2303 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2304 (SignalException): For BreakPoints ignore any mode bits and just
2306 (SignalException): Always set the CAUSE register.
2308 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2310 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2311 exception has been taken.
2313 * interp.c: Implement the ERET and mt/f sr instructions.
2315 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2317 * interp.c (SignalException): Don't bother restarting an
2320 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2322 * interp.c (SignalException): Really take an interrupt.
2323 (interrupt_event): Only deliver interrupts when enabled.
2325 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2327 * interp.c (sim_info): Only print info when verbose.
2328 (sim_info) Use sim_io_printf for output.
2330 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2332 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2335 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2337 * interp.c (sim_do_command): Check for common commands if a
2338 simulator specific command fails.
2340 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2342 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2343 and simBE when DEBUG is defined.
2345 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2347 * interp.c (interrupt_event): New function. Pass exception event
2348 onto exception handler.
2350 * configure.in: Check for stdlib.h.
2351 * configure: Regenerate.
2353 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2354 variable declaration.
2355 (build_instruction): Initialize memval1.
2356 (build_instruction): Add UNUSED attribute to byte, bigend,
2358 (build_operands): Ditto.
2360 * interp.c: Fix GCC warnings.
2361 (sim_get_quit_code): Delete.
2363 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2364 * Makefile.in: Ditto.
2365 * configure: Re-generate.
2367 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2369 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2371 * interp.c (mips_option_handler): New function parse argumes using
2373 (myname): Replace with STATE_MY_NAME.
2374 (sim_open): Delete check for host endianness - performed by
2376 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2377 (sim_open): Move much of the initialization from here.
2378 (sim_load): To here. After the image has been loaded and
2380 (sim_open): Move ColdReset from here.
2381 (sim_create_inferior): To here.
2382 (sim_open): Make FP check less dependant on host endianness.
2384 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2386 * interp.c (sim_set_callbacks): Delete.
2388 * interp.c (membank, membank_base, membank_size): Replace with
2389 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2390 (sim_open): Remove call to callback->init. gdb/run do this.
2394 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2396 * interp.c (big_endian_p): Delete, replaced by
2397 current_target_byte_order.
2399 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2401 * interp.c (host_read_long, host_read_word, host_swap_word,
2402 host_swap_long): Delete. Using common sim-endian.
2403 (sim_fetch_register, sim_store_register): Use H2T.
2404 (pipeline_ticks): Delete. Handled by sim-events.
2406 (sim_engine_run): Update.
2408 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2410 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2412 (SignalException): To here. Signal using sim_engine_halt.
2413 (sim_stop_reason): Delete, moved to common.
2415 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2417 * interp.c (sim_open): Add callback argument.
2418 (sim_set_callbacks): Delete SIM_DESC argument.
2421 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2423 * Makefile.in (SIM_OBJS): Add common modules.
2425 * interp.c (sim_set_callbacks): Also set SD callback.
2426 (set_endianness, xfer_*, swap_*): Delete.
2427 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2428 Change to functions using sim-endian macros.
2429 (control_c, sim_stop): Delete, use common version.
2430 (simulate): Convert into.
2431 (sim_engine_run): This function.
2432 (sim_resume): Delete.
2434 * interp.c (simulation): New variable - the simulator object.
2435 (sim_kind): Delete global - merged into simulation.
2436 (sim_load): Cleanup. Move PC assignment from here.
2437 (sim_create_inferior): To here.
2439 * sim-main.h: New file.
2440 * interp.c (sim-main.h): Include.
2442 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2444 * configure: Regenerated to track ../common/aclocal.m4 changes.
2446 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2448 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2450 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2452 * gencode.c (build_instruction): DIV instructions: check
2453 for division by zero and integer overflow before using
2454 host's division operation.
2456 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2458 * Makefile.in (SIM_OBJS): Add sim-load.o.
2459 * interp.c: #include bfd.h.
2460 (target_byte_order): Delete.
2461 (sim_kind, myname, big_endian_p): New static locals.
2462 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2463 after argument parsing. Recognize -E arg, set endianness accordingly.
2464 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2465 load file into simulator. Set PC from bfd.
2466 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2467 (set_endianness): Use big_endian_p instead of target_byte_order.
2469 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2471 * interp.c (sim_size): Delete prototype - conflicts with
2472 definition in remote-sim.h. Correct definition.
2474 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2476 * configure: Regenerated to track ../common/aclocal.m4 changes.
2479 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2481 * interp.c (sim_open): New arg `kind'.
2483 * configure: Regenerated to track ../common/aclocal.m4 changes.
2485 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2487 * configure: Regenerated to track ../common/aclocal.m4 changes.
2489 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2491 * interp.c (sim_open): Set optind to 0 before calling getopt.
2493 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2495 * configure: Regenerated to track ../common/aclocal.m4 changes.
2497 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2499 * interp.c : Replace uses of pr_addr with pr_uword64
2500 where the bit length is always 64 independent of SIM_ADDR.
2501 (pr_uword64) : added.
2503 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2505 * configure: Re-generate.
2507 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2509 * configure: Regenerate to track ../common/aclocal.m4 changes.
2511 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2513 * interp.c (sim_open): New SIM_DESC result. Argument is now
2515 (other sim_*): New SIM_DESC argument.
2517 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2519 * interp.c: Fix printing of addresses for non-64-bit targets.
2520 (pr_addr): Add function to print address based on size.
2522 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2524 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2526 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2528 * gencode.c (build_mips16_operands): Correct computation of base
2529 address for extended PC relative instruction.
2531 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2533 * interp.c (mips16_entry): Add support for floating point cases.
2534 (SignalException): Pass floating point cases to mips16_entry.
2535 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2537 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2539 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2540 and then set the state to fmt_uninterpreted.
2541 (COP_SW): Temporarily set the state to fmt_word while calling
2544 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2546 * gencode.c (build_instruction): The high order may be set in the
2547 comparison flags at any ISA level, not just ISA 4.
2549 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2551 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2552 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2553 * configure.in: sinclude ../common/aclocal.m4.
2554 * configure: Regenerated.
2556 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2558 * configure: Rebuild after change to aclocal.m4.
2560 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2562 * configure configure.in Makefile.in: Update to new configure
2563 scheme which is more compatible with WinGDB builds.
2564 * configure.in: Improve comment on how to run autoconf.
2565 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2566 * Makefile.in: Use autoconf substitution to install common
2569 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2571 * gencode.c (build_instruction): Use BigEndianCPU instead of
2574 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2576 * interp.c (sim_monitor): Make output to stdout visible in
2577 wingdb's I/O log window.
2579 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2581 * support.h: Undo previous change to SIGTRAP
2584 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2586 * interp.c (store_word, load_word): New static functions.
2587 (mips16_entry): New static function.
2588 (SignalException): Look for mips16 entry and exit instructions.
2589 (simulate): Use the correct index when setting fpr_state after
2590 doing a pending move.
2592 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2594 * interp.c: Fix byte-swapping code throughout to work on
2595 both little- and big-endian hosts.
2597 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2599 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2600 with gdb/config/i386/xm-windows.h.
2602 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2604 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2605 that messes up arithmetic shifts.
2607 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2609 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2610 SIGTRAP and SIGQUIT for _WIN32.
2612 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2614 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2615 force a 64 bit multiplication.
2616 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2617 destination register is 0, since that is the default mips16 nop
2620 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2622 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2623 (build_endian_shift): Don't check proc64.
2624 (build_instruction): Always set memval to uword64. Cast op2 to
2625 uword64 when shifting it left in memory instructions. Always use
2626 the same code for stores--don't special case proc64.
2628 * gencode.c (build_mips16_operands): Fix base PC value for PC
2630 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2632 * interp.c (simJALDELAYSLOT): Define.
2633 (JALDELAYSLOT): Define.
2634 (INDELAYSLOT, INJALDELAYSLOT): Define.
2635 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2637 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2639 * interp.c (sim_open): add flush_cache as a PMON routine
2640 (sim_monitor): handle flush_cache by ignoring it
2642 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2644 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2646 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2647 (BigEndianMem): Rename to ByteSwapMem and change sense.
2648 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2649 BigEndianMem references to !ByteSwapMem.
2650 (set_endianness): New function, with prototype.
2651 (sim_open): Call set_endianness.
2652 (sim_info): Use simBE instead of BigEndianMem.
2653 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2654 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2655 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2656 ifdefs, keeping the prototype declaration.
2657 (swap_word): Rewrite correctly.
2658 (ColdReset): Delete references to CONFIG. Delete endianness related
2659 code; moved to set_endianness.
2661 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2663 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2664 * interp.c (CHECKHILO): Define away.
2665 (simSIGINT): New macro.
2666 (membank_size): Increase from 1MB to 2MB.
2667 (control_c): New function.
2668 (sim_resume): Rename parameter signal to signal_number. Add local
2669 variable prev. Call signal before and after simulate.
2670 (sim_stop_reason): Add simSIGINT support.
2671 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2673 (sim_warning): Delete call to SignalException. Do call printf_filtered
2675 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2676 a call to sim_warning.
2678 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2680 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2681 16 bit instructions.
2683 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2685 Add support for mips16 (16 bit MIPS implementation):
2686 * gencode.c (inst_type): Add mips16 instruction encoding types.
2687 (GETDATASIZEINSN): Define.
2688 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2689 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2691 (MIPS16_DECODE): New table, for mips16 instructions.
2692 (bitmap_val): New static function.
2693 (struct mips16_op): Define.
2694 (mips16_op_table): New table, for mips16 operands.
2695 (build_mips16_operands): New static function.
2696 (process_instructions): If PC is odd, decode a mips16
2697 instruction. Break out instruction handling into new
2698 build_instruction function.
2699 (build_instruction): New static function, broken out of
2700 process_instructions. Check modifiers rather than flags for SHIFT
2701 bit count and m[ft]{hi,lo} direction.
2702 (usage): Pass program name to fprintf.
2703 (main): Remove unused variable this_option_optind. Change
2704 ``*loptarg++'' to ``loptarg++''.
2705 (my_strtoul): Parenthesize && within ||.
2706 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2707 (simulate): If PC is odd, fetch a 16 bit instruction, and
2708 increment PC by 2 rather than 4.
2709 * configure.in: Add case for mips16*-*-*.
2710 * configure: Rebuild.
2712 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2714 * interp.c: Allow -t to enable tracing in standalone simulator.
2715 Fix garbage output in trace file and error messages.
2717 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2719 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2720 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2721 * configure.in: Simplify using macros in ../common/aclocal.m4.
2722 * configure: Regenerated.
2723 * tconfig.in: New file.
2725 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2727 * interp.c: Fix bugs in 64-bit port.
2728 Use ansi function declarations for msvc compiler.
2729 Initialize and test file pointer in trace code.
2730 Prevent duplicate definition of LAST_EMED_REGNUM.
2732 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2734 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2736 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2738 * interp.c (SignalException): Check for explicit terminating
2740 * gencode.c: Pass instruction value through SignalException()
2741 calls for Trap, Breakpoint and Syscall.
2743 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2745 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2746 only used on those hosts that provide it.
2747 * configure.in: Add sqrt() to list of functions to be checked for.
2748 * config.in: Re-generated.
2749 * configure: Re-generated.
2751 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2753 * gencode.c (process_instructions): Call build_endian_shift when
2754 expanding STORE RIGHT, to fix swr.
2755 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2756 clear the high bits.
2757 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2758 Fix float to int conversions to produce signed values.
2760 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2762 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2763 (process_instructions): Correct handling of nor instruction.
2764 Correct shift count for 32 bit shift instructions. Correct sign
2765 extension for arithmetic shifts to not shift the number of bits in
2766 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2767 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2769 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2770 It's OK to have a mult follow a mult. What's not OK is to have a
2771 mult follow an mfhi.
2772 (Convert): Comment out incorrect rounding code.
2774 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2776 * interp.c (sim_monitor): Improved monitor printf
2777 simulation. Tidied up simulator warnings, and added "--log" option
2778 for directing warning message output.
2779 * gencode.c: Use sim_warning() rather than WARNING macro.
2781 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2783 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2784 getopt1.o, rather than on gencode.c. Link objects together.
2785 Don't link against -liberty.
2786 (gencode.o, getopt.o, getopt1.o): New targets.
2787 * gencode.c: Include <ctype.h> and "ansidecl.h".
2788 (AND): Undefine after including "ansidecl.h".
2789 (ULONG_MAX): Define if not defined.
2790 (OP_*): Don't define macros; now defined in opcode/mips.h.
2791 (main): Call my_strtoul rather than strtoul.
2792 (my_strtoul): New static function.
2794 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2796 * gencode.c (process_instructions): Generate word64 and uword64
2797 instead of `long long' and `unsigned long long' data types.
2798 * interp.c: #include sysdep.h to get signals, and define default
2800 * (Convert): Work around for Visual-C++ compiler bug with type
2802 * support.h: Make things compile under Visual-C++ by using
2803 __int64 instead of `long long'. Change many refs to long long
2804 into word64/uword64 typedefs.
2806 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2808 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2809 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2811 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2812 (AC_PROG_INSTALL): Added.
2813 (AC_PROG_CC): Moved to before configure.host call.
2814 * configure: Rebuilt.
2816 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2818 * configure.in: Define @SIMCONF@ depending on mips target.
2819 * configure: Rebuild.
2820 * Makefile.in (run): Add @SIMCONF@ to control simulator
2822 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2823 * interp.c: Remove some debugging, provide more detailed error
2824 messages, update memory accesses to use LOADDRMASK.
2826 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2828 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2829 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2831 * configure: Rebuild.
2832 * config.in: New file, generated by autoheader.
2833 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2834 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2835 HAVE_ANINT and HAVE_AINT, as appropriate.
2836 * Makefile.in (run): Use @LIBS@ rather than -lm.
2837 (interp.o): Depend upon config.h.
2838 (Makefile): Just rebuild Makefile.
2839 (clean): Remove stamp-h.
2840 (mostlyclean): Make the same as clean, not as distclean.
2841 (config.h, stamp-h): New targets.
2843 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2845 * interp.c (ColdReset): Fix boolean test. Make all simulator
2848 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2850 * interp.c (xfer_direct_word, xfer_direct_long,
2851 swap_direct_word, swap_direct_long, xfer_big_word,
2852 xfer_big_long, xfer_little_word, xfer_little_long,
2853 swap_word,swap_long): Added.
2854 * interp.c (ColdReset): Provide function indirection to
2855 host<->simulated_target transfer routines.
2856 * interp.c (sim_store_register, sim_fetch_register): Updated to
2857 make use of indirected transfer routines.
2859 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2861 * gencode.c (process_instructions): Ensure FP ABS instruction
2863 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2864 system call support.
2866 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2868 * interp.c (sim_do_command): Complain if callback structure not
2871 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2873 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2874 support for Sun hosts.
2875 * Makefile.in (gencode): Ensure the host compiler and libraries
2876 used for cross-hosted build.
2878 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2880 * interp.c, gencode.c: Some more (TODO) tidying.
2882 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2884 * gencode.c, interp.c: Replaced explicit long long references with
2885 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2886 * support.h (SET64LO, SET64HI): Macros added.
2888 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2890 * configure: Regenerate with autoconf 2.7.
2892 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2894 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2895 * support.h: Remove superfluous "1" from #if.
2896 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2898 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2900 * interp.c (StoreFPR): Control UndefinedResult() call on
2901 WARN_RESULT manifest.
2903 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2905 * gencode.c: Tidied instruction decoding, and added FP instruction
2908 * interp.c: Added dineroIII, and BSD profiling support. Also
2909 run-time FP handling.
2911 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2913 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2914 gencode.c, interp.c, support.h: created.