1 /* Simulator for Motorola's MCore processor
2 Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include <sys/times.h>
25 #include <sys/param.h>
28 #include "gdb/callback.h"
29 #include "libiberty.h"
30 #include "gdb/remote-sim.h"
34 #include "sim-syscall.h"
35 #include "sim-options.h"
37 #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
41 mcore_extract_unsigned_integer (unsigned char *addr, int len)
45 unsigned char * startaddr = (unsigned char *)addr;
46 unsigned char * endaddr = startaddr + len;
48 if (len > (int) sizeof (unsigned long))
49 printf ("That operation is not available on integers of more than %zu bytes.",
50 sizeof (unsigned long));
52 /* Start at the most significant end of the integer, and work towards
53 the least significant. */
56 if (! target_big_endian)
58 for (p = endaddr; p > startaddr;)
59 retval = (retval << 8) | * -- p;
63 for (p = startaddr; p < endaddr;)
64 retval = (retval << 8) | * p ++;
71 mcore_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
74 unsigned char * startaddr = (unsigned char *)addr;
75 unsigned char * endaddr = startaddr + len;
77 if (! target_big_endian)
79 for (p = startaddr; p < endaddr;)
87 for (p = endaddr; p > startaddr;)
96 This state is maintained in host byte order. The
97 fetch/store register functions must translate between host
98 byte order and the target processor byte order.
99 Keeping this data in target byte order simplifies the register
100 read/write functions. Keeping this data in native order improves
101 the performance of the simulator. Simulation speed is deemed more
103 /* TODO: Should be moved to sim-main.h:sim_cpu. */
105 /* The ordering of the mcore_regset structure is matched in the
106 gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
109 word gregs [16]; /* primary registers */
110 word alt_gregs [16]; /* alt register file */
111 word cregs [32]; /* control registers */
121 struct mcore_regset asregs;
122 word asints [1]; /* but accessed larger... */
125 #define LAST_VALID_CREG 32 /* only 0..12 implemented */
126 #define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
128 static int memcycles = 1;
130 #define gr asregs.active_gregs
131 #define cr asregs.cregs
132 #define sr asregs.cregs[0]
133 #define vbr asregs.cregs[1]
134 #define esr asregs.cregs[2]
135 #define fsr asregs.cregs[3]
136 #define epc asregs.cregs[4]
137 #define fpc asregs.cregs[5]
138 #define ss0 asregs.cregs[6]
139 #define ss1 asregs.cregs[7]
140 #define ss2 asregs.cregs[8]
141 #define ss3 asregs.cregs[9]
142 #define ss4 asregs.cregs[10]
143 #define gcr asregs.cregs[11]
144 #define gsr asregs.cregs[12]
146 /* maniuplate the carry bit */
147 #define C_ON() (cpu.sr & 1)
148 #define C_VALUE() (cpu.sr & 1)
149 #define C_OFF() ((cpu.sr & 1) == 0)
150 #define SET_C() {cpu.sr |= 1;}
151 #define CLR_C() {cpu.sr &= 0xfffffffe;}
152 #define NEW_C(v) {CLR_C(); cpu.sr |= ((v) & 1);}
154 #define SR_AF() ((cpu.sr >> 1) & 1)
156 #define TRAPCODE 1 /* r1 holds which function we want */
157 #define PARM1 2 /* first parameter */
161 #define RET1 2 /* register for return values. */
163 /* Default to a 8 Mbyte (== 2^23) memory space. */
164 #define DEFAULT_MEMORY_SIZE 0x800000
167 set_initial_gprs (SIM_CPU *scpu)
172 /* Set up machine just out of reset. */
173 CPU_PC_SET (scpu, 0);
176 /* Clean out the GPRs and alternate GPRs. */
177 for (i = 0; i < 16; i++)
179 cpu.asregs.gregs[i] = 0;
180 cpu.asregs.alt_gregs[i] = 0;
183 /* Make our register set point to the right place. */
185 cpu.asregs.active_gregs = &cpu.asregs.alt_gregs[0];
187 cpu.asregs.active_gregs = &cpu.asregs.gregs[0];
189 /* ABI specifies initial values for these registers. */
190 cpu.gr[0] = DEFAULT_MEMORY_SIZE - 4;
192 /* dac fix, the stack address must be 8-byte aligned! */
193 cpu.gr[0] = cpu.gr[0] - cpu.gr[0] % 8;
197 cpu.gr[PARM4] = cpu.gr[0];
200 /* Simulate a monitor trap. */
203 handle_trap1 (SIM_DESC sd)
205 /* XXX: We don't pass back the actual errno value. */
206 cpu.gr[RET1] = sim_syscall (STATE_CPU (sd, 0), cpu.gr[TRAPCODE],
207 cpu.gr[PARM1], cpu.gr[PARM2], cpu.gr[PARM3],
212 process_stub (SIM_DESC sd, int what)
214 /* These values should match those in libgloss/mcore/syscalls.s. */
221 case 10: /* _unlink */
222 case 19: /* _lseek */
223 case 43: /* _times */
224 cpu.gr [TRAPCODE] = what;
229 if (STATE_VERBOSE_P (sd))
230 fprintf (stderr, "Unhandled stub opcode: %d\n", what);
236 util (SIM_DESC sd, SIM_CPU *scpu, unsigned what)
241 sim_engine_halt (sd, scpu, NULL, scpu->pc, sim_exited, cpu.gr[PARM1]);
245 if (STATE_VERBOSE_P (sd))
246 fprintf (stderr, "WARNING: printf unimplemented\n");
250 if (STATE_VERBOSE_P (sd))
251 fprintf (stderr, "WARNING: scanf unimplemented\n");
255 cpu.gr[RET1] = cpu.asregs.insts;
259 process_stub (sd, cpu.gr[1]);
263 if (STATE_VERBOSE_P (sd))
264 fprintf (stderr, "Unhandled util code: %x\n", what);
269 /* For figuring out whether we carried; addc/subc use this. */
271 iu_carry (unsigned long a, unsigned long b, int cin)
275 x = (a & 0xffff) + (b & 0xffff) + cin;
276 x = (x >> 16) + (a >> 16) + (b >> 16);
282 /* TODO: Convert to common watchpoints. */
283 #undef WATCHFUNCTIONS
284 #ifdef WATCHFUNCTIONS
301 #define RD (inst & 0xF)
302 #define RS ((inst >> 4) & 0xF)
303 #define RX ((inst >> 8) & 0xF)
304 #define IMM5 ((inst >> 4) & 0x1F)
305 #define IMM4 ((inst) & 0xF)
307 #define rbat(X) sim_core_read_1 (scpu, 0, read_map, X)
308 #define rhat(X) sim_core_read_2 (scpu, 0, read_map, X)
309 #define rlat(X) sim_core_read_4 (scpu, 0, read_map, X)
310 #define wbat(X, D) sim_core_write_1 (scpu, 0, write_map, X, D)
311 #define what(X, D) sim_core_write_2 (scpu, 0, write_map, X, D)
312 #define wlat(X, D) sim_core_write_4 (scpu, 0, write_map, X, D)
314 static int tracing = 0;
317 sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGILL)
320 step_once (SIM_DESC sd, SIM_CPU *scpu)
331 #ifdef WATCHFUNCTIONS
335 pc = CPU_PC_GET (scpu);
337 /* Fetch the initial instructions that we'll decode. */
338 ibuf = rlat (pc & 0xFFFFFFFC);
345 /* make our register set point to the right place */
347 cpu.asregs.active_gregs = & cpu.asregs.alt_gregs[0];
349 cpu.asregs.active_gregs = & cpu.asregs.gregs[0];
351 #ifdef WATCHFUNCTIONS
352 /* make a hash to speed exec loop, hope it's nonzero */
355 for (w = 1; w <= ENDWL; w++)
356 WLhash = WLhash & WL[w];
359 /* TODO: Unindent this block. */
367 if (! target_big_endian)
370 inst = ibuf & 0xFFFF;
375 if (! target_big_endian)
376 inst = ibuf & 0xFFFF;
381 #ifdef WATCHFUNCTIONS
382 /* now scan list of watch addresses, if match, count it and
383 note return address and count cycles until pc=return address */
385 if ((WLincyc == 1) && (pc == WLendpc))
387 cycs = (cpu.asregs.cycles + (insts + bonus_cycles +
388 (memops * memcycles)) - WLbcyc);
390 if (WLcnts[WLW] == 1)
397 if (cycs > WLmax[WLW])
402 if (cycs < WLmin[WLW])
412 /* Optimize with a hash to speed loop. */
415 if ((WLhash == 0) || ((WLhash & pc) != 0))
417 for (w=1; w <= ENDWL; w++)
422 WLbcyc = cpu.asregs.cycles + insts
423 + bonus_cycles + (memops * memcycles);
424 WLendpc = cpu.gr[15];
435 fprintf (stderr, "%.4lx: inst = %.4x ", pc, inst);
451 sim_engine_halt (sd, scpu, NULL, pc - 2,
452 sim_stopped, SIM_SIGTRAP);
464 cpu.asregs.active_gregs = & cpu.asregs.alt_gregs[0];
466 cpu.asregs.active_gregs = & cpu.asregs.gregs[0];
475 cpu.asregs.active_gregs = &cpu.asregs.alt_gregs[0];
477 cpu.asregs.active_gregs = &cpu.asregs.gregs[0];
481 if (STATE_VERBOSE_P (sd))
482 fprintf (stderr, "WARNING: stop unimplemented\n");
486 if (STATE_VERBOSE_P (sd))
487 fprintf (stderr, "WARNING: wait unimplemented\n");
491 if (STATE_VERBOSE_P (sd))
492 fprintf (stderr, "WARNING: doze unimplemented\n");
496 ILLEGAL (); /* illegal */
499 case 0x8: /* trap 0 */
500 case 0xA: /* trap 2 */
501 case 0xB: /* trap 3 */
502 sim_engine_halt (sd, scpu, NULL, pc,
503 sim_stopped, SIM_SIGTRAP);
506 case 0xC: /* trap 4 */
507 case 0xD: /* trap 5 */
508 case 0xE: /* trap 6 */
509 ILLEGAL (); /* illegal */
512 case 0xF: /* trap 7 */
513 sim_engine_halt (sd, scpu, NULL, pc, /* integer div-by-0 */
514 sim_stopped, SIM_SIGTRAP);
517 case 0x9: /* trap 1 */
524 ILLEGAL (); /* illegal */
528 cpu.gr[RD] = C_VALUE();
531 cpu.gr[RD] = C_OFF();
535 word addr = cpu.gr[RD];
536 int regno = 4; /* always r4-r7 */
542 cpu.gr[regno] = rlat(addr);
546 while ((regno&0x3) != 0);
551 word addr = cpu.gr[RD];
552 int regno = 4; /* always r4-r7 */
558 wlat(addr, cpu.gr[regno]);
562 while ((regno & 0x3) != 0);
567 word addr = cpu.gr[0];
570 /* bonus cycle is really only needed if
571 the next insn shifts the last reg loaded.
578 cpu.gr[regno] = rlat(addr);
586 word addr = cpu.gr[0];
589 /* this should be removed! */
590 /* bonus_cycles ++; */
592 memops += 16 - regno;
595 wlat(addr, cpu.gr[regno]);
603 cpu.gr[RD] -= C_VALUE();
606 cpu.gr[RD] -= C_OFF();
609 cpu.gr[RD] += C_VALUE();
612 cpu.gr[RD] += C_OFF();
616 if (tracing && RD == 15)
617 fprintf (stderr, "Func return, r2 = %lxx, r3 = %lx\n",
618 cpu.gr[2], cpu.gr[3]);
632 for (i = 0; !(tmp & 0x80000000) && i < 32; i++)
641 tmp = ((tmp & 0xaaaaaaaa) >> 1) | ((tmp & 0x55555555) << 1);
642 tmp = ((tmp & 0xcccccccc) >> 2) | ((tmp & 0x33333333) << 2);
643 tmp = ((tmp & 0xf0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f) << 4);
644 tmp = ((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8);
645 cpu.gr[RD] = ((tmp & 0xffff0000) >> 16) | ((tmp & 0x0000ffff) << 16);
653 case 0x0: /* xtrb3 */
654 cpu.gr[1] = (cpu.gr[RD]) & 0xFF;
655 NEW_C (cpu.gr[RD] != 0);
657 case 0x1: /* xtrb2 */
658 cpu.gr[1] = (cpu.gr[RD]>>8) & 0xFF;
659 NEW_C (cpu.gr[RD] != 0);
661 case 0x2: /* xtrb1 */
662 cpu.gr[1] = (cpu.gr[RD]>>16) & 0xFF;
663 NEW_C (cpu.gr[RD] != 0);
665 case 0x3: /* xtrb0 */
666 cpu.gr[1] = (cpu.gr[RD]>>24) & 0xFF;
667 NEW_C (cpu.gr[RD] != 0);
669 case 0x4: /* zextb */
670 cpu.gr[RD] &= 0x000000FF;
672 case 0x5: /* sextb */
681 case 0x6: /* zexth */
682 cpu.gr[RD] &= 0x0000FFFF;
684 case 0x7: /* sexth */
693 case 0x8: /* declt */
695 NEW_C ((long)cpu.gr[RD] < 0);
697 case 0x9: /* tstnbz */
699 word tmp = cpu.gr[RD];
700 NEW_C ((tmp & 0xFF000000) != 0 &&
701 (tmp & 0x00FF0000) != 0 && (tmp & 0x0000FF00) != 0 &&
702 (tmp & 0x000000FF) != 0);
705 case 0xA: /* decgt */
707 NEW_C ((long)cpu.gr[RD] > 0);
709 case 0xB: /* decne */
711 NEW_C ((long)cpu.gr[RD] != 0);
722 if (cpu.gr[RD] & 0x80000000)
723 cpu.gr[RD] = ~cpu.gr[RD] + 1;
726 cpu.gr[RD] = ~cpu.gr[RD];
730 case 0x02: /* movt */
732 cpu.gr[RD] = cpu.gr[RS];
734 case 0x03: /* mult */
735 /* consume 2 bits per cycle from rs, until rs is 0 */
737 unsigned int t = cpu.gr[RS];
739 for (ticks = 0; t != 0 ; t >>= 2)
741 bonus_cycles += ticks;
743 bonus_cycles += 2; /* min. is 3, so add 2, plus ticks above */
745 fprintf (stderr, " mult %lx by %lx to give %lx",
746 cpu.gr[RD], cpu.gr[RS], cpu.gr[RD] * cpu.gr[RS]);
747 cpu.gr[RD] = cpu.gr[RD] * cpu.gr[RS];
749 case 0x04: /* loopt */
752 pc += (IMM4 << 1) - 32;
756 --cpu.gr[RS]; /* not RD! */
757 NEW_C (((long)cpu.gr[RS]) > 0);
759 case 0x05: /* subu */
760 cpu.gr[RD] -= cpu.gr[RS];
762 case 0x06: /* addc */
764 unsigned long tmp, a, b;
767 cpu.gr[RD] = a + b + C_VALUE ();
768 tmp = iu_carry (a, b, C_VALUE ());
772 case 0x07: /* subc */
774 unsigned long tmp, a, b;
777 cpu.gr[RD] = a - b + C_VALUE () - 1;
778 tmp = iu_carry (a,~b, C_VALUE ());
782 case 0x08: /* illegal */
783 case 0x09: /* illegal*/
786 case 0x0A: /* movf */
788 cpu.gr[RD] = cpu.gr[RS];
792 unsigned long dst, src;
795 /* We must not rely solely upon the native shift operations, since they
796 may not match the M*Core's behaviour on boundary conditions. */
797 dst = src > 31 ? 0 : dst >> src;
801 case 0x0C: /* cmphs */
802 NEW_C ((unsigned long )cpu.gr[RD] >=
803 (unsigned long)cpu.gr[RS]);
805 case 0x0D: /* cmplt */
806 NEW_C ((long)cpu.gr[RD] < (long)cpu.gr[RS]);
809 NEW_C ((cpu.gr[RD] & cpu.gr[RS]) != 0);
811 case 0x0F: /* cmpne */
812 NEW_C (cpu.gr[RD] != cpu.gr[RS]);
814 case 0x10: case 0x11: /* mfcr */
818 if (r <= LAST_VALID_CREG)
819 cpu.gr[RD] = cpu.cr[r];
826 cpu.gr[RD] = cpu.gr[RS];
828 fprintf (stderr, "MOV %lx into reg %d", cpu.gr[RD], RD);
831 case 0x13: /* bgenr */
832 if (cpu.gr[RS] & 0x20)
835 cpu.gr[RD] = 1 << (cpu.gr[RS] & 0x1F);
838 case 0x14: /* rsub */
839 cpu.gr[RD] = cpu.gr[RS] - cpu.gr[RD];
843 cpu.gr[RD] += cpu.gr[RS]<<2;
847 cpu.gr[RD] &= cpu.gr[RS];
851 cpu.gr[RD] ^= cpu.gr[RS];
854 case 0x18: case 0x19: /* mtcr */
858 if (r <= LAST_VALID_CREG)
859 cpu.cr[r] = cpu.gr[RD];
863 /* we might have changed register sets... */
865 cpu.asregs.active_gregs = & cpu.asregs.alt_gregs[0];
867 cpu.asregs.active_gregs = & cpu.asregs.gregs[0];
872 /* We must not rely solely upon the native shift operations, since they
873 may not match the M*Core's behaviour on boundary conditions. */
875 cpu.gr[RD] = ((long) cpu.gr[RD]) < 0 ? -1 : 0;
877 cpu.gr[RD] = (long) cpu.gr[RD] >> cpu.gr[RS];
881 /* We must not rely solely upon the native shift operations, since they
882 may not match the M*Core's behaviour on boundary conditions. */
883 cpu.gr[RD] = cpu.gr[RS] > 31 ? 0 : cpu.gr[RD] << cpu.gr[RS];
886 case 0x1C: /* addu */
887 cpu.gr[RD] += cpu.gr[RS];
891 cpu.gr[RD] += cpu.gr[RS] << 1;
895 cpu.gr[RD] |= cpu.gr[RS];
898 case 0x1F: /* andn */
899 cpu.gr[RD] &= ~cpu.gr[RS];
901 case 0x20: case 0x21: /* addi */
903 cpu.gr[RD] + (IMM5 + 1);
905 case 0x22: case 0x23: /* cmplti */
907 int tmp = (IMM5 + 1);
908 if (cpu.gr[RD] < tmp)
918 case 0x24: case 0x25: /* subi */
920 cpu.gr[RD] - (IMM5 + 1);
922 case 0x26: case 0x27: /* illegal */
925 case 0x28: case 0x29: /* rsubi */
929 case 0x2A: case 0x2B: /* cmpnei */
930 if (cpu.gr[RD] != IMM5)
940 case 0x2C: case 0x2D: /* bmaski, divu */
954 /* unsigned divide */
955 cpu.gr[RD] = (word) ((unsigned int) cpu.gr[RD] / (unsigned int)cpu.gr[1] );
957 /* compute bonus_cycles for divu */
958 for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32); r1nlz ++)
961 for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32); rxnlz ++)
967 exe += 5 + r1nlz - rxnlz;
969 if (exe >= (2 * memcycles - 1))
971 bonus_cycles += exe - (2 * memcycles) + 1;
974 else if (imm == 0 || imm >= 8)
980 cpu.gr[RD] = (1 << imm) - 1;
989 case 0x2E: case 0x2F: /* andi */
990 cpu.gr[RD] = cpu.gr[RD] & IMM5;
992 case 0x30: case 0x31: /* bclri */
993 cpu.gr[RD] = cpu.gr[RD] & ~(1<<IMM5);
995 case 0x32: case 0x33: /* bgeni, divs */
1004 /* compute bonus_cycles for divu */
1009 if (((rx < 0) && (r1 > 0)) || ((rx >= 0) && (r1 < 0)))
1017 /* signed divide, general registers are of type int, so / op is OK */
1018 cpu.gr[RD] = cpu.gr[RD] / cpu.gr[1];
1020 for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32) ; r1nlz ++ )
1023 for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32) ; rxnlz ++ )
1029 exe += 6 + r1nlz - rxnlz + sc;
1031 if (exe >= (2 * memcycles - 1))
1033 bonus_cycles += exe - (2 * memcycles) + 1;
1039 cpu.gr[RD] = (1 << IMM5);
1048 case 0x34: case 0x35: /* bseti */
1049 cpu.gr[RD] = cpu.gr[RD] | (1 << IMM5);
1051 case 0x36: case 0x37: /* btsti */
1052 NEW_C (cpu.gr[RD] >> IMM5);
1054 case 0x38: case 0x39: /* xsr, rotli */
1056 unsigned imm = IMM5;
1057 unsigned long tmp = cpu.gr[RD];
1063 cpu.gr[RD] = (cbit << 31) | (tmp >> 1);
1066 cpu.gr[RD] = (tmp << imm) | (tmp >> (32 - imm));
1069 case 0x3A: case 0x3B: /* asrc, asri */
1071 unsigned imm = IMM5;
1072 long tmp = cpu.gr[RD];
1076 cpu.gr[RD] = tmp >> 1;
1079 cpu.gr[RD] = tmp >> imm;
1082 case 0x3C: case 0x3D: /* lslc, lsli */
1084 unsigned imm = IMM5;
1085 unsigned long tmp = cpu.gr[RD];
1089 cpu.gr[RD] = tmp << 1;
1092 cpu.gr[RD] = tmp << imm;
1095 case 0x3E: case 0x3F: /* lsrc, lsri */
1097 unsigned imm = IMM5;
1098 unsigned long tmp = cpu.gr[RD];
1102 cpu.gr[RD] = tmp >> 1;
1105 cpu.gr[RD] = tmp >> imm;
1108 case 0x40: case 0x41: case 0x42: case 0x43:
1109 case 0x44: case 0x45: case 0x46: case 0x47:
1110 case 0x48: case 0x49: case 0x4A: case 0x4B:
1111 case 0x4C: case 0x4D: case 0x4E: case 0x4F:
1115 util (sd, scpu, inst & 0xFF);
1117 case 0x51: case 0x52: case 0x53:
1118 case 0x54: case 0x55: case 0x56: case 0x57:
1119 case 0x58: case 0x59: case 0x5A: case 0x5B:
1120 case 0x5C: case 0x5D: case 0x5E: case 0x5F:
1123 case 0x60: case 0x61: case 0x62: case 0x63: /* movi */
1124 case 0x64: case 0x65: case 0x66: case 0x67:
1125 cpu.gr[RD] = (inst >> 4) & 0x7F;
1127 case 0x68: case 0x69: case 0x6A: case 0x6B:
1128 case 0x6C: case 0x6D: case 0x6E: case 0x6F: /* illegal */
1131 case 0x71: case 0x72: case 0x73:
1132 case 0x74: case 0x75: case 0x76: case 0x77:
1133 case 0x78: case 0x79: case 0x7A: case 0x7B:
1134 case 0x7C: case 0x7D: case 0x7E: /* lrw */
1135 cpu.gr[RX] = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
1137 fprintf (stderr, "LRW of 0x%x from 0x%lx to reg %d",
1138 rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC),
1139 (pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC, RX);
1142 case 0x7F: /* jsri */
1146 "func call: r2 = %lx r3 = %lx r4 = %lx r5 = %lx r6 = %lx r7 = %lx\n",
1147 cpu.gr[2], cpu.gr[3], cpu.gr[4], cpu.gr[5], cpu.gr[6], cpu.gr[7]);
1148 case 0x70: /* jmpi */
1149 pc = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
1155 case 0x80: case 0x81: case 0x82: case 0x83:
1156 case 0x84: case 0x85: case 0x86: case 0x87:
1157 case 0x88: case 0x89: case 0x8A: case 0x8B:
1158 case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */
1159 cpu.gr[RX] = rlat (cpu.gr[RD] + ((inst >> 2) & 0x003C));
1161 fprintf (stderr, "load reg %d from 0x%lx with 0x%lx",
1163 cpu.gr[RD] + ((inst >> 2) & 0x003C), cpu.gr[RX]);
1166 case 0x90: case 0x91: case 0x92: case 0x93:
1167 case 0x94: case 0x95: case 0x96: case 0x97:
1168 case 0x98: case 0x99: case 0x9A: case 0x9B:
1169 case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */
1170 wlat (cpu.gr[RD] + ((inst >> 2) & 0x003C), cpu.gr[RX]);
1172 fprintf (stderr, "store reg %d (containing 0x%lx) to 0x%lx",
1174 cpu.gr[RD] + ((inst >> 2) & 0x003C));
1177 case 0xA0: case 0xA1: case 0xA2: case 0xA3:
1178 case 0xA4: case 0xA5: case 0xA6: case 0xA7:
1179 case 0xA8: case 0xA9: case 0xAA: case 0xAB:
1180 case 0xAC: case 0xAD: case 0xAE: case 0xAF: /* ld.b */
1181 cpu.gr[RX] = rbat (cpu.gr[RD] + RS);
1184 case 0xB0: case 0xB1: case 0xB2: case 0xB3:
1185 case 0xB4: case 0xB5: case 0xB6: case 0xB7:
1186 case 0xB8: case 0xB9: case 0xBA: case 0xBB:
1187 case 0xBC: case 0xBD: case 0xBE: case 0xBF: /* st.b */
1188 wbat (cpu.gr[RD] + RS, cpu.gr[RX]);
1191 case 0xC0: case 0xC1: case 0xC2: case 0xC3:
1192 case 0xC4: case 0xC5: case 0xC6: case 0xC7:
1193 case 0xC8: case 0xC9: case 0xCA: case 0xCB:
1194 case 0xCC: case 0xCD: case 0xCE: case 0xCF: /* ld.h */
1195 cpu.gr[RX] = rhat (cpu.gr[RD] + ((inst >> 3) & 0x001E));
1198 case 0xD0: case 0xD1: case 0xD2: case 0xD3:
1199 case 0xD4: case 0xD5: case 0xD6: case 0xD7:
1200 case 0xD8: case 0xD9: case 0xDA: case 0xDB:
1201 case 0xDC: case 0xDD: case 0xDE: case 0xDF: /* st.h */
1202 what (cpu.gr[RD] + ((inst >> 3) & 0x001E), cpu.gr[RX]);
1205 case 0xE8: case 0xE9: case 0xEA: case 0xEB:
1206 case 0xEC: case 0xED: case 0xEE: case 0xEF: /* bf */
1210 disp = inst & 0x03FF;
1218 case 0xE0: case 0xE1: case 0xE2: case 0xE3:
1219 case 0xE4: case 0xE5: case 0xE6: case 0xE7: /* bt */
1223 disp = inst & 0x03FF;
1232 case 0xF8: case 0xF9: case 0xFA: case 0xFB:
1233 case 0xFC: case 0xFD: case 0xFE: case 0xFF: /* bsr */
1235 case 0xF0: case 0xF1: case 0xF2: case 0xF3:
1236 case 0xF4: case 0xF5: case 0xF6: case 0xF7: /* br */
1239 disp = inst & 0x03FF;
1251 fprintf (stderr, "\n");
1255 ibuf = rlat (pc & 0xFFFFFFFC);
1260 /* Hide away the things we've cached while executing. */
1261 CPU_PC_SET (scpu, pc);
1262 cpu.asregs.insts += insts; /* instructions done ... */
1263 cpu.asregs.cycles += insts; /* and each takes a cycle */
1264 cpu.asregs.cycles += bonus_cycles; /* and extra cycles for branches */
1265 cpu.asregs.cycles += memops * memcycles; /* and memop cycle delays */
1269 sim_engine_run (SIM_DESC sd,
1270 int next_cpu_nr, /* ignore */
1271 int nr_cpus, /* ignore */
1272 int siggnal) /* ignore */
1276 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1278 scpu = STATE_CPU (sd, 0);
1282 step_once (sd, scpu);
1283 if (sim_events_tick (sd))
1284 sim_events_process (sd);
1289 mcore_reg_store (SIM_CPU *scpu, int rn, unsigned char *memory, int length)
1291 if (rn < NUM_MCORE_REGS && rn >= 0)
1297 /* misalignment safe */
1298 ival = mcore_extract_unsigned_integer (memory, 4);
1299 cpu.asints[rn] = ival;
1309 mcore_reg_fetch (SIM_CPU *scpu, int rn, unsigned char *memory, int length)
1311 if (rn < NUM_MCORE_REGS && rn >= 0)
1315 long ival = cpu.asints[rn];
1317 /* misalignment-safe */
1318 mcore_store_unsigned_integer (memory, 4, ival);
1328 sim_info (SIM_DESC sd, int verbose)
1330 #ifdef WATCHFUNCTIONS
1333 double virttime = cpu.asregs.cycles / 36.0e6;
1334 host_callback *callback = STATE_CALLBACK (sd);
1336 callback->printf_filtered (callback, "\n\n# instructions executed %10d\n",
1338 callback->printf_filtered (callback, "# cycles %10d\n",
1340 callback->printf_filtered (callback, "# pipeline stalls %10d\n",
1342 callback->printf_filtered (callback, "# virtual time taken %10.4f\n",
1345 #ifdef WATCHFUNCTIONS
1346 callback->printf_filtered (callback, "\nNumber of watched functions: %d\n",
1351 for (w = 1; w <= ENDWL; w++)
1353 callback->printf_filtered (callback, "WL = %s %8x\n",WLstr[w],WL[w]);
1354 callback->printf_filtered (callback, " calls = %d, cycles = %d\n",
1355 WLcnts[w],WLcyc[w]);
1358 callback->printf_filtered (callback,
1359 " maxcpc = %d, mincpc = %d, avecpc = %d\n",
1360 WLmax[w],WLmin[w],WLcyc[w]/WLcnts[w]);
1364 callback->printf_filtered (callback,
1365 "Total cycles for watched functions: %d\n",wcyc);
1370 mcore_pc_get (sim_cpu *cpu)
1376 mcore_pc_set (sim_cpu *cpu, sim_cia pc)
1382 free_state (SIM_DESC sd)
1384 if (STATE_MODULES (sd) != NULL)
1385 sim_module_uninstall (sd);
1386 sim_cpu_free_all (sd);
1387 sim_state_free (sd);
1391 sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
1394 SIM_DESC sd = sim_state_alloc (kind, cb);
1395 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1397 /* The cpu data is kept in a separately allocated chunk of memory. */
1398 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
1404 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1410 /* getopt will print the error message so we just have to exit if this fails.
1411 FIXME: Hmmm... in the case of gdb we need getopt to call
1413 if (sim_parse_args (sd, argv) != SIM_RC_OK)
1419 /* Check for/establish the a reference program image. */
1420 if (sim_analyze_program (sd,
1421 (STATE_PROG_ARGV (sd) != NULL
1422 ? *STATE_PROG_ARGV (sd)
1423 : NULL), abfd) != SIM_RC_OK)
1429 /* Configure/verify the target byte order and other runtime
1430 configuration options. */
1431 if (sim_config (sd) != SIM_RC_OK)
1433 sim_module_uninstall (sd);
1437 if (sim_post_argv_init (sd) != SIM_RC_OK)
1439 /* Uninstall the modules to avoid memory leaks,
1440 file descriptor leaks, etc. */
1441 sim_module_uninstall (sd);
1445 /* CPU specific initialization. */
1446 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
1448 SIM_CPU *cpu = STATE_CPU (sd, i);
1450 CPU_REG_FETCH (cpu) = mcore_reg_fetch;
1451 CPU_REG_STORE (cpu) = mcore_reg_store;
1452 CPU_PC_FETCH (cpu) = mcore_pc_get;
1453 CPU_PC_STORE (cpu) = mcore_pc_set;
1455 set_initial_gprs (cpu); /* Reset the GPR registers. */
1458 /* Default to a 8 Mbyte (== 2^23) memory space. */
1459 sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEMORY_SIZE);
1465 sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
1467 SIM_CPU *scpu = STATE_CPU (sd, 0);
1473 unsigned long strings;
1474 unsigned long pointers;
1475 unsigned long hi_stack;
1478 /* Set the initial register set. */
1479 set_initial_gprs (scpu);
1481 hi_stack = DEFAULT_MEMORY_SIZE - 4;
1482 CPU_PC_SET (scpu, bfd_get_start_address (prog_bfd));
1484 /* Calculate the argument and environment strings. */
1490 l = strlen (*avp) + 1; /* include the null */
1491 s_length += (l + 3) & ~3; /* make it a 4 byte boundary */
1499 l = strlen (*avp) + 1; /* include the null */
1500 s_length += (l + 3) & ~ 3;/* make it a 4 byte boundary */
1504 /* Claim some memory for the pointers and strings. */
1505 pointers = hi_stack - sizeof(word) * (nenv+1+nargs+1);
1506 pointers &= ~3; /* must be 4-byte aligned */
1507 cpu.gr[0] = pointers;
1509 strings = cpu.gr[0] - s_length;
1510 strings &= ~3; /* want to make it 4-byte aligned */
1511 cpu.gr[0] = strings;
1512 /* dac fix, the stack address must be 8-byte aligned! */
1513 cpu.gr[0] = cpu.gr[0] - cpu.gr[0] % 8;
1515 /* Loop through the arguments and fill them in. */
1516 cpu.gr[PARM1] = nargs;
1519 /* No strings to fill in. */
1524 cpu.gr[PARM2] = pointers;
1528 /* Save where we're putting it. */
1529 wlat (pointers, strings);
1531 /* Copy the string. */
1532 l = strlen (* avp) + 1;
1533 sim_core_write_buffer (sd, scpu, write_map, *avp, strings, l);
1535 /* Bump the pointers. */
1541 /* A null to finish the list. */
1546 /* Now do the environment pointers. */
1549 /* No strings to fill in. */
1554 cpu.gr[PARM3] = pointers;
1559 /* Save where we're putting it. */
1560 wlat (pointers, strings);
1562 /* Copy the string. */
1563 l = strlen (* avp) + 1;
1564 sim_core_write_buffer (sd, scpu, write_map, *avp, strings, l);
1566 /* Bump the pointers. */
1572 /* A null to finish the list. */