1 /* interp.c -- Simulator for Motorola 68HC11/68HC12
2 Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "sim-assert.h"
23 #include "sim-options.h"
25 #include "hw-device.h"
27 #include "elf32-m68hc1x.h"
30 # define MONITOR_BASE (0x0C000)
31 # define MONITOR_SIZE (0x04000)
34 static void sim_get_info (SIM_DESC sd, char *cmd);
37 char *interrupt_names[] = {
50 struct sim_info_list dev_list_68hc11[] = {
52 {"timer", "/m68hc11/m68hc11tim"},
53 {"sio", "/m68hc11/m68hc11sio"},
54 {"spi", "/m68hc11/m68hc11spi"},
55 {"eeprom", "/m68hc11/m68hc11eepr"},
59 struct sim_info_list dev_list_68hc12[] = {
61 {"timer", "/m68hc12/m68hc12tim"},
62 {"sio", "/m68hc12/m68hc12sio"},
63 {"spi", "/m68hc12/m68hc12spi"},
64 {"eeprom", "/m68hc12/m68hc12eepr"},
68 /* Cover function of sim_state_free to free the cpu buffers as well. */
71 free_state (SIM_DESC sd)
73 if (STATE_MODULES (sd) != NULL)
74 sim_module_uninstall (sd);
79 /* Give some information about the simulator. */
81 sim_get_info (SIM_DESC sd, char *cmd)
85 cpu = STATE_CPU (sd, 0);
86 if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
90 struct sim_info_list *dev_list;
91 const struct bfd_arch_info *arch;
93 arch = STATE_ARCHITECTURE (sd);
96 if (arch->arch == bfd_arch_m68hc11)
97 dev_list = dev_list_68hc11;
99 dev_list = dev_list_68hc12;
101 for (i = 0; dev_list[i].name; i++)
102 if (strcmp (cmd, dev_list[i].name) == 0)
105 if (dev_list[i].name == 0)
107 sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
108 sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
111 hw_dev = sim_hw_parse (sd, dev_list[i].device);
114 sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
117 hw_ioctl (hw_dev, 23, 0);
122 interrupts_info (sd, &cpu->cpu_interrupts);
127 sim_board_reset (SIM_DESC sd)
131 const struct bfd_arch_info *arch;
132 const char *cpu_type;
134 cpu = STATE_CPU (sd, 0);
135 arch = STATE_ARCHITECTURE (sd);
137 /* hw_cpu = sim_hw_parse (sd, "/"); */
138 if (arch->arch == bfd_arch_m68hc11)
140 cpu->cpu_type = CPU_M6811;
141 cpu_type = "/m68hc11";
145 cpu->cpu_type = CPU_M6812;
146 cpu_type = "/m68hc12";
149 hw_cpu = sim_hw_parse (sd, cpu_type);
152 sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
157 hw_port_event (hw_cpu, 3, 0);
162 sim_hw_configure (SIM_DESC sd)
164 const struct bfd_arch_info *arch;
165 struct hw *device_tree;
168 arch = STATE_ARCHITECTURE (sd);
172 cpu = STATE_CPU (sd, 0);
173 cpu->cpu_configured_arch = arch;
174 device_tree = sim_hw_parse (sd, "/");
175 if (arch->arch == bfd_arch_m68hc11)
177 cpu->cpu_interpretor = cpu_interp_m6811;
178 if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
180 /* Allocate core managed memory */
183 sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
184 /* MONITOR_BASE, MONITOR_SIZE */
185 0x8000, M6811_RAM_LEVEL, 0x8000);
186 sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
188 sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
189 if (cpu->bank_start < cpu->bank_end)
191 sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
192 cpu->bank_virtual, M6811_RAM_LEVEL);
193 sim_hw_parse (sd, "/m68hc11/use_bank 1");
196 if (cpu->cpu_start_mode)
198 sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode);
200 if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
202 sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
203 sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
204 sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
206 if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
208 /* M68hc11 Timer configuration. */
209 sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
210 sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
211 sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
214 /* Create the SPI device. */
215 if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
217 sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
218 sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
220 if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
222 /* M68hc11 persistent ram configuration. */
223 sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
224 sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
225 sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
226 /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
228 if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
230 sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
231 sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
233 sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
234 sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
235 sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
236 sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
237 cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
241 cpu->cpu_interpretor = cpu_interp_m6812;
242 if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
244 /* Allocate core external memory. */
245 sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
246 0x8000, M6811_RAM_LEVEL, 0x8000);
247 sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
249 if (cpu->bank_start < cpu->bank_end)
251 sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
252 cpu->bank_virtual, M6811_RAM_LEVEL);
253 sim_hw_parse (sd, "/m68hc12/use_bank 1");
255 sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
258 if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
260 sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
261 sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
262 sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
264 if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
266 /* M68hc11 Timer configuration. */
267 sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
268 sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
269 sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
272 /* Create the SPI device. */
273 if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
275 sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
276 sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
278 if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
280 /* M68hc11 persistent ram configuration. */
281 sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
282 sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
283 sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
285 if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
287 sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
288 sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
291 sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
292 sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
293 sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
294 sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
295 cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
300 /* Get the memory bank parameters by looking at the global symbols
301 defined by the linker. */
303 sim_get_bank_parameters (SIM_DESC sd, bfd* abfd)
307 long symbol_count, i;
312 cpu = STATE_CPU (sd, 0);
314 symsize = bfd_get_symtab_upper_bound (abfd);
317 sim_io_eprintf (sd, "Cannot read symbols of program");
320 asymbols = (asymbol **) xmalloc (symsize);
321 symbol_count = bfd_canonicalize_symtab (abfd, asymbols);
322 if (symbol_count < 0)
324 sim_io_eprintf (sd, "Cannot read symbols of program");
329 for (i = 0, current = asymbols; i < symbol_count; i++, current++)
331 const char* name = bfd_asymbol_name (*current);
333 if (strcmp (name, BFD_M68HC11_BANK_START_NAME) == 0)
335 cpu->bank_start = bfd_asymbol_value (*current);
337 else if (strcmp (name, BFD_M68HC11_BANK_SIZE_NAME) == 0)
339 size = bfd_asymbol_value (*current);
341 else if (strcmp (name, BFD_M68HC11_BANK_VIRTUAL_NAME) == 0)
343 cpu->bank_virtual = bfd_asymbol_value (*current);
348 cpu->bank_end = cpu->bank_start + size;
350 for (; size > 1; size >>= 1)
357 sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
362 cpu = STATE_CPU (sd, 0);
368 if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
369 elf_flags = elf_elfheader (abfd)->e_flags;
371 cpu->cpu_elf_start = bfd_get_start_address (abfd);
372 /* See if any section sets the reset address */
373 cpu->cpu_use_elf_start = 1;
374 for (s = abfd->sections; s && cpu->cpu_use_elf_start; s = s->next)
376 if (s->flags & SEC_LOAD)
380 size = bfd_get_section_size (s);
385 if (STATE_LOAD_AT_LMA_P (sd))
386 lma = bfd_section_lma (abfd, s);
388 lma = bfd_section_vma (abfd, s);
390 if (lma <= 0xFFFE && lma+size >= 0x10000)
391 cpu->cpu_use_elf_start = 0;
396 if (elf_flags & E_M68HC12_BANKS)
398 if (sim_get_bank_parameters (sd, abfd) != 0)
399 sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
403 if (!sim_hw_configure (sd))
406 /* reset all state information */
407 sim_board_reset (sd);
413 m68hc11_pc_get (sim_cpu *cpu)
415 return cpu_get_pc (cpu);
419 m68hc11_pc_set (sim_cpu *cpu, sim_cia pc)
421 cpu_set_pc (cpu, pc);
425 sim_open (SIM_OPEN_KIND kind, host_callback *callback,
426 bfd *abfd, char **argv)
432 sd = sim_state_alloc (kind, callback);
434 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
436 /* The cpu data is kept in a separately allocated chunk of memory. */
437 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
443 cpu = STATE_CPU (sd, 0);
445 /* for compatibility */
446 current_alignment = NONSTRICT_ALIGNMENT;
447 current_target_byte_order = BIG_ENDIAN;
449 cpu_initialize (sd, cpu);
451 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
457 /* getopt will print the error message so we just have to exit if this fails.
458 FIXME: Hmmm... in the case of gdb we need getopt to call
460 if (sim_parse_args (sd, argv) != SIM_RC_OK)
462 /* Uninstall the modules to avoid memory leaks,
463 file descriptor leaks, etc. */
468 /* Check for/establish the a reference program image. */
469 if (sim_analyze_program (sd,
470 (STATE_PROG_ARGV (sd) != NULL
471 ? *STATE_PROG_ARGV (sd)
472 : NULL), abfd) != SIM_RC_OK)
478 /* Establish any remaining configuration options. */
479 if (sim_config (sd) != SIM_RC_OK)
485 if (sim_post_argv_init (sd) != SIM_RC_OK)
487 /* Uninstall the modules to avoid memory leaks,
488 file descriptor leaks, etc. */
492 if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
498 /* CPU specific initialization. */
499 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
501 SIM_CPU *cpu = STATE_CPU (sd, i);
503 CPU_PC_FETCH (cpu) = m68hc11_pc_get;
504 CPU_PC_STORE (cpu) = m68hc11_pc_set;
512 sim_close (SIM_DESC sd, int quitting)
514 /* shut down modules */
515 sim_module_uninstall (sd);
517 /* Ensure that any resources allocated through the callback
518 mechanism are released: */
519 sim_io_shutdown (sd);
521 /* FIXME - free SD */
526 /* Generic implementation of sim_engine_run that works within the
527 sim_engine setjmp/longjmp framework. */
530 sim_engine_run (SIM_DESC sd,
531 int next_cpu_nr, /* ignore */
532 int nr_cpus, /* ignore */
533 int siggnal) /* ignore */
537 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
538 cpu = STATE_CPU (sd, 0);
541 cpu_single_step (cpu);
543 /* process any events */
544 if (sim_events_tickn (sd, cpu->cpu_current_cycle))
546 sim_events_process (sd);
552 sim_info (SIM_DESC sd, int verbose)
554 const char *cpu_type;
555 const struct bfd_arch_info *arch;
557 /* Nothing to do if there is no verbose flag set. */
558 if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
561 arch = STATE_ARCHITECTURE (sd);
562 if (arch->arch == bfd_arch_m68hc11)
567 sim_io_eprintf (sd, "Simulator info:\n");
568 sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type);
569 sim_get_info (sd, 0);
570 sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
574 sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
575 char **argv, char **env)
577 return sim_prepare_for_program (sd, abfd);
581 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
587 cpu = STATE_CPU (sd, 0);
591 val = cpu_get_a (cpu);
596 val = cpu_get_b (cpu);
601 val = cpu_get_d (cpu);
605 val = cpu_get_x (cpu);
609 val = cpu_get_y (cpu);
613 val = cpu_get_sp (cpu);
617 val = cpu_get_pc (cpu);
621 val = cpu_get_ccr (cpu);
626 val = cpu_get_page (cpu);
640 memory[0] = val >> 8;
641 memory[1] = val & 0x0FF;
647 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
652 cpu = STATE_CPU (sd, 0);
656 val = (val << 8) | *memory;
661 cpu_set_d (cpu, val);
665 cpu_set_a (cpu, val);
669 cpu_set_b (cpu, val);
673 cpu_set_x (cpu, val);
677 cpu_set_y (cpu, val);
681 cpu_set_sp (cpu, val);
685 cpu_set_pc (cpu, val);
689 cpu_set_ccr (cpu, val);
693 cpu_set_page (cpu, val);