1 /* dv-m68hc11spi.c -- Simulation of the 68HC11 SPI
2 Copyright (C) 2000-2017 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
4 (From a driver model Contributed by Cygnus Solutions.)
6 This file is part of the program GDB, the GNU debugger.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>.
26 #include "dv-sockser.h"
27 #include "sim-assert.h"
32 m68hc11spi - m68hc11 SPI interface
37 Implements the m68hc11 Synchronous Serial Peripheral Interface
38 described in the m68hc11 user guide (Chapter 8 in pink book).
39 The SPI I/O controller is directly connected to the CPU
40 interrupt. The simulator implements:
44 - Write collision detection
56 Reset port. This port is only used to simulate a reset of the SPI
57 I/O controller. It should be connected to the RESET output of the cpu.
71 static const struct hw_port_descriptor m68hc11spi_ports[] =
73 { "reset", RESET_PORT, 0, input_port, },
81 /* Information about next character to be transmited. */
82 unsigned char tx_char;
86 unsigned char rx_char;
87 unsigned char rx_clear_scsr;
88 unsigned char clk_pin;
90 /* SPI clock rate (twice the real clock). */
93 /* Periodic SPI event. */
94 struct hw_event* spi_event;
99 /* Finish off the partially created hw device. Attach our local
100 callbacks. Wire up our port names etc */
102 static hw_io_read_buffer_method m68hc11spi_io_read_buffer;
103 static hw_io_write_buffer_method m68hc11spi_io_write_buffer;
104 static hw_port_event_method m68hc11spi_port_event;
105 static hw_ioctl_method m68hc11spi_ioctl;
107 #define M6811_SPI_FIRST_REG (M6811_SPCR)
108 #define M6811_SPI_LAST_REG (M6811_SPDR)
112 attach_m68hc11spi_regs (struct hw *me,
113 struct m68hc11spi *controller)
115 hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
117 M6811_SPI_LAST_REG - M6811_SPI_FIRST_REG + 1,
122 m68hc11spi_finish (struct hw *me)
124 struct m68hc11spi *controller;
126 controller = HW_ZALLOC (me, struct m68hc11spi);
127 set_hw_data (me, controller);
128 set_hw_io_read_buffer (me, m68hc11spi_io_read_buffer);
129 set_hw_io_write_buffer (me, m68hc11spi_io_write_buffer);
130 set_hw_ports (me, m68hc11spi_ports);
131 set_hw_port_event (me, m68hc11spi_port_event);
133 set_hw_ioctl (me, m68hc11spi_ioctl);
135 me->to_ioctl = m68hc11spi_ioctl;
138 /* Attach ourself to our parent bus. */
139 attach_m68hc11spi_regs (me, controller);
141 /* Initialize to reset state. */
142 controller->spi_event = NULL;
143 controller->rx_clear_scsr = 0;
148 /* An event arrives on an interrupt port */
151 m68hc11spi_port_event (struct hw *me,
158 struct m68hc11spi *controller;
162 controller = hw_data (me);
164 cpu = STATE_CPU (sd, 0);
169 HW_TRACE ((me, "SPI reset"));
171 /* Reset the state of SPI registers. */
172 controller->rx_clear_scsr = 0;
173 if (controller->spi_event)
175 hw_event_queue_deschedule (me, controller->spi_event);
176 controller->spi_event = 0;
180 m68hc11spi_io_write_buffer (me, &val, io_map,
181 (unsigned_word) M6811_SPCR, 1);
186 hw_abort (me, "Event on unknown port %d", my_port);
192 set_bit_port (struct hw *me, sim_cpu *cpu, int port, int mask, int value)
197 val = cpu->ios[port] | mask;
199 val = cpu->ios[port] & ~mask;
201 /* Set the new value and post an event to inform other devices
202 that pin 'port' changed. */
203 m68hc11cpu_set_port (me, cpu, port, val);
207 /* When a character is sent/received by the SPI, the PD2..PD5 line
208 are driven by the following signals:
211 -----+---------+--------+---/-+-------
213 MISO +---------+--------+---/-+
215 CLK _______/ \____/ \__ CPOL=0, CPHA=0
217 \____/ \___/ CPOL=1, CPHA=0
219 __/ \____/ \___/ CPOL=0, CPHA=1
221 \____/ \____/ \__ CPOL=1, CPHA=1
224 \__________________________//___/
233 #define SPI_START_BYTE 0
234 #define SPI_START_BIT 1
235 #define SPI_MIDDLE_BIT 2
238 m68hc11spi_clock (struct hw *me, void *data)
241 struct m68hc11spi* controller;
243 int check_interrupt = 0;
245 controller = hw_data (me);
247 cpu = STATE_CPU (sd, 0);
249 /* Cleanup current event. */
250 if (controller->spi_event)
252 hw_event_queue_deschedule (me, controller->spi_event);
253 controller->spi_event = 0;
256 /* Change a bit of data at each two SPI event. */
257 if (controller->mode == SPI_START_BIT)
259 /* Reflect the bit value on bit 2 of port D. */
260 set_bit_port (me, cpu, M6811_PORTD, (1 << 2),
261 (controller->tx_char & (1 << controller->tx_bit)));
262 controller->tx_bit--;
263 controller->mode = SPI_MIDDLE_BIT;
265 else if (controller->mode == SPI_MIDDLE_BIT)
267 controller->mode = SPI_START_BIT;
270 if (controller->mode == SPI_START_BYTE)
272 /* Start a new SPI transfer. */
274 /* TBD: clear SS output. */
275 controller->mode = SPI_START_BIT;
276 controller->tx_bit = 7;
277 set_bit_port (me, cpu, M6811_PORTD, (1 << 4), ~controller->clk_pin);
281 /* Change the SPI clock at each event on bit 4 of port D. */
282 controller->clk_pin = ~controller->clk_pin;
283 set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
286 /* Transmit is now complete for this byte. */
287 if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
289 controller->rx_clear_scsr = 0;
290 cpu->ios[M6811_SPSR] |= M6811_SPIF;
291 if (cpu->ios[M6811_SPCR] & M6811_SPIE)
296 controller->spi_event = hw_event_queue_schedule (me, controller->clock,
302 interrupts_update_pending (&cpu->cpu_interrupts);
305 /* Flags of the SPCR register. */
306 io_reg_desc spcr_desc[] = {
307 { M6811_SPIE, "SPIE ", "Serial Peripheral Interrupt Enable" },
308 { M6811_SPE, "SPE ", "Serial Peripheral System Enable" },
309 { M6811_DWOM, "DWOM ", "Port D Wire-OR mode option" },
310 { M6811_MSTR, "MSTR ", "Master Mode Select" },
311 { M6811_CPOL, "CPOL ", "Clock Polarity" },
312 { M6811_CPHA, "CPHA ", "Clock Phase" },
313 { M6811_SPR1, "SPR1 ", "SPI Clock Rate Select" },
314 { M6811_SPR0, "SPR0 ", "SPI Clock Rate Select" },
319 /* Flags of the SPSR register. */
320 io_reg_desc spsr_desc[] = {
321 { M6811_SPIF, "SPIF ", "SPI Transfer Complete flag" },
322 { M6811_WCOL, "WCOL ", "Write Collision" },
323 { M6811_MODF, "MODF ", "Mode Fault" },
328 m68hc11spi_info (struct hw *me)
333 struct m68hc11spi *controller;
337 cpu = STATE_CPU (sd, 0);
338 controller = hw_data (me);
340 sim_io_printf (sd, "M68HC11 SPI:\n");
342 base = cpu_get_io_base (cpu);
344 val = cpu->ios[M6811_SPCR];
345 print_io_byte (sd, "SPCR", spcr_desc, val, base + M6811_SPCR);
346 sim_io_printf (sd, "\n");
348 val = cpu->ios[M6811_SPSR];
349 print_io_byte (sd, "SPSR", spsr_desc, val, base + M6811_SPSR);
350 sim_io_printf (sd, "\n");
352 if (controller->spi_event)
356 sim_io_printf (sd, " SPI has %d bits to send\n",
357 controller->tx_bit + 1);
358 t = hw_event_remain_time (me, controller->spi_event);
359 sim_io_printf (sd, " SPI current bit-cycle finished in %s\n",
360 cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE));
362 t += (controller->tx_bit + 1) * 2 * controller->clock;
363 sim_io_printf (sd, " SPI operation finished in %s\n",
364 cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE));
369 m68hc11spi_ioctl (struct hw *me,
370 hw_ioctl_request request,
373 m68hc11spi_info (me);
377 /* generic read/write */
380 m68hc11spi_io_read_buffer (struct hw *me,
387 struct m68hc11spi *controller;
391 HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
394 cpu = STATE_CPU (sd, 0);
395 controller = hw_data (me);
400 controller->rx_clear_scsr = cpu->ios[M6811_SCSR]
401 & (M6811_SPIF | M6811_WCOL | M6811_MODF);
404 val = cpu->ios[base];
408 if (controller->rx_clear_scsr)
410 cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
411 controller->rx_clear_scsr = 0;
412 interrupts_update_pending (&cpu->cpu_interrupts);
414 val = controller->rx_char;
420 *((unsigned8*) dest) = val;
425 m68hc11spi_io_write_buffer (struct hw *me,
432 struct m68hc11spi *controller;
436 HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
439 cpu = STATE_CPU (sd, 0);
440 controller = hw_data (me);
442 val = *((const unsigned8*) source);
446 cpu->ios[M6811_SPCR] = val;
448 /* The SPI clock rate is 2, 4, 16, 32 of the internal CPU clock.
449 We have to drive the clock pin and need a 2x faster clock. */
450 switch (val & (M6811_SPR1 | M6811_SPR0))
453 controller->clock = 1;
457 controller->clock = 2;
461 controller->clock = 8;
465 controller->clock = 16;
469 /* Set the clock pin. */
470 if ((val & M6811_CPOL)
471 && (controller->spi_event == 0
472 || ((val & M6811_CPHA) && controller->mode == 1)))
473 controller->clk_pin = 1;
475 controller->clk_pin = 0;
477 set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
480 /* Can't write to SPSR. */
485 if (!(cpu->ios[M6811_SPCR] & M6811_SPE))
490 if (controller->rx_clear_scsr)
492 cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
493 controller->rx_clear_scsr = 0;
494 interrupts_update_pending (&cpu->cpu_interrupts);
497 /* If transfer is taking place, a write to SPDR
498 generates a collision. */
499 if (controller->spi_event)
501 cpu->ios[M6811_SPSR] |= M6811_WCOL;
505 /* Refuse the write if there was no read of SPSR. */
508 /* Prepare to send a byte. */
509 controller->tx_char = val;
510 controller->mode = SPI_START_BYTE;
512 /* Toggle clock pin internal value when CPHA is 0 so that
513 it will really change in the middle of a bit. */
514 if (!(cpu->ios[M6811_SPCR] & M6811_CPHA))
515 controller->clk_pin = ~controller->clk_pin;
517 cpu->ios[M6811_SPDR] = val;
519 /* Activate transmission. */
520 m68hc11spi_clock (me, NULL);
530 const struct hw_descriptor dv_m68hc11spi_descriptor[] = {
531 { "m68hc11spi", m68hc11spi_finish },
532 { "m68hc12spi", m68hc11spi_finish },