1 /* dv-m68hc11sio.c -- Simulation of the 68HC11 serial device.
2 Copyright (C) 1999-2018 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
4 (From a driver model Contributed by Cygnus Solutions.)
6 This file is part of the program GDB, the GNU debugger.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>.
26 #include "dv-sockser.h"
27 #include "sim-assert.h"
32 m68hc11sio - m68hc11 serial I/O
37 Implements the m68hc11 serial I/O controller described in the m68hc11
38 user guide. The serial I/O controller is directly connected to the CPU
39 interrupt. The simulator implements:
48 Use dv-sockser TCP-port backend or stdio for backend. Default: stdio.
55 Reset port. This port is only used to simulate a reset of the serial
56 I/O controller. It should be connected to the RESET output of the cpu.
70 static const struct hw_port_descriptor m68hc11sio_ports[] =
72 { "reset", RESET_PORT, 0, input_port, },
77 /* Serial Controller information. */
80 enum {sio_tcp, sio_stdio} backend; /* backend */
82 /* Number of cpu cycles to send a bit on the wire. */
83 unsigned long baud_cycle;
85 /* Length in bits of characters sent, this includes the
86 start/stop and parity bits. Together with baud_cycle, this
87 is used to find the number of cpu cycles to send/receive a data. */
88 unsigned int data_length;
90 /* Information about next character to be transmited. */
91 unsigned char tx_has_char;
92 unsigned char tx_char;
94 unsigned char rx_char;
95 unsigned char rx_clear_scsr;
97 /* Periodic I/O polling. */
98 struct hw_event* tx_poll_event;
99 struct hw_event* rx_poll_event;
104 /* Finish off the partially created hw device. Attach our local
105 callbacks. Wire up our port names etc. */
107 static hw_io_read_buffer_method m68hc11sio_io_read_buffer;
108 static hw_io_write_buffer_method m68hc11sio_io_write_buffer;
109 static hw_port_event_method m68hc11sio_port_event;
110 static hw_ioctl_method m68hc11sio_ioctl;
112 #define M6811_SCI_FIRST_REG (M6811_BAUD)
113 #define M6811_SCI_LAST_REG (M6811_SCDR)
117 attach_m68hc11sio_regs (struct hw *me,
118 struct m68hc11sio *controller)
120 hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
122 M6811_SCI_LAST_REG - M6811_SCI_FIRST_REG + 1,
125 if (hw_find_property(me, "backend") != NULL)
127 const char *value = hw_find_string_property(me, "backend");
128 if(! strcmp(value, "tcp"))
129 controller->backend = sio_tcp;
130 else if(! strcmp(value, "stdio"))
131 controller->backend = sio_stdio;
133 hw_abort (me, "illegal value for backend parameter `%s':"
134 "use tcp or stdio", value);
140 m68hc11sio_finish (struct hw *me)
142 struct m68hc11sio *controller;
144 controller = HW_ZALLOC (me, struct m68hc11sio);
145 set_hw_data (me, controller);
146 set_hw_io_read_buffer (me, m68hc11sio_io_read_buffer);
147 set_hw_io_write_buffer (me, m68hc11sio_io_write_buffer);
148 set_hw_ports (me, m68hc11sio_ports);
149 set_hw_port_event (me, m68hc11sio_port_event);
151 set_hw_ioctl (me, m68hc11sio_ioctl);
153 me->to_ioctl = m68hc11sio_ioctl;
156 /* Preset defaults. */
157 controller->backend = sio_stdio;
159 /* Attach ourself to our parent bus. */
160 attach_m68hc11sio_regs (me, controller);
162 /* Initialize to reset state. */
163 controller->tx_poll_event = NULL;
164 controller->rx_poll_event = NULL;
165 controller->tx_char = 0;
166 controller->tx_has_char = 0;
167 controller->rx_clear_scsr = 0;
168 controller->rx_char = 0;
173 /* An event arrives on an interrupt port. */
176 m68hc11sio_port_event (struct hw *me,
183 struct m68hc11sio *controller;
187 controller = hw_data (me);
189 cpu = STATE_CPU (sd, 0);
194 HW_TRACE ((me, "SCI reset"));
196 /* Reset the state of SCI registers. */
198 m68hc11sio_io_write_buffer (me, &val, io_map,
199 (unsigned_word) M6811_BAUD, 1);
200 m68hc11sio_io_write_buffer (me, &val, io_map,
201 (unsigned_word) M6811_SCCR1, 1);
202 m68hc11sio_io_write_buffer (me, &val, io_map,
203 (unsigned_word) M6811_SCCR2, 1);
205 cpu->ios[M6811_SCSR] = M6811_TC | M6811_TDRE;
206 controller->rx_char = 0;
207 controller->tx_char = 0;
208 controller->tx_has_char = 0;
209 controller->rx_clear_scsr = 0;
210 if (controller->rx_poll_event)
212 hw_event_queue_deschedule (me, controller->rx_poll_event);
213 controller->rx_poll_event = 0;
215 if (controller->tx_poll_event)
217 hw_event_queue_deschedule (me, controller->tx_poll_event);
218 controller->tx_poll_event = 0;
221 /* In bootstrap mode, initialize the SCI to 1200 bauds to
222 simulate some initial setup by the internal rom. */
223 if (((cpu->ios[M6811_HPRIO]) & (M6811_SMOD | M6811_MDA)) == M6811_SMOD)
225 unsigned char val = 0x33;
227 m68hc11sio_io_write_buffer (me, &val, io_map,
228 (unsigned_word) M6811_BAUD, 1);
230 m68hc11sio_io_write_buffer (me, &val, io_map,
231 (unsigned_word) M6811_SCCR2, 1);
237 hw_abort (me, "Event on unknown port %d", my_port);
244 m68hc11sio_rx_poll (struct hw *me, void *data)
247 struct m68hc11sio *controller;
251 int check_interrupt = 0;
253 controller = hw_data (me);
255 cpu = STATE_CPU (sd, 0);
256 switch (controller->backend)
259 cnt = dv_sockser_read (sd);
268 cnt = sim_io_poll_read (sd, 0 /* stdin */, &cc, 1);
278 /* Raise the overrun flag if the previous character was not read. */
279 if (cpu->ios[M6811_SCSR] & M6811_RDRF)
280 cpu->ios[M6811_SCSR] |= M6811_OR;
282 cpu->ios[M6811_SCSR] |= M6811_RDRF;
283 controller->rx_char = cc;
284 controller->rx_clear_scsr = 0;
289 /* handle idle line detect here. */
293 if (controller->rx_poll_event)
295 hw_event_queue_deschedule (me, controller->rx_poll_event);
296 controller->rx_poll_event = 0;
299 if (cpu->ios[M6811_SCCR2] & M6811_RE)
301 unsigned long clock_cycle;
303 /* Compute CPU clock cycles to wait for the next character. */
304 clock_cycle = controller->data_length * controller->baud_cycle;
306 controller->rx_poll_event = hw_event_queue_schedule (me, clock_cycle,
312 interrupts_update_pending (&cpu->cpu_interrupts);
317 m68hc11sio_tx_poll (struct hw *me, void *data)
320 struct m68hc11sio *controller;
323 controller = hw_data (me);
325 cpu = STATE_CPU (sd, 0);
327 cpu->ios[M6811_SCSR] |= M6811_TDRE;
328 cpu->ios[M6811_SCSR] |= M6811_TC;
330 /* Transmitter is enabled and we have something to send. */
331 if ((cpu->ios[M6811_SCCR2] & M6811_TE) && controller->tx_has_char)
333 cpu->ios[M6811_SCSR] &= ~M6811_TDRE;
334 cpu->ios[M6811_SCSR] &= ~M6811_TC;
335 controller->tx_has_char = 0;
336 switch (controller->backend)
339 dv_sockser_write (sd, controller->tx_char);
343 sim_io_write_stdout (sd, &controller->tx_char, 1);
344 sim_io_flush_stdout (sd);
352 if (controller->tx_poll_event)
354 hw_event_queue_deschedule (me, controller->tx_poll_event);
355 controller->tx_poll_event = 0;
358 if ((cpu->ios[M6811_SCCR2] & M6811_TE)
359 && ((cpu->ios[M6811_SCSR] & M6811_TC) == 0))
361 unsigned long clock_cycle;
363 /* Compute CPU clock cycles to wait for the next character. */
364 clock_cycle = controller->data_length * controller->baud_cycle;
366 controller->tx_poll_event = hw_event_queue_schedule (me, clock_cycle,
371 interrupts_update_pending (&cpu->cpu_interrupts);
374 /* Descriptions of the SIO I/O ports. These descriptions are only used to
375 give information of the SIO device under GDB. */
376 io_reg_desc sccr2_desc[] = {
377 { M6811_TIE, "TIE ", "Transmit Interrupt Enable" },
378 { M6811_TCIE, "TCIE ", "Transmit Complete Interrupt Enable" },
379 { M6811_RIE, "RIE ", "Receive Interrupt Enable" },
380 { M6811_ILIE, "ILIE ", "Idle Line Interrupt Enable" },
381 { M6811_TE, "TE ", "Transmit Enable" },
382 { M6811_RE, "RE ", "Receive Enable" },
383 { M6811_RWU, "RWU ", "Receiver Wake Up" },
384 { M6811_SBK, "SBRK ", "Send Break" },
388 io_reg_desc sccr1_desc[] = {
389 { M6811_R8, "R8 ", "Receive Data bit 8" },
390 { M6811_T8, "T8 ", "Transmit Data bit 8" },
391 { M6811_M, "M ", "SCI Character length (0=8-bits, 1=9-bits)" },
392 { M6811_WAKE, "WAKE ", "Wake up method select (0=idle, 1=addr mark" },
396 io_reg_desc scsr_desc[] = {
397 { M6811_TDRE, "TDRE ", "Transmit Data Register Empty" },
398 { M6811_TC, "TC ", "Transmit Complete" },
399 { M6811_RDRF, "RDRF ", "Receive Data Register Full" },
400 { M6811_IDLE, "IDLE ", "Idle Line Detect" },
401 { M6811_OR, "OR ", "Overrun Error" },
402 { M6811_NF, "NF ", "Noise Flag" },
403 { M6811_FE, "FE ", "Framing Error" },
407 io_reg_desc baud_desc[] = {
408 { M6811_TCLR, "TCLR ", "Clear baud rate (test mode)" },
409 { M6811_SCP1, "SCP1 ", "SCI baud rate prescaler select (SCP1)" },
410 { M6811_SCP0, "SCP0 ", "SCI baud rate prescaler select (SCP0)" },
411 { M6811_RCKB, "RCKB ", "Baur Rate Clock Check (test mode)" },
412 { M6811_SCR2, "SCR2 ", "SCI Baud rate select (SCR2)" },
413 { M6811_SCR1, "SCR1 ", "SCI Baud rate select (SCR1)" },
414 { M6811_SCR0, "SCR0 ", "SCI Baud rate select (SCR0)" },
419 m68hc11sio_info (struct hw *me)
424 struct m68hc11sio *controller;
429 cpu = STATE_CPU (sd, 0);
430 controller = hw_data (me);
432 sim_io_printf (sd, "M68HC11 SIO:\n");
434 base = cpu_get_io_base (cpu);
436 val = cpu->ios[M6811_BAUD];
437 print_io_byte (sd, "BAUD ", baud_desc, val, base + M6811_BAUD);
438 sim_io_printf (sd, " (%ld baud)\n",
439 (cpu->cpu_frequency / 4) / controller->baud_cycle);
441 val = cpu->ios[M6811_SCCR1];
442 print_io_byte (sd, "SCCR1", sccr1_desc, val, base + M6811_SCCR1);
443 sim_io_printf (sd, " (%d bits) (%dN1)\n",
444 controller->data_length, controller->data_length - 2);
446 val = cpu->ios[M6811_SCCR2];
447 print_io_byte (sd, "SCCR2", sccr2_desc, val, base + M6811_SCCR2);
448 sim_io_printf (sd, "\n");
450 val = cpu->ios[M6811_SCSR];
451 print_io_byte (sd, "SCSR ", scsr_desc, val, base + M6811_SCSR);
452 sim_io_printf (sd, "\n");
454 clock_cycle = controller->data_length * controller->baud_cycle;
456 if (controller->tx_poll_event)
461 t = hw_event_remain_time (me, controller->tx_poll_event);
462 n = (clock_cycle - t) / controller->baud_cycle;
463 n = controller->data_length - n;
464 sim_io_printf (sd, " Transmit finished in %s (%d bit%s)\n",
465 cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE),
466 n, (n > 1 ? "s" : ""));
468 if (controller->rx_poll_event)
472 t = hw_event_remain_time (me, controller->rx_poll_event);
473 sim_io_printf (sd, " Receive finished in %s\n",
474 cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE));
480 m68hc11sio_ioctl (struct hw *me,
481 hw_ioctl_request request,
484 m68hc11sio_info (me);
488 /* generic read/write */
491 m68hc11sio_io_read_buffer (struct hw *me,
498 struct m68hc11sio *controller;
502 HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
505 cpu = STATE_CPU (sd, 0);
506 controller = hw_data (me);
511 controller->rx_clear_scsr = cpu->ios[M6811_SCSR]
512 & (M6811_RDRF | M6811_IDLE | M6811_OR | M6811_NF | M6811_FE);
517 val = cpu->ios[base];
521 if (controller->rx_clear_scsr)
523 cpu->ios[M6811_SCSR] &= ~controller->rx_clear_scsr;
525 val = controller->rx_char;
531 *((unsigned8*) dest) = val;
536 m68hc11sio_io_write_buffer (struct hw *me,
543 struct m68hc11sio *controller;
547 HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
550 cpu = STATE_CPU (sd, 0);
551 controller = hw_data (me);
553 val = *((const unsigned8*) source);
561 cpu->ios[M6811_BAUD] = val;
562 switch (val & (M6811_SCP1|M6811_SCP0))
564 case M6811_BAUD_DIV_1:
568 case M6811_BAUD_DIV_3:
572 case M6811_BAUD_DIV_4:
577 case M6811_BAUD_DIV_13:
581 val &= (M6811_SCR2|M6811_SCR1|M6811_SCR0);
582 divisor *= (1 << val);
584 baud = (cpu->cpu_frequency / 4) / divisor;
586 HW_TRACE ((me, "divide rate %ld, baud rate %ld",
589 controller->baud_cycle = divisor;
596 controller->data_length = 11;
598 controller->data_length = 10;
600 cpu->ios[M6811_SCCR1] = val;
605 if ((val & M6811_RE) == 0)
607 val &= ~(M6811_RDRF|M6811_IDLE|M6811_OR|M6811_NF|M6811_NF);
608 val |= (cpu->ios[M6811_SCCR2]
609 & (M6811_RDRF|M6811_IDLE|M6811_OR|M6811_NF|M6811_NF));
610 cpu->ios[M6811_SCCR2] = val;
614 /* Activate reception. */
615 if (controller->rx_poll_event == 0)
619 /* Compute CPU clock cycles to wait for the next character. */
620 clock_cycle = controller->data_length * controller->baud_cycle;
622 controller->rx_poll_event = hw_event_queue_schedule (me, clock_cycle,
626 cpu->ios[M6811_SCCR2] = val;
627 interrupts_update_pending (&cpu->cpu_interrupts);
635 if (!(cpu->ios[M6811_SCSR] & M6811_TDRE))
640 controller->tx_char = val;
641 controller->tx_has_char = 1;
642 if ((cpu->ios[M6811_SCCR2] & M6811_TE)
643 && controller->tx_poll_event == 0)
645 m68hc11sio_tx_poll (me, NULL);
656 const struct hw_descriptor dv_m68hc11sio_descriptor[] = {
657 { "m68hc11sio", m68hc11sio_finish },
658 { "m68hc12sio", m68hc11sio_finish },