1 /* m32r exception, interrupt, and trap (EIT) support
2 Copyright (C) 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #include "targ-vals.h"
24 /* The semantic code invokes this for invalid (unrecognized) instructions. */
27 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
29 SIM_DESC sd = CPU_STATE (current_cpu);
32 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
34 h_bsm_set (current_cpu, h_sm_get (current_cpu));
35 h_bie_set (current_cpu, h_ie_get (current_cpu));
36 h_bcond_set (current_cpu, h_cond_get (current_cpu));
38 h_ie_set (current_cpu, 0);
39 h_cond_set (current_cpu, 0);
41 h_bpc_set (current_cpu, cia);
43 sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
48 sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
51 /* Process an address exception. */
54 m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
55 unsigned int map, int nr_bytes, address_word addr,
56 transfer_type transfer, sim_core_signals sig)
58 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
60 a_m32r_h_cr_set (current_cpu, H_CR_BBPC,
61 a_m32r_h_cr_get (current_cpu, H_CR_BPC));
62 a_m32r_h_bpsw_set (current_cpu, a_m32r_h_psw_get (current_cpu));
64 a_m32r_h_psw_set (current_cpu, a_m32r_h_psw_get (current_cpu) & 0x80);
65 a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
67 sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
71 sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
75 /* Read/write functions for system call interface. */
78 syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
79 unsigned long taddr, char *buf, int bytes)
81 SIM_DESC sd = (SIM_DESC) sc->p1;
82 SIM_CPU *cpu = (SIM_CPU *) sc->p2;
84 return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
88 syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
89 unsigned long taddr, const char *buf, int bytes)
91 SIM_DESC sd = (SIM_DESC) sc->p1;
92 SIM_CPU *cpu = (SIM_CPU *) sc->p2;
94 return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
98 The result is the pc address to continue at.
99 Preprocessing like saving the various registers has already been done. */
102 m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
104 SIM_DESC sd = CPU_STATE (current_cpu);
105 host_callback *cb = STATE_CALLBACK (sd);
107 #ifdef SIM_HAVE_BREAKPOINTS
108 /* Check for breakpoints "owned" by the simulator first, regardless
110 if (num == TRAP_BREAKPOINT)
112 /* First try sim-break.c. If it's a breakpoint the simulator "owns"
113 it doesn't return. Otherwise it returns and let's us try. */
114 sim_handle_breakpoint (sd, current_cpu, pc);
119 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
121 /* The new pc is the trap vector entry.
122 We assume there's a branch there to some handler. */
123 USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
133 CB_SYSCALL_INIT (&s);
134 s.func = a_m32r_h_gr_get (current_cpu, 0);
135 s.arg1 = a_m32r_h_gr_get (current_cpu, 1);
136 s.arg2 = a_m32r_h_gr_get (current_cpu, 2);
137 s.arg3 = a_m32r_h_gr_get (current_cpu, 3);
139 if (s.func == TARGET_SYS_exit)
141 sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
145 s.p2 = (PTR) current_cpu;
146 s.read_mem = syscall_read_mem;
147 s.write_mem = syscall_write_mem;
149 a_m32r_h_gr_set (current_cpu, 2, s.errcode);
150 a_m32r_h_gr_set (current_cpu, 0, s.result);
151 a_m32r_h_gr_set (current_cpu, 1, s.result2);
155 case TRAP_BREAKPOINT:
156 sim_engine_halt (sd, current_cpu, NULL, pc,
157 sim_stopped, SIM_SIGTRAP);
162 USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
167 /* Fake an "rte" insn. */
168 /* FIXME: Should duplicate all of rte processing. */
169 return (pc & -4) + 4;