1 /* m32r exception, interrupt, and trap (EIT) support
2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "sim-syscall.h"
22 #include "targ-vals.h"
24 #define TRAP_FLUSH_CACHE 12
25 /* The semantic code invokes this for invalid (unrecognized) instructions. */
28 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC pc)
30 SIM_DESC sd = CPU_STATE (current_cpu);
33 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
35 h_bsm_set (current_cpu, h_sm_get (current_cpu));
36 h_bie_set (current_cpu, h_ie_get (current_cpu));
37 h_bcond_set (current_cpu, h_cond_get (current_cpu));
39 h_ie_set (current_cpu, 0);
40 h_cond_set (current_cpu, 0);
42 h_bpc_set (current_cpu, cia);
44 sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
49 sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
54 /* Process an address exception. */
57 m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
58 unsigned int map, int nr_bytes, address_word addr,
59 transfer_type transfer, sim_core_signals sig)
61 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
63 m32rbf_h_cr_set (current_cpu, H_CR_BBPC,
64 m32rbf_h_cr_get (current_cpu, H_CR_BPC));
65 switch (MACH_NUM (CPU_MACH (current_cpu)))
68 m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
70 m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
73 m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
75 m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
78 m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
80 m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
86 m32rbf_h_cr_set (current_cpu, H_CR_BPC, cia);
88 sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
92 sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
97 The result is the pc address to continue at.
98 Preprocessing like saving the various registers has already been done. */
101 m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
103 SIM_DESC sd = CPU_STATE (current_cpu);
104 host_callback *cb = STATE_CALLBACK (sd);
106 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
108 /* The new pc is the trap vector entry.
109 We assume there's a branch there to some handler.
110 Use cr5 as EVB (EIT Vector Base) register. */
111 /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
112 USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
120 long result, result2;
123 sim_syscall_multi (current_cpu,
124 m32rbf_h_gr_get (current_cpu, 0),
125 m32rbf_h_gr_get (current_cpu, 1),
126 m32rbf_h_gr_get (current_cpu, 2),
127 m32rbf_h_gr_get (current_cpu, 3),
128 m32rbf_h_gr_get (current_cpu, 4),
129 &result, &result2, &errcode);
131 m32rbf_h_gr_set (current_cpu, 2, errcode);
132 m32rbf_h_gr_set (current_cpu, 0, result);
133 m32rbf_h_gr_set (current_cpu, 1, result2);
137 case TRAP_BREAKPOINT:
138 sim_engine_halt (sd, current_cpu, NULL, pc,
139 sim_stopped, SIM_SIGTRAP);
142 case TRAP_FLUSH_CACHE:
148 /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
149 /* Use cr5 as EVB (EIT Vector Base) register. */
150 USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
155 /* Fake an "rte" insn. */
156 /* FIXME: Should duplicate all of rte processing. */
157 return (pc & -4) + 4;