1 /* m32r exception, interrupt, and trap (EIT) support
2 Copyright (C) 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #include "targ-vals.h"
24 #define TRAP_FLUSH_CACHE 12
25 /* The semantic code invokes this for invalid (unrecognized) instructions.
26 CIA is the address with the invalid insn.
27 VPC is the virtual pc of the following insn. */
30 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
32 SIM_DESC sd = CPU_STATE (current_cpu);
35 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
37 h_bsm_set (current_cpu, h_sm_get (current_cpu));
38 h_bie_set (current_cpu, h_ie_get (current_cpu));
39 h_bcond_set (current_cpu, h_cond_get (current_cpu));
41 h_ie_set (current_cpu, 0);
42 h_cond_set (current_cpu, 0);
44 h_bpc_set (current_cpu, cia);
46 sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
51 sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
55 /* Process an address exception. */
58 m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
59 unsigned int map, int nr_bytes, address_word addr,
60 transfer_type transfer, sim_core_signals sig)
62 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
64 a_m32r_h_cr_set (current_cpu, H_CR_BBPC,
65 a_m32r_h_cr_get (current_cpu, H_CR_BPC));
66 if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R)
68 m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
70 m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
72 else if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32RX)
74 m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
76 m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
80 m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
82 m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
84 a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
86 sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
90 sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
94 /* Read/write functions for system call interface. */
97 syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
98 unsigned long taddr, char *buf, int bytes)
100 SIM_DESC sd = (SIM_DESC) sc->p1;
101 SIM_CPU *cpu = (SIM_CPU *) sc->p2;
103 return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
107 syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
108 unsigned long taddr, const char *buf, int bytes)
110 SIM_DESC sd = (SIM_DESC) sc->p1;
111 SIM_CPU *cpu = (SIM_CPU *) sc->p2;
113 return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
117 The result is the pc address to continue at.
118 Preprocessing like saving the various registers has already been done. */
121 m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
123 SIM_DESC sd = CPU_STATE (current_cpu);
124 host_callback *cb = STATE_CALLBACK (sd);
126 #ifdef SIM_HAVE_BREAKPOINTS
127 /* Check for breakpoints "owned" by the simulator first, regardless
129 if (num == TRAP_BREAKPOINT)
131 /* First try sim-break.c. If it's a breakpoint the simulator "owns"
132 it doesn't return. Otherwise it returns and let's us try. */
133 sim_handle_breakpoint (sd, current_cpu, pc);
138 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
140 /* The new pc is the trap vector entry.
141 We assume there's a branch there to some handler.
142 Use cr5 as EVB (EIT Vector Base) register. */
143 /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
144 USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
154 CB_SYSCALL_INIT (&s);
155 s.func = a_m32r_h_gr_get (current_cpu, 0);
156 s.arg1 = a_m32r_h_gr_get (current_cpu, 1);
157 s.arg2 = a_m32r_h_gr_get (current_cpu, 2);
158 s.arg3 = a_m32r_h_gr_get (current_cpu, 3);
160 if (s.func == TARGET_SYS_exit)
162 sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
166 s.p2 = (PTR) current_cpu;
167 s.read_mem = syscall_read_mem;
168 s.write_mem = syscall_write_mem;
170 a_m32r_h_gr_set (current_cpu, 2, s.errcode);
171 a_m32r_h_gr_set (current_cpu, 0, s.result);
172 a_m32r_h_gr_set (current_cpu, 1, s.result2);
176 case TRAP_BREAKPOINT:
177 sim_engine_halt (sd, current_cpu, NULL, pc,
178 sim_stopped, SIM_SIGTRAP);
181 case TRAP_FLUSH_CACHE:
187 /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
188 /* Use cr5 as EVB (EIT Vector Base) register. */
189 USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
194 /* Fake an "rte" insn. */
195 /* FIXME: Should duplicate all of rte processing. */
196 return (pc & -4) + 4;