1 /* Simulator model support for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #define WANT_CPU m32rxf
26 #define WANT_CPU_M32RXF
30 /* The profiling data is recorded here, but is accessed via the profiling
31 mechanism. After all, this is information for profiling. */
33 #if WITH_PROFILE_MODEL_P
35 /* Model handlers for each insn. */
38 model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg)
40 #define FLD(f) abuf->fields.fmt_add.f
41 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
42 const IDESC * UNUSED idesc = abuf->idesc;
46 int UNUSED insn_referenced = abuf->written;
54 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
61 model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg)
63 #define FLD(f) abuf->fields.fmt_add3.f
64 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
65 const IDESC * UNUSED idesc = abuf->idesc;
69 int UNUSED insn_referenced = abuf->written;
77 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
84 model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg)
86 #define FLD(f) abuf->fields.fmt_add.f
87 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
88 const IDESC * UNUSED idesc = abuf->idesc;
92 int UNUSED insn_referenced = abuf->written;
100 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
107 model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg)
109 #define FLD(f) abuf->fields.fmt_and3.f
110 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
111 const IDESC * UNUSED idesc = abuf->idesc;
115 int UNUSED insn_referenced = abuf->written;
121 referenced |= 1 << 0;
122 referenced |= 1 << 2;
123 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
130 model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg)
132 #define FLD(f) abuf->fields.fmt_add.f
133 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
134 const IDESC * UNUSED idesc = abuf->idesc;
138 int UNUSED insn_referenced = abuf->written;
144 referenced |= 1 << 0;
145 referenced |= 1 << 2;
146 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
153 model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg)
155 #define FLD(f) abuf->fields.fmt_or3.f
156 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
157 const IDESC * UNUSED idesc = abuf->idesc;
161 int UNUSED insn_referenced = abuf->written;
167 referenced |= 1 << 0;
168 referenced |= 1 << 2;
169 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
176 model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg)
178 #define FLD(f) abuf->fields.fmt_add.f
179 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
180 const IDESC * UNUSED idesc = abuf->idesc;
184 int UNUSED insn_referenced = abuf->written;
190 referenced |= 1 << 0;
191 referenced |= 1 << 2;
192 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
199 model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg)
201 #define FLD(f) abuf->fields.fmt_and3.f
202 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
203 const IDESC * UNUSED idesc = abuf->idesc;
207 int UNUSED insn_referenced = abuf->written;
213 referenced |= 1 << 0;
214 referenced |= 1 << 2;
215 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
222 model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg)
224 #define FLD(f) abuf->fields.fmt_addi.f
225 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
226 const IDESC * UNUSED idesc = abuf->idesc;
230 int UNUSED insn_referenced = abuf->written;
236 referenced |= 1 << 0;
237 referenced |= 1 << 2;
238 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
245 model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg)
247 #define FLD(f) abuf->fields.fmt_addv.f
248 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
249 const IDESC * UNUSED idesc = abuf->idesc;
253 int UNUSED insn_referenced = abuf->written;
259 referenced |= 1 << 0;
260 referenced |= 1 << 2;
261 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
268 model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg)
270 #define FLD(f) abuf->fields.fmt_addv3.f
271 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
272 const IDESC * UNUSED idesc = abuf->idesc;
276 int UNUSED insn_referenced = abuf->written;
282 referenced |= 1 << 0;
283 referenced |= 1 << 2;
284 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
291 model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg)
293 #define FLD(f) abuf->fields.fmt_addx.f
294 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
295 const IDESC * UNUSED idesc = abuf->idesc;
299 int UNUSED insn_referenced = abuf->written;
305 referenced |= 1 << 0;
306 referenced |= 1 << 2;
307 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
314 model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg)
316 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
317 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
318 const IDESC * UNUSED idesc = abuf->idesc;
322 int UNUSED insn_referenced = abuf->written;
324 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
325 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
332 model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg)
334 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
335 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
336 const IDESC * UNUSED idesc = abuf->idesc;
340 int UNUSED insn_referenced = abuf->written;
342 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
343 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
350 model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg)
352 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
353 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
354 const IDESC * UNUSED idesc = abuf->idesc;
358 int UNUSED insn_referenced = abuf->written;
360 if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
361 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
365 int UNUSED insn_referenced = abuf->written;
368 src1 = FLD (in_src1);
369 src2 = FLD (in_src2);
370 referenced |= 1 << 0;
371 referenced |= 1 << 1;
372 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
379 model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg)
381 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
382 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
383 const IDESC * UNUSED idesc = abuf->idesc;
387 int UNUSED insn_referenced = abuf->written;
389 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
390 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
394 int UNUSED insn_referenced = abuf->written;
397 src2 = FLD (in_src2);
398 referenced |= 1 << 1;
399 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
406 model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg)
408 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
409 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
410 const IDESC * UNUSED idesc = abuf->idesc;
414 int UNUSED insn_referenced = abuf->written;
416 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
417 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
421 int UNUSED insn_referenced = abuf->written;
424 src2 = FLD (in_src2);
425 referenced |= 1 << 1;
426 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
433 model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg)
435 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
436 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
437 const IDESC * UNUSED idesc = abuf->idesc;
441 int UNUSED insn_referenced = abuf->written;
443 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
444 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
448 int UNUSED insn_referenced = abuf->written;
451 src2 = FLD (in_src2);
452 referenced |= 1 << 1;
453 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
460 model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg)
462 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
463 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
464 const IDESC * UNUSED idesc = abuf->idesc;
468 int UNUSED insn_referenced = abuf->written;
470 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
471 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
475 int UNUSED insn_referenced = abuf->written;
478 src2 = FLD (in_src2);
479 referenced |= 1 << 1;
480 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
487 model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg)
489 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
490 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
491 const IDESC * UNUSED idesc = abuf->idesc;
495 int UNUSED insn_referenced = abuf->written;
497 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
498 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
502 int UNUSED insn_referenced = abuf->written;
505 src2 = FLD (in_src2);
506 referenced |= 1 << 1;
507 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
514 model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg)
516 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
517 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
518 const IDESC * UNUSED idesc = abuf->idesc;
522 int UNUSED insn_referenced = abuf->written;
524 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
525 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
529 int UNUSED insn_referenced = abuf->written;
532 src2 = FLD (in_src2);
533 referenced |= 1 << 1;
534 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
541 model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg)
543 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
544 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
545 const IDESC * UNUSED idesc = abuf->idesc;
549 int UNUSED insn_referenced = abuf->written;
551 referenced |= 1 << 1;
552 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
559 model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg)
561 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
562 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
563 const IDESC * UNUSED idesc = abuf->idesc;
567 int UNUSED insn_referenced = abuf->written;
569 referenced |= 1 << 1;
570 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
577 model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
579 #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
580 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
581 const IDESC * UNUSED idesc = abuf->idesc;
585 int UNUSED insn_referenced = abuf->written;
587 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
588 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
595 model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
597 #define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
598 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
599 const IDESC * UNUSED idesc = abuf->idesc;
603 int UNUSED insn_referenced = abuf->written;
605 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
606 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
613 model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
615 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
616 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
617 const IDESC * UNUSED idesc = abuf->idesc;
621 int UNUSED insn_referenced = abuf->written;
623 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
624 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
631 model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
633 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
634 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
635 const IDESC * UNUSED idesc = abuf->idesc;
639 int UNUSED insn_referenced = abuf->written;
641 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
642 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
649 model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg)
651 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
652 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
653 const IDESC * UNUSED idesc = abuf->idesc;
657 int UNUSED insn_referenced = abuf->written;
659 if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
660 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
664 int UNUSED insn_referenced = abuf->written;
667 src1 = FLD (in_src1);
668 src2 = FLD (in_src2);
669 referenced |= 1 << 0;
670 referenced |= 1 << 1;
671 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
678 model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg)
680 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
681 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
682 const IDESC * UNUSED idesc = abuf->idesc;
686 int UNUSED insn_referenced = abuf->written;
688 referenced |= 1 << 1;
689 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
696 model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg)
698 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
699 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
700 const IDESC * UNUSED idesc = abuf->idesc;
704 int UNUSED insn_referenced = abuf->written;
706 referenced |= 1 << 1;
707 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
714 model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
716 #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
717 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
718 const IDESC * UNUSED idesc = abuf->idesc;
722 int UNUSED insn_referenced = abuf->written;
724 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
725 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
732 model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
734 #define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
735 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
736 const IDESC * UNUSED idesc = abuf->idesc;
740 int UNUSED insn_referenced = abuf->written;
742 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
743 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
750 model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg)
752 #define FLD(f) abuf->fields.fmt_cmp.f
753 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
754 const IDESC * UNUSED idesc = abuf->idesc;
758 int UNUSED insn_referenced = abuf->written;
761 src1 = FLD (in_src1);
762 src2 = FLD (in_src2);
763 referenced |= 1 << 0;
764 referenced |= 1 << 1;
765 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
772 model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg)
774 #define FLD(f) abuf->fields.fmt_cmpi.f
775 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
776 const IDESC * UNUSED idesc = abuf->idesc;
780 int UNUSED insn_referenced = abuf->written;
783 src2 = FLD (in_src2);
784 referenced |= 1 << 1;
785 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
792 model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg)
794 #define FLD(f) abuf->fields.fmt_cmp.f
795 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
796 const IDESC * UNUSED idesc = abuf->idesc;
800 int UNUSED insn_referenced = abuf->written;
803 src1 = FLD (in_src1);
804 src2 = FLD (in_src2);
805 referenced |= 1 << 0;
806 referenced |= 1 << 1;
807 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
814 model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg)
816 #define FLD(f) abuf->fields.fmt_cmpi.f
817 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
818 const IDESC * UNUSED idesc = abuf->idesc;
822 int UNUSED insn_referenced = abuf->written;
825 src2 = FLD (in_src2);
826 referenced |= 1 << 1;
827 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
834 model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
836 #define FLD(f) abuf->fields.fmt_cmp.f
837 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
838 const IDESC * UNUSED idesc = abuf->idesc;
842 int UNUSED insn_referenced = abuf->written;
845 src1 = FLD (in_src1);
846 src2 = FLD (in_src2);
847 referenced |= 1 << 0;
848 referenced |= 1 << 1;
849 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
856 model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg)
858 #define FLD(f) abuf->fields.fmt_cmpz.f
859 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
860 const IDESC * UNUSED idesc = abuf->idesc;
864 int UNUSED insn_referenced = abuf->written;
867 src2 = FLD (in_src2);
868 referenced |= 1 << 1;
869 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
876 model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg)
878 #define FLD(f) abuf->fields.fmt_div.f
879 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
880 const IDESC * UNUSED idesc = abuf->idesc;
884 int UNUSED insn_referenced = abuf->written;
890 referenced |= 1 << 0;
891 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
892 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
899 model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg)
901 #define FLD(f) abuf->fields.fmt_div.f
902 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
903 const IDESC * UNUSED idesc = abuf->idesc;
907 int UNUSED insn_referenced = abuf->written;
913 referenced |= 1 << 0;
914 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
915 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
922 model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg)
924 #define FLD(f) abuf->fields.fmt_div.f
925 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
926 const IDESC * UNUSED idesc = abuf->idesc;
930 int UNUSED insn_referenced = abuf->written;
936 referenced |= 1 << 0;
937 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
938 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
945 model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg)
947 #define FLD(f) abuf->fields.fmt_div.f
948 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
949 const IDESC * UNUSED idesc = abuf->idesc;
953 int UNUSED insn_referenced = abuf->written;
959 referenced |= 1 << 0;
960 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
961 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
968 model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg)
970 #define FLD(f) abuf->fields.fmt_div.f
971 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
972 const IDESC * UNUSED idesc = abuf->idesc;
976 int UNUSED insn_referenced = abuf->written;
982 referenced |= 1 << 0;
983 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
984 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
991 model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg)
993 #define FLD(f) abuf->fields.cti.fields.fmt_jc.f
994 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
995 const IDESC * UNUSED idesc = abuf->idesc;
999 int UNUSED insn_referenced = abuf->written;
1002 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1003 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
1004 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
1011 model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg)
1013 #define FLD(f) abuf->fields.cti.fields.fmt_jc.f
1014 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1015 const IDESC * UNUSED idesc = abuf->idesc;
1019 int UNUSED insn_referenced = abuf->written;
1022 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1023 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
1024 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
1031 model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg)
1033 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
1034 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1035 const IDESC * UNUSED idesc = abuf->idesc;
1039 int UNUSED insn_referenced = abuf->written;
1042 referenced |= 1 << 0;
1043 referenced |= 1 << 1;
1044 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
1051 model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg)
1053 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
1054 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1055 const IDESC * UNUSED idesc = abuf->idesc;
1059 int UNUSED insn_referenced = abuf->written;
1062 referenced |= 1 << 0;
1063 referenced |= 1 << 1;
1064 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr);
1071 model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg)
1073 #define FLD(f) abuf->fields.fmt_ld.f
1074 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1075 const IDESC * UNUSED idesc = abuf->idesc;
1079 int UNUSED insn_referenced = abuf->written;
1084 referenced |= 1 << 0;
1085 referenced |= 1 << 1;
1086 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1093 model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg)
1095 #define FLD(f) abuf->fields.fmt_ld_d.f
1096 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1097 const IDESC * UNUSED idesc = abuf->idesc;
1101 int UNUSED insn_referenced = abuf->written;
1106 referenced |= 1 << 0;
1107 referenced |= 1 << 1;
1108 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1115 model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg)
1117 #define FLD(f) abuf->fields.fmt_ldb.f
1118 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1119 const IDESC * UNUSED idesc = abuf->idesc;
1123 int UNUSED insn_referenced = abuf->written;
1128 referenced |= 1 << 0;
1129 referenced |= 1 << 1;
1130 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1137 model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
1139 #define FLD(f) abuf->fields.fmt_ldb_d.f
1140 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1141 const IDESC * UNUSED idesc = abuf->idesc;
1145 int UNUSED insn_referenced = abuf->written;
1150 referenced |= 1 << 0;
1151 referenced |= 1 << 1;
1152 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1159 model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg)
1161 #define FLD(f) abuf->fields.fmt_ldh.f
1162 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1163 const IDESC * UNUSED idesc = abuf->idesc;
1167 int UNUSED insn_referenced = abuf->written;
1172 referenced |= 1 << 0;
1173 referenced |= 1 << 1;
1174 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1181 model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
1183 #define FLD(f) abuf->fields.fmt_ldh_d.f
1184 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1185 const IDESC * UNUSED idesc = abuf->idesc;
1189 int UNUSED insn_referenced = abuf->written;
1194 referenced |= 1 << 0;
1195 referenced |= 1 << 1;
1196 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1203 model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg)
1205 #define FLD(f) abuf->fields.fmt_ldb.f
1206 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1207 const IDESC * UNUSED idesc = abuf->idesc;
1211 int UNUSED insn_referenced = abuf->written;
1216 referenced |= 1 << 0;
1217 referenced |= 1 << 1;
1218 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1225 model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
1227 #define FLD(f) abuf->fields.fmt_ldb_d.f
1228 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1229 const IDESC * UNUSED idesc = abuf->idesc;
1233 int UNUSED insn_referenced = abuf->written;
1238 referenced |= 1 << 0;
1239 referenced |= 1 << 1;
1240 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1247 model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg)
1249 #define FLD(f) abuf->fields.fmt_ldh.f
1250 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1251 const IDESC * UNUSED idesc = abuf->idesc;
1255 int UNUSED insn_referenced = abuf->written;
1260 referenced |= 1 << 0;
1261 referenced |= 1 << 1;
1262 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1269 model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
1271 #define FLD(f) abuf->fields.fmt_ldh_d.f
1272 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1273 const IDESC * UNUSED idesc = abuf->idesc;
1277 int UNUSED insn_referenced = abuf->written;
1282 referenced |= 1 << 0;
1283 referenced |= 1 << 1;
1284 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1291 model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
1293 #define FLD(f) abuf->fields.fmt_ld_plus.f
1294 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1295 const IDESC * UNUSED idesc = abuf->idesc;
1299 int UNUSED insn_referenced = abuf->written;
1304 referenced |= 1 << 0;
1305 referenced |= 1 << 1;
1306 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1310 int UNUSED insn_referenced = abuf->written;
1316 referenced |= 1 << 0;
1317 referenced |= 1 << 2;
1318 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
1325 model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg)
1327 #define FLD(f) abuf->fields.fmt_ld24.f
1328 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1329 const IDESC * UNUSED idesc = abuf->idesc;
1333 int UNUSED insn_referenced = abuf->written;
1338 referenced |= 1 << 2;
1339 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1346 model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
1348 #define FLD(f) abuf->fields.fmt_ldi8.f
1349 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1350 const IDESC * UNUSED idesc = abuf->idesc;
1354 int UNUSED insn_referenced = abuf->written;
1359 referenced |= 1 << 2;
1360 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1367 model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
1369 #define FLD(f) abuf->fields.fmt_ldi16.f
1370 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1371 const IDESC * UNUSED idesc = abuf->idesc;
1375 int UNUSED insn_referenced = abuf->written;
1380 referenced |= 1 << 2;
1381 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1388 model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg)
1390 #define FLD(f) abuf->fields.fmt_lock.f
1391 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1392 const IDESC * UNUSED idesc = abuf->idesc;
1396 int UNUSED insn_referenced = abuf->written;
1401 referenced |= 1 << 0;
1402 referenced |= 1 << 1;
1403 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1410 model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg)
1412 #define FLD(f) abuf->fields.fmt_machi_a.f
1413 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1414 const IDESC * UNUSED idesc = abuf->idesc;
1418 int UNUSED insn_referenced = abuf->written;
1421 src1 = FLD (in_src1);
1422 src2 = FLD (in_src2);
1423 referenced |= 1 << 0;
1424 referenced |= 1 << 1;
1425 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1432 model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
1434 #define FLD(f) abuf->fields.fmt_machi_a.f
1435 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1436 const IDESC * UNUSED idesc = abuf->idesc;
1440 int UNUSED insn_referenced = abuf->written;
1443 src1 = FLD (in_src1);
1444 src2 = FLD (in_src2);
1445 referenced |= 1 << 0;
1446 referenced |= 1 << 1;
1447 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1454 model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1456 #define FLD(f) abuf->fields.fmt_machi_a.f
1457 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1458 const IDESC * UNUSED idesc = abuf->idesc;
1462 int UNUSED insn_referenced = abuf->written;
1465 src1 = FLD (in_src1);
1466 src2 = FLD (in_src2);
1467 referenced |= 1 << 0;
1468 referenced |= 1 << 1;
1469 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1476 model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1478 #define FLD(f) abuf->fields.fmt_machi_a.f
1479 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1480 const IDESC * UNUSED idesc = abuf->idesc;
1484 int UNUSED insn_referenced = abuf->written;
1487 src1 = FLD (in_src1);
1488 src2 = FLD (in_src2);
1489 referenced |= 1 << 0;
1490 referenced |= 1 << 1;
1491 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1498 model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg)
1500 #define FLD(f) abuf->fields.fmt_add.f
1501 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1502 const IDESC * UNUSED idesc = abuf->idesc;
1506 int UNUSED insn_referenced = abuf->written;
1512 referenced |= 1 << 0;
1513 referenced |= 1 << 2;
1514 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1521 model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
1523 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1524 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1525 const IDESC * UNUSED idesc = abuf->idesc;
1529 int UNUSED insn_referenced = abuf->written;
1532 src1 = FLD (in_src1);
1533 src2 = FLD (in_src2);
1534 referenced |= 1 << 0;
1535 referenced |= 1 << 1;
1536 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1543 model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
1545 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1546 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1547 const IDESC * UNUSED idesc = abuf->idesc;
1551 int UNUSED insn_referenced = abuf->written;
1554 src1 = FLD (in_src1);
1555 src2 = FLD (in_src2);
1556 referenced |= 1 << 0;
1557 referenced |= 1 << 1;
1558 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1565 model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1567 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1568 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1569 const IDESC * UNUSED idesc = abuf->idesc;
1573 int UNUSED insn_referenced = abuf->written;
1576 src1 = FLD (in_src1);
1577 src2 = FLD (in_src2);
1578 referenced |= 1 << 0;
1579 referenced |= 1 << 1;
1580 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1587 model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1589 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1590 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1591 const IDESC * UNUSED idesc = abuf->idesc;
1595 int UNUSED insn_referenced = abuf->written;
1598 src1 = FLD (in_src1);
1599 src2 = FLD (in_src2);
1600 referenced |= 1 << 0;
1601 referenced |= 1 << 1;
1602 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1609 model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg)
1611 #define FLD(f) abuf->fields.fmt_mv.f
1612 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1613 const IDESC * UNUSED idesc = abuf->idesc;
1617 int UNUSED insn_referenced = abuf->written;
1623 referenced |= 1 << 0;
1624 referenced |= 1 << 2;
1625 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1632 model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
1634 #define FLD(f) abuf->fields.fmt_mvfachi_a.f
1635 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1636 const IDESC * UNUSED idesc = abuf->idesc;
1640 int UNUSED insn_referenced = abuf->written;
1645 referenced |= 1 << 2;
1646 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1653 model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1655 #define FLD(f) abuf->fields.fmt_mvfachi_a.f
1656 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1657 const IDESC * UNUSED idesc = abuf->idesc;
1661 int UNUSED insn_referenced = abuf->written;
1666 referenced |= 1 << 2;
1667 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1674 model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
1676 #define FLD(f) abuf->fields.fmt_mvfachi_a.f
1677 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1678 const IDESC * UNUSED idesc = abuf->idesc;
1682 int UNUSED insn_referenced = abuf->written;
1687 referenced |= 1 << 2;
1688 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1695 model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg)
1697 #define FLD(f) abuf->fields.fmt_mvfc.f
1698 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1699 const IDESC * UNUSED idesc = abuf->idesc;
1703 int UNUSED insn_referenced = abuf->written;
1708 referenced |= 1 << 2;
1709 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1716 model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
1718 #define FLD(f) abuf->fields.fmt_mvtachi_a.f
1719 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1720 const IDESC * UNUSED idesc = abuf->idesc;
1724 int UNUSED insn_referenced = abuf->written;
1729 referenced |= 1 << 0;
1730 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1737 model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1739 #define FLD(f) abuf->fields.fmt_mvtachi_a.f
1740 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1741 const IDESC * UNUSED idesc = abuf->idesc;
1745 int UNUSED insn_referenced = abuf->written;
1750 referenced |= 1 << 0;
1751 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1758 model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg)
1760 #define FLD(f) abuf->fields.fmt_mvtc.f
1761 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1762 const IDESC * UNUSED idesc = abuf->idesc;
1766 int UNUSED insn_referenced = abuf->written;
1771 referenced |= 1 << 0;
1772 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1779 model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
1781 #define FLD(f) abuf->fields.fmt_mv.f
1782 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1783 const IDESC * UNUSED idesc = abuf->idesc;
1787 int UNUSED insn_referenced = abuf->written;
1793 referenced |= 1 << 0;
1794 referenced |= 1 << 2;
1795 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1802 model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
1804 #define FLD(f) abuf->fields.fmt_nop.f
1805 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1806 const IDESC * UNUSED idesc = abuf->idesc;
1810 int UNUSED insn_referenced = abuf->written;
1814 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1821 model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg)
1823 #define FLD(f) abuf->fields.fmt_mv.f
1824 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1825 const IDESC * UNUSED idesc = abuf->idesc;
1829 int UNUSED insn_referenced = abuf->written;
1835 referenced |= 1 << 0;
1836 referenced |= 1 << 2;
1837 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1844 model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
1846 #define FLD(f) abuf->fields.fmt_rac_dsi.f
1847 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1848 const IDESC * UNUSED idesc = abuf->idesc;
1852 int UNUSED insn_referenced = abuf->written;
1855 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1862 model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
1864 #define FLD(f) abuf->fields.fmt_rac_dsi.f
1865 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1866 const IDESC * UNUSED idesc = abuf->idesc;
1870 int UNUSED insn_referenced = abuf->written;
1873 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1880 model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
1882 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
1883 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1884 const IDESC * UNUSED idesc = abuf->idesc;
1888 int UNUSED insn_referenced = abuf->written;
1892 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1899 model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg)
1901 #define FLD(f) abuf->fields.fmt_seth.f
1902 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1903 const IDESC * UNUSED idesc = abuf->idesc;
1907 int UNUSED insn_referenced = abuf->written;
1912 referenced |= 1 << 2;
1913 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1920 model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg)
1922 #define FLD(f) abuf->fields.fmt_add.f
1923 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1924 const IDESC * UNUSED idesc = abuf->idesc;
1928 int UNUSED insn_referenced = abuf->written;
1934 referenced |= 1 << 0;
1935 referenced |= 1 << 2;
1936 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1943 model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg)
1945 #define FLD(f) abuf->fields.fmt_sll3.f
1946 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1947 const IDESC * UNUSED idesc = abuf->idesc;
1951 int UNUSED insn_referenced = abuf->written;
1957 referenced |= 1 << 0;
1958 referenced |= 1 << 2;
1959 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1966 model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg)
1968 #define FLD(f) abuf->fields.fmt_slli.f
1969 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1970 const IDESC * UNUSED idesc = abuf->idesc;
1974 int UNUSED insn_referenced = abuf->written;
1979 referenced |= 1 << 2;
1980 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1987 model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg)
1989 #define FLD(f) abuf->fields.fmt_add.f
1990 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1991 const IDESC * UNUSED idesc = abuf->idesc;
1995 int UNUSED insn_referenced = abuf->written;
2001 referenced |= 1 << 0;
2002 referenced |= 1 << 2;
2003 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2010 model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg)
2012 #define FLD(f) abuf->fields.fmt_sll3.f
2013 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2014 const IDESC * UNUSED idesc = abuf->idesc;
2018 int UNUSED insn_referenced = abuf->written;
2024 referenced |= 1 << 0;
2025 referenced |= 1 << 2;
2026 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2033 model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg)
2035 #define FLD(f) abuf->fields.fmt_slli.f
2036 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2037 const IDESC * UNUSED idesc = abuf->idesc;
2041 int UNUSED insn_referenced = abuf->written;
2046 referenced |= 1 << 2;
2047 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2054 model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg)
2056 #define FLD(f) abuf->fields.fmt_add.f
2057 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2058 const IDESC * UNUSED idesc = abuf->idesc;
2062 int UNUSED insn_referenced = abuf->written;
2068 referenced |= 1 << 0;
2069 referenced |= 1 << 2;
2070 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2077 model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg)
2079 #define FLD(f) abuf->fields.fmt_sll3.f
2080 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2081 const IDESC * UNUSED idesc = abuf->idesc;
2085 int UNUSED insn_referenced = abuf->written;
2091 referenced |= 1 << 0;
2092 referenced |= 1 << 2;
2093 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2100 model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg)
2102 #define FLD(f) abuf->fields.fmt_slli.f
2103 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2104 const IDESC * UNUSED idesc = abuf->idesc;
2108 int UNUSED insn_referenced = abuf->written;
2113 referenced |= 1 << 2;
2114 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2121 model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg)
2123 #define FLD(f) abuf->fields.fmt_st.f
2124 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2125 const IDESC * UNUSED idesc = abuf->idesc;
2129 int UNUSED insn_referenced = abuf->written;
2132 src1 = FLD (in_src1);
2133 src2 = FLD (in_src2);
2134 referenced |= 1 << 0;
2135 referenced |= 1 << 1;
2136 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2143 model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg)
2145 #define FLD(f) abuf->fields.fmt_st_d.f
2146 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2147 const IDESC * UNUSED idesc = abuf->idesc;
2151 int UNUSED insn_referenced = abuf->written;
2154 src1 = FLD (in_src1);
2155 src2 = FLD (in_src2);
2156 referenced |= 1 << 0;
2157 referenced |= 1 << 1;
2158 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2165 model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg)
2167 #define FLD(f) abuf->fields.fmt_stb.f
2168 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2169 const IDESC * UNUSED idesc = abuf->idesc;
2173 int UNUSED insn_referenced = abuf->written;
2176 src1 = FLD (in_src1);
2177 src2 = FLD (in_src2);
2178 referenced |= 1 << 0;
2179 referenced |= 1 << 1;
2180 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2187 model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg)
2189 #define FLD(f) abuf->fields.fmt_stb_d.f
2190 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2191 const IDESC * UNUSED idesc = abuf->idesc;
2195 int UNUSED insn_referenced = abuf->written;
2198 src1 = FLD (in_src1);
2199 src2 = FLD (in_src2);
2200 referenced |= 1 << 0;
2201 referenced |= 1 << 1;
2202 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2209 model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg)
2211 #define FLD(f) abuf->fields.fmt_sth.f
2212 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2213 const IDESC * UNUSED idesc = abuf->idesc;
2217 int UNUSED insn_referenced = abuf->written;
2220 src1 = FLD (in_src1);
2221 src2 = FLD (in_src2);
2222 referenced |= 1 << 0;
2223 referenced |= 1 << 1;
2224 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2231 model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg)
2233 #define FLD(f) abuf->fields.fmt_sth_d.f
2234 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2235 const IDESC * UNUSED idesc = abuf->idesc;
2239 int UNUSED insn_referenced = abuf->written;
2242 src1 = FLD (in_src1);
2243 src2 = FLD (in_src2);
2244 referenced |= 1 << 0;
2245 referenced |= 1 << 1;
2246 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2253 model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg)
2255 #define FLD(f) abuf->fields.fmt_st_plus.f
2256 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2257 const IDESC * UNUSED idesc = abuf->idesc;
2261 int UNUSED insn_referenced = abuf->written;
2264 src1 = FLD (in_src1);
2265 src2 = FLD (in_src2);
2266 referenced |= 1 << 0;
2267 referenced |= 1 << 1;
2268 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2272 int UNUSED insn_referenced = abuf->written;
2276 dr = FLD (out_src2);
2278 referenced |= 1 << 0;
2279 referenced |= 1 << 2;
2280 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
2287 model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg)
2289 #define FLD(f) abuf->fields.fmt_st_plus.f
2290 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2291 const IDESC * UNUSED idesc = abuf->idesc;
2295 int UNUSED insn_referenced = abuf->written;
2298 src1 = FLD (in_src1);
2299 src2 = FLD (in_src2);
2300 referenced |= 1 << 0;
2301 referenced |= 1 << 1;
2302 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2306 int UNUSED insn_referenced = abuf->written;
2310 dr = FLD (out_src2);
2312 referenced |= 1 << 0;
2313 referenced |= 1 << 2;
2314 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
2321 model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg)
2323 #define FLD(f) abuf->fields.fmt_add.f
2324 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2325 const IDESC * UNUSED idesc = abuf->idesc;
2329 int UNUSED insn_referenced = abuf->written;
2335 referenced |= 1 << 0;
2336 referenced |= 1 << 2;
2337 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2344 model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg)
2346 #define FLD(f) abuf->fields.fmt_addv.f
2347 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2348 const IDESC * UNUSED idesc = abuf->idesc;
2352 int UNUSED insn_referenced = abuf->written;
2358 referenced |= 1 << 0;
2359 referenced |= 1 << 2;
2360 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2367 model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg)
2369 #define FLD(f) abuf->fields.fmt_addx.f
2370 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2371 const IDESC * UNUSED idesc = abuf->idesc;
2375 int UNUSED insn_referenced = abuf->written;
2381 referenced |= 1 << 0;
2382 referenced |= 1 << 2;
2383 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2390 model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg)
2392 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
2393 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2394 const IDESC * UNUSED idesc = abuf->idesc;
2398 int UNUSED insn_referenced = abuf->written;
2402 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2409 model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg)
2411 #define FLD(f) abuf->fields.fmt_unlock.f
2412 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2413 const IDESC * UNUSED idesc = abuf->idesc;
2417 int UNUSED insn_referenced = abuf->written;
2420 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr);
2427 model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg)
2429 #define FLD(f) abuf->fields.fmt_satb.f
2430 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2431 const IDESC * UNUSED idesc = abuf->idesc;
2435 int UNUSED insn_referenced = abuf->written;
2441 referenced |= 1 << 0;
2442 referenced |= 1 << 2;
2443 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2450 model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg)
2452 #define FLD(f) abuf->fields.fmt_satb.f
2453 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2454 const IDESC * UNUSED idesc = abuf->idesc;
2458 int UNUSED insn_referenced = abuf->written;
2464 referenced |= 1 << 0;
2465 referenced |= 1 << 2;
2466 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2473 model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg)
2475 #define FLD(f) abuf->fields.fmt_sat.f
2476 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2477 const IDESC * UNUSED idesc = abuf->idesc;
2481 int UNUSED insn_referenced = abuf->written;
2487 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
2488 referenced |= 1 << 2;
2489 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2496 model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
2498 #define FLD(f) abuf->fields.fmt_cmpz.f
2499 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2500 const IDESC * UNUSED idesc = abuf->idesc;
2504 int UNUSED insn_referenced = abuf->written;
2507 src2 = FLD (in_src2);
2508 referenced |= 1 << 1;
2509 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
2516 model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
2518 #define FLD(f) abuf->fields.fmt_sadd.f
2519 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2520 const IDESC * UNUSED idesc = abuf->idesc;
2524 int UNUSED insn_referenced = abuf->written;
2527 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
2534 model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
2536 #define FLD(f) abuf->fields.fmt_macwu1.f
2537 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2538 const IDESC * UNUSED idesc = abuf->idesc;
2542 int UNUSED insn_referenced = abuf->written;
2545 src1 = FLD (in_src1);
2546 src2 = FLD (in_src2);
2547 referenced |= 1 << 0;
2548 referenced |= 1 << 1;
2549 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
2556 model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg)
2558 #define FLD(f) abuf->fields.fmt_msblo.f
2559 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2560 const IDESC * UNUSED idesc = abuf->idesc;
2564 int UNUSED insn_referenced = abuf->written;
2567 src1 = FLD (in_src1);
2568 src2 = FLD (in_src2);
2569 referenced |= 1 << 0;
2570 referenced |= 1 << 1;
2571 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
2578 model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
2580 #define FLD(f) abuf->fields.fmt_mulwu1.f
2581 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2582 const IDESC * UNUSED idesc = abuf->idesc;
2586 int UNUSED insn_referenced = abuf->written;
2589 src1 = FLD (in_src1);
2590 src2 = FLD (in_src2);
2591 referenced |= 1 << 0;
2592 referenced |= 1 << 1;
2593 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
2600 model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
2602 #define FLD(f) abuf->fields.fmt_macwu1.f
2603 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2604 const IDESC * UNUSED idesc = abuf->idesc;
2608 int UNUSED insn_referenced = abuf->written;
2611 src1 = FLD (in_src1);
2612 src2 = FLD (in_src2);
2613 referenced |= 1 << 0;
2614 referenced |= 1 << 1;
2615 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
2622 model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
2624 #define FLD(f) abuf->fields.cti.fields.fmt_sc.f
2625 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2626 const IDESC * UNUSED idesc = abuf->idesc;
2630 int UNUSED insn_referenced = abuf->written;
2634 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2641 model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
2643 #define FLD(f) abuf->fields.cti.fields.fmt_sc.f
2644 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2645 const IDESC * UNUSED idesc = abuf->idesc;
2649 int UNUSED insn_referenced = abuf->written;
2653 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2659 /* We assume UNIT_NONE == 0 because the tables don't always terminate
2662 /* Model timing data for `m32rx'. */
2664 static const INSN_TIMING m32rx_timing[] = {
2665 { M32RXF_INSN_X_INVALID, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2666 { M32RXF_INSN_X_AFTER, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2667 { M32RXF_INSN_X_BEFORE, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2668 { M32RXF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2669 { M32RXF_INSN_X_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2670 { M32RXF_INSN_X_BEGIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2671 { M32RXF_INSN_ADD, model_m32rx_add, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2672 { M32RXF_INSN_ADD3, model_m32rx_add3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2673 { M32RXF_INSN_AND, model_m32rx_and, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2674 { M32RXF_INSN_AND3, model_m32rx_and3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2675 { M32RXF_INSN_OR, model_m32rx_or, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2676 { M32RXF_INSN_OR3, model_m32rx_or3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2677 { M32RXF_INSN_XOR, model_m32rx_xor, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2678 { M32RXF_INSN_XOR3, model_m32rx_xor3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2679 { M32RXF_INSN_ADDI, model_m32rx_addi, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2680 { M32RXF_INSN_ADDV, model_m32rx_addv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2681 { M32RXF_INSN_ADDV3, model_m32rx_addv3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2682 { M32RXF_INSN_ADDX, model_m32rx_addx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2683 { M32RXF_INSN_BC8, model_m32rx_bc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2684 { M32RXF_INSN_BC24, model_m32rx_bc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2685 { M32RXF_INSN_BEQ, model_m32rx_beq, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2686 { M32RXF_INSN_BEQZ, model_m32rx_beqz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2687 { M32RXF_INSN_BGEZ, model_m32rx_bgez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2688 { M32RXF_INSN_BGTZ, model_m32rx_bgtz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2689 { M32RXF_INSN_BLEZ, model_m32rx_blez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2690 { M32RXF_INSN_BLTZ, model_m32rx_bltz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2691 { M32RXF_INSN_BNEZ, model_m32rx_bnez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2692 { M32RXF_INSN_BL8, model_m32rx_bl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2693 { M32RXF_INSN_BL24, model_m32rx_bl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2694 { M32RXF_INSN_BCL8, model_m32rx_bcl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2695 { M32RXF_INSN_BCL24, model_m32rx_bcl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2696 { M32RXF_INSN_BNC8, model_m32rx_bnc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2697 { M32RXF_INSN_BNC24, model_m32rx_bnc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2698 { M32RXF_INSN_BNE, model_m32rx_bne, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2699 { M32RXF_INSN_BRA8, model_m32rx_bra8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2700 { M32RXF_INSN_BRA24, model_m32rx_bra24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2701 { M32RXF_INSN_BNCL8, model_m32rx_bncl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2702 { M32RXF_INSN_BNCL24, model_m32rx_bncl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2703 { M32RXF_INSN_CMP, model_m32rx_cmp, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2704 { M32RXF_INSN_CMPI, model_m32rx_cmpi, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2705 { M32RXF_INSN_CMPU, model_m32rx_cmpu, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2706 { M32RXF_INSN_CMPUI, model_m32rx_cmpui, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2707 { M32RXF_INSN_CMPEQ, model_m32rx_cmpeq, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2708 { M32RXF_INSN_CMPZ, model_m32rx_cmpz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2709 { M32RXF_INSN_DIV, model_m32rx_div, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2710 { M32RXF_INSN_DIVU, model_m32rx_divu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2711 { M32RXF_INSN_REM, model_m32rx_rem, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2712 { M32RXF_INSN_REMU, model_m32rx_remu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2713 { M32RXF_INSN_DIVH, model_m32rx_divh, { { (int) UNIT_M32RX_U_EXEC, 1, 21 } } },
2714 { M32RXF_INSN_JC, model_m32rx_jc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2715 { M32RXF_INSN_JNC, model_m32rx_jnc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2716 { M32RXF_INSN_JL, model_m32rx_jl, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2717 { M32RXF_INSN_JMP, model_m32rx_jmp, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2718 { M32RXF_INSN_LD, model_m32rx_ld, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2719 { M32RXF_INSN_LD_D, model_m32rx_ld_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2720 { M32RXF_INSN_LDB, model_m32rx_ldb, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2721 { M32RXF_INSN_LDB_D, model_m32rx_ldb_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2722 { M32RXF_INSN_LDH, model_m32rx_ldh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2723 { M32RXF_INSN_LDH_D, model_m32rx_ldh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2724 { M32RXF_INSN_LDUB, model_m32rx_ldub, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2725 { M32RXF_INSN_LDUB_D, model_m32rx_ldub_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2726 { M32RXF_INSN_LDUH, model_m32rx_lduh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2727 { M32RXF_INSN_LDUH_D, model_m32rx_lduh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2728 { M32RXF_INSN_LD_PLUS, model_m32rx_ld_plus, { { (int) UNIT_M32RX_U_LOAD, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2729 { M32RXF_INSN_LD24, model_m32rx_ld24, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2730 { M32RXF_INSN_LDI8, model_m32rx_ldi8, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2731 { M32RXF_INSN_LDI16, model_m32rx_ldi16, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2732 { M32RXF_INSN_LOCK, model_m32rx_lock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2733 { M32RXF_INSN_MACHI_A, model_m32rx_machi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2734 { M32RXF_INSN_MACLO_A, model_m32rx_maclo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2735 { M32RXF_INSN_MACWHI_A, model_m32rx_macwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2736 { M32RXF_INSN_MACWLO_A, model_m32rx_macwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2737 { M32RXF_INSN_MUL, model_m32rx_mul, { { (int) UNIT_M32RX_U_EXEC, 1, 4 } } },
2738 { M32RXF_INSN_MULHI_A, model_m32rx_mulhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2739 { M32RXF_INSN_MULLO_A, model_m32rx_mullo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2740 { M32RXF_INSN_MULWHI_A, model_m32rx_mulwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2741 { M32RXF_INSN_MULWLO_A, model_m32rx_mulwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2742 { M32RXF_INSN_MV, model_m32rx_mv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2743 { M32RXF_INSN_MVFACHI_A, model_m32rx_mvfachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2744 { M32RXF_INSN_MVFACLO_A, model_m32rx_mvfaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2745 { M32RXF_INSN_MVFACMI_A, model_m32rx_mvfacmi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2746 { M32RXF_INSN_MVFC, model_m32rx_mvfc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2747 { M32RXF_INSN_MVTACHI_A, model_m32rx_mvtachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2748 { M32RXF_INSN_MVTACLO_A, model_m32rx_mvtaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2749 { M32RXF_INSN_MVTC, model_m32rx_mvtc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2750 { M32RXF_INSN_NEG, model_m32rx_neg, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2751 { M32RXF_INSN_NOP, model_m32rx_nop, { { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2752 { M32RXF_INSN_NOT, model_m32rx_not, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2753 { M32RXF_INSN_RAC_DSI, model_m32rx_rac_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2754 { M32RXF_INSN_RACH_DSI, model_m32rx_rach_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2755 { M32RXF_INSN_RTE, model_m32rx_rte, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2756 { M32RXF_INSN_SETH, model_m32rx_seth, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2757 { M32RXF_INSN_SLL, model_m32rx_sll, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2758 { M32RXF_INSN_SLL3, model_m32rx_sll3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2759 { M32RXF_INSN_SLLI, model_m32rx_slli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2760 { M32RXF_INSN_SRA, model_m32rx_sra, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2761 { M32RXF_INSN_SRA3, model_m32rx_sra3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2762 { M32RXF_INSN_SRAI, model_m32rx_srai, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2763 { M32RXF_INSN_SRL, model_m32rx_srl, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2764 { M32RXF_INSN_SRL3, model_m32rx_srl3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2765 { M32RXF_INSN_SRLI, model_m32rx_srli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2766 { M32RXF_INSN_ST, model_m32rx_st, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2767 { M32RXF_INSN_ST_D, model_m32rx_st_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2768 { M32RXF_INSN_STB, model_m32rx_stb, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2769 { M32RXF_INSN_STB_D, model_m32rx_stb_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2770 { M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2771 { M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2772 { M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2773 { M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2774 { M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2775 { M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2776 { M32RXF_INSN_SUBX, model_m32rx_subx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2777 { M32RXF_INSN_TRAP, model_m32rx_trap, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2778 { M32RXF_INSN_UNLOCK, model_m32rx_unlock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2779 { M32RXF_INSN_SATB, model_m32rx_satb, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2780 { M32RXF_INSN_SATH, model_m32rx_sath, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2781 { M32RXF_INSN_SAT, model_m32rx_sat, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2782 { M32RXF_INSN_PCMPBZ, model_m32rx_pcmpbz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2783 { M32RXF_INSN_SADD, model_m32rx_sadd, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2784 { M32RXF_INSN_MACWU1, model_m32rx_macwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2785 { M32RXF_INSN_MSBLO, model_m32rx_msblo, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2786 { M32RXF_INSN_MULWU1, model_m32rx_mulwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2787 { M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2788 { M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2789 { M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2792 #endif /* WITH_PROFILE_MODEL_P */
2795 m32rx_model_init (SIM_CPU *cpu)
2797 CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32RX_DATA));
2800 #if WITH_PROFILE_MODEL_P
2801 #define TIMING_DATA(td) td
2803 #define TIMING_DATA(td) 0
2806 static const MODEL m32rx_models[] =
2808 { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
2812 /* The properties of this cpu's implementation. */
2814 static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
2824 static const CGEN_INSN *
2825 m32rxf_opcode (SIM_CPU *cpu, int inum)
2827 return CPU_IDESC (cpu) [inum].opcode;
2830 /* start-sanitize-m32rx */
2832 m32rx_init_cpu (SIM_CPU *cpu)
2834 CPU_REG_FETCH (cpu) = m32rxf_fetch_register;
2835 CPU_REG_STORE (cpu) = m32rxf_store_register;
2836 CPU_PC_FETCH (cpu) = m32rxf_h_pc_get;
2837 CPU_PC_STORE (cpu) = m32rxf_h_pc_set;
2838 CPU_OPCODE (cpu) = m32rxf_opcode;
2839 CPU_MAX_INSNS (cpu) = M32RXF_INSN_MAX;
2840 CPU_INSN_NAME (cpu) = cgen_insn_name;
2841 CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full;
2843 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_fast;
2845 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_full;
2847 m32rxf_init_idesc_table (cpu);
2850 const MACH m32rx_mach =
2853 32, 32, & m32rx_models[0], & m32rxf_imp_properties,
2857 /* end-sanitize-m32rx */