1 # Simulator main loop for m32r2. -*- C -*-
2 # Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc.
4 # This file is part of GDB, the GNU debugger.
6 # This program is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; either version 2, or (at your option)
11 # This program is distributed in the hope that it will be useful,
12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 # GNU General Public License for more details.
16 # You should have received a copy of the GNU General Public License along
17 # with this program; if not, write to the Free Software Foundation, Inc.,
18 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 # /bin/sh mainloop.in command
27 # extract-{simple,scache,pbb}
28 # {full,fast}-exec-{simple,scache,pbb}
30 # A target need only provide a "full" version of one of simple,scache,pbb.
31 # If the target wants it can also provide a fast version of same, or if
32 # the slow (full featured) version is `simple', then the fast version can be
34 # A target can't provide more than this.
36 # ??? After a few more ports are done, revisit.
37 # Will eventually need to machine generate a lot of this.
45 /* Emit insns to write back the results of insns executed in parallel.
46 SC points to a sufficient number of scache entries for the writeback
48 SC1/ID1 is the first insn (left slot, lower address).
49 SC2/ID2 is the second insn (right slot, higher address). */
52 emit_par_finish (SIM_CPU *current_cpu, PCADDR pc, SCACHE *sc,
53 SCACHE *sc1, const IDESC *id1, SCACHE *sc2, const IDESC *id2)
59 abuf->fields.write.abuf = &sc1->argbuf;
60 @cpu@_fill_argbuf (current_cpu, abuf, id1, pc, 0);
61 /* no need to set trace_p,profile_p */
62 #if 0 /* not currently needed for id2 since results written directly */
65 abuf->fields.write.abuf = &sc2->argbuf;
66 @cpu@_fill_argbuf (current_cpu, abuf, id2, pc + 2, 0);
67 /* no need to set trace_p,profile_p */
71 static INLINE const IDESC *
72 emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
73 SCACHE *sc, int fast_p, int parallel_p)
75 ARGBUF *abuf = &sc->argbuf;
76 const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
80 @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
84 static INLINE const IDESC *
85 emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
86 int trace_p, int profile_p)
90 @cpu@_emit_before (current_cpu, sc, pc, 1);
91 id = emit_16 (current_cpu, pc, insn, sc + 1, 0, 0);
92 @cpu@_emit_after (current_cpu, sc + 2, pc);
93 sc[1].argbuf.trace_p = trace_p;
94 sc[1].argbuf.profile_p = profile_p;
98 static INLINE const IDESC *
99 emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
100 SCACHE *sc, int fast_p)
102 const IDESC *id,*id2;
104 /* Emit both insns, then emit a finisher-upper.
105 We speed things up by handling the second insn serially
106 [not parallelly]. Then the writeback only has to deal
107 with the first insn. */
108 /* ??? Revisit to handle exceptions right. */
110 /* FIXME: No need to handle this parallely if second is nop. */
111 id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1);
113 /* Note that this can never be a cti. No cti's go in the S pipeline. */
114 id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, fast_p, 0);
116 /* Set sc/snc insns notion of where to skip to. */
117 if (IDESC_SKIP_P (id))
118 SEM_SKIP_COMPILE (current_cpu, sc, 1);
120 /* Emit code to finish executing the semantics
121 (write back the results). */
122 emit_par_finish (current_cpu, pc, sc + 2, sc, id, sc + 1, id2);
127 static INLINE const IDESC *
128 emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
129 SCACHE *sc, int trace_p, int profile_p)
131 const IDESC *id,*id2;
133 /* Emit both insns, then emit a finisher-upper.
134 We speed things up by handling the second insn serially
135 [not parallelly]. Then the writeback only has to deal
136 with the first insn. */
137 /* ??? Revisit to handle exceptions right. */
139 @cpu@_emit_before (current_cpu, sc, pc, 1);
141 /* FIXME: No need to handle this parallelly if second is nop. */
142 id = emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 1);
143 sc[1].argbuf.trace_p = trace_p;
144 sc[1].argbuf.profile_p = profile_p;
146 @cpu@_emit_before (current_cpu, sc + 2, pc, 0);
148 /* Note that this can never be a cti. No cti's go in the S pipeline. */
149 id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 3, 0, 0);
150 sc[3].argbuf.trace_p = trace_p;
151 sc[3].argbuf.profile_p = profile_p;
153 /* Set sc/snc insns notion of where to skip to. */
154 if (IDESC_SKIP_P (id))
155 SEM_SKIP_COMPILE (current_cpu, sc, 4);
157 /* Emit code to finish executing the semantics
158 (write back the results). */
159 emit_par_finish (current_cpu, pc, sc + 4, sc + 1, id, sc + 3, id2);
161 @cpu@_emit_after (current_cpu, sc + 5, pc);
166 static INLINE const IDESC *
167 emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
168 SCACHE *sc, int fast_p)
170 ARGBUF *abuf = &sc->argbuf;
171 const IDESC *id = @cpu@_decode (current_cpu, pc,
172 (USI) insn >> 16, insn, abuf);
174 @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
178 static INLINE const IDESC *
179 emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
180 int trace_p, int profile_p)
184 @cpu@_emit_before (current_cpu, sc, pc, 1);
185 id = emit_32 (current_cpu, pc, insn, sc + 1, 0);
186 @cpu@_emit_after (current_cpu, sc + 2, pc);
187 sc[1].argbuf.trace_p = trace_p;
188 sc[1].argbuf.profile_p = profile_p;
204 # Inputs: current_cpu, pc, sc, max_insns, FAST_P
206 # sc must be left pointing past the last created entry.
207 # pc must be left pointing past the last created entry.
208 # If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
209 # to record the vpc of the cti insn.
210 # SET_INSN_COUNT(n) must be called to record number of real insns.
219 /* This occurs when single stepping and when compiling the not-taken
220 part of conditional branches. */
221 UHI insn = GETIMEMUHI (current_cpu, pc);
222 int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
223 int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
224 SCACHE *cti_sc; /* ??? tmp hack */
226 /* A parallel insn isn't allowed here, but we don't mind nops.
227 ??? We need to wait until the insn is executed before signalling
228 the error, for situations where such signalling is wanted. */
230 if ((insn & 0x8000) != 0
231 && (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
232 sim_engine_invalid_insn (current_cpu, pc, 0);
235 /* Only emit before/after handlers if necessary. */
236 if (FAST_P || (! trace_p && ! profile_p))
238 idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P, 0);
245 idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
253 if (IDESC_CTI_P (idesc))
255 SET_CTI_VPC (cti_sc);
260 /* There are two copies of the compiler: full(!fast) and fast.
261 The "full" case emits before/after handlers for each insn.
262 Having two copies of this code is a tradeoff, having one copy
263 seemed a bit more difficult to read (due to constantly testing
264 FAST_P). ??? On the other hand, with address ranges we'll want to
265 omit before/after handlers for unwanted insns. Having separate loops
266 for FAST/!FAST avoids constantly doing the test in the loop, but
267 typically FAST_P is a constant and such tests will get optimized out. */
271 while (max_insns > 0)
273 USI insn = GETIMEMUSI (current_cpu, pc);
277 idesc = emit_32 (current_cpu, pc, insn, sc, 1);
282 if (IDESC_CTI_P (idesc))
284 SET_CTI_VPC (sc - 1);
290 if ((insn & 0x8000) != 0) /* parallel? */
292 /* Yep. Here's the "interesting" [sic] part. */
293 idesc = emit_parallel (current_cpu, pc, insn, sc, 1);
298 if (IDESC_CTI_P (idesc))
300 SET_CTI_VPC (sc - 3);
304 else /* 2 serial 16 bit insns */
306 idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 1, 0);
311 if (IDESC_CTI_P (idesc))
313 SET_CTI_VPC (sc - 1);
316 /* While we're guaranteed that there's room to extract the
317 insn, when single stepping we can't; the pbb must stop
318 after the first insn. */
321 idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 1, 0);
326 if (IDESC_CTI_P (idesc))
328 SET_CTI_VPC (sc - 1);
337 while (max_insns > 0)
339 USI insn = GETIMEMUSI (current_cpu, pc);
340 int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
341 int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
342 SCACHE *cti_sc; /* ??? tmp hack */
346 Only emit before/after handlers if necessary. */
347 if (trace_p || profile_p)
349 idesc = emit_full32 (current_cpu, pc, insn, sc,
357 idesc = emit_32 (current_cpu, pc, insn, sc, 0);
364 if (IDESC_CTI_P (idesc))
366 SET_CTI_VPC (cti_sc);
372 if ((insn & 0x8000) != 0) /* parallel? */
374 /* Yep. Here's the "interesting" [sic] part.
375 Only emit before/after handlers if necessary. */
376 if (trace_p || profile_p)
378 idesc = emit_full_parallel (current_cpu, pc, insn, sc,
386 idesc = emit_parallel (current_cpu, pc, insn, sc, 0);
393 if (IDESC_CTI_P (idesc))
395 SET_CTI_VPC (cti_sc);
399 else /* 2 serial 16 bit insns */
401 /* Only emit before/after handlers if necessary. */
402 if (trace_p || profile_p)
404 idesc = emit_full16 (current_cpu, pc, insn >> 16, sc,
412 idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 0, 0);
419 if (IDESC_CTI_P (idesc))
421 SET_CTI_VPC (cti_sc);
424 /* While we're guaranteed that there's room to extract the
425 insn, when single stepping we can't; the pbb must stop
426 after the first insn. */
429 /* Use the same trace/profile address for the 2nd insn.
430 Saves us having to compute it and they come in pairs
431 anyway (e.g. can never branch to the 2nd insn). */
432 if (trace_p || profile_p)
434 idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
442 idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 0, 0);
449 if (IDESC_CTI_P (idesc))
451 SET_CTI_VPC (cti_sc);
460 SET_INSN_COUNT (icount);
468 # Inputs: current_cpu, vpc, FAST_P
470 # vpc is the virtual program counter.
473 #define DEFINE_SWITCH
474 #include "sem2-switch.c"
480 echo "Invalid argument to mainloop.in: $1" >&2