1 /* m32r simulator support code
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #define WANT_CPU m32rbf
22 #define WANT_CPU_M32RBF
28 /* Decode gdb ctrl register number. */
31 m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
35 case PSW_REGNUM : return H_CR_PSW;
36 case CBR_REGNUM : return H_CR_CBR;
37 case SPI_REGNUM : return H_CR_SPI;
38 case SPU_REGNUM : return H_CR_SPU;
39 case BPC_REGNUM : return H_CR_BPC;
40 case BBPSW_REGNUM : return H_CR_BBPSW;
41 case BBPC_REGNUM : return H_CR_BBPC;
42 case EVB_REGNUM : return H_CR_CR5;
47 /* The contents of BUF are in target byte order. */
50 m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
52 int mach = MACH_NUM (CPU_MACH (current_cpu));
55 SETTWI (buf, a_m32r_h_gr_get (current_cpu, rn));
67 SETTWI (buf, a_m32r_h_cr_get (current_cpu,
68 m32r_decode_gdb_ctrl_regnum (rn)));
71 if (mach == MACH_M32R)
72 SETTWI (buf, m32rbf_h_pc_get (current_cpu));
73 else if (mach == MACH_M32RX)
74 SETTWI (buf, m32rxf_h_pc_get (current_cpu));
76 SETTWI (buf, m32r2f_h_pc_get (current_cpu));
79 if (mach == MACH_M32R)
80 SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
81 else if (mach == MACH_M32RX)
82 SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
84 SETTWI (buf, GETLODI (m32r2f_h_accum_get (current_cpu)));
87 if (mach == MACH_M32R)
88 SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
89 else if (mach == MACH_M32RX)
90 SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
92 SETTWI (buf, GETHIDI (m32r2f_h_accum_get (current_cpu)));
101 /* The contents of BUF are in target byte order. */
104 m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
106 int mach = MACH_NUM (CPU_MACH (current_cpu));
109 a_m32r_h_gr_set (current_cpu, rn, GETTWI (buf));
121 a_m32r_h_cr_set (current_cpu,
122 m32r_decode_gdb_ctrl_regnum (rn),
126 if (mach == MACH_M32R)
127 m32rbf_h_pc_set (current_cpu, GETTWI (buf));
128 else if (mach == MACH_M32RX)
129 m32rxf_h_pc_set (current_cpu, GETTWI (buf));
131 m32r2f_h_pc_set (current_cpu, GETTWI (buf));
136 if (mach == MACH_M32R)
137 val = m32rbf_h_accum_get (current_cpu);
138 else if (mach == MACH_M32RX)
139 val = m32rxf_h_accum_get (current_cpu);
141 val = m32r2f_h_accum_get (current_cpu);
142 SETLODI (val, GETTWI (buf));
143 if (mach == MACH_M32R)
144 m32rbf_h_accum_set (current_cpu, val);
145 else if (mach == MACH_M32RX)
146 m32rxf_h_accum_set (current_cpu, val);
148 m32r2f_h_accum_set (current_cpu, val);
154 if (mach == MACH_M32R)
155 val = m32rbf_h_accum_get (current_cpu);
156 else if (mach == MACH_M32RX)
157 val = m32rxf_h_accum_get (current_cpu);
159 val = m32r2f_h_accum_get (current_cpu);
160 SETHIDI (val, GETTWI (buf));
161 if (mach == MACH_M32R)
162 m32rbf_h_accum_set (current_cpu, val);
163 else if (mach == MACH_M32RX)
164 m32rxf_h_accum_set (current_cpu, val);
166 m32r2f_h_accum_set (current_cpu, val);
176 /* Cover fns for mach independent register accesses. */
179 a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno)
181 switch (MACH_NUM (CPU_MACH (current_cpu)))
183 #ifdef HAVE_CPU_M32RBF
185 return m32rbf_h_gr_get (current_cpu, regno);
187 #ifdef HAVE_CPU_M32RXF
189 return m32rxf_h_gr_get (current_cpu, regno);
191 #ifdef HAVE_CPU_M32R2F
193 return m32r2f_h_gr_get (current_cpu, regno);
201 a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
203 switch (MACH_NUM (CPU_MACH (current_cpu)))
205 #ifdef HAVE_CPU_M32RBF
207 m32rbf_h_gr_set (current_cpu, regno, newval);
210 #ifdef HAVE_CPU_M32RXF
212 m32rxf_h_gr_set (current_cpu, regno, newval);
215 #ifdef HAVE_CPU_M32RXF
217 m32r2f_h_gr_set (current_cpu, regno, newval);
226 a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno)
228 switch (MACH_NUM (CPU_MACH (current_cpu)))
230 #ifdef HAVE_CPU_M32RBF
232 return m32rbf_h_cr_get (current_cpu, regno);
234 #ifdef HAVE_CPU_M32RXF
236 return m32rxf_h_cr_get (current_cpu, regno);
238 #ifdef HAVE_CPU_M32R2F
240 return m32r2f_h_cr_get (current_cpu, regno);
248 a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
250 switch (MACH_NUM (CPU_MACH (current_cpu)))
252 #ifdef HAVE_CPU_M32RBF
254 m32rbf_h_cr_set (current_cpu, regno, newval);
257 #ifdef HAVE_CPU_M32RXF
259 m32rxf_h_cr_set (current_cpu, regno, newval);
262 #ifdef HAVE_CPU_M32RXF
264 m32r2f_h_cr_set (current_cpu, regno, newval);
273 m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
277 case H_CR_PSW : /* psw */
278 return (((CPU (h_bpsw) & 0xc1) << 8)
279 | ((CPU (h_psw) & 0xc0) << 0)
281 case H_CR_BBPSW : /* backup backup psw */
282 return CPU (h_bbpsw) & 0xc1;
283 case H_CR_CBR : /* condition bit */
284 return GET_H_COND ();
285 case H_CR_SPI : /* interrupt stack pointer */
287 return CPU (h_gr[H_GR_SP]);
289 return CPU (h_cr[H_CR_SPI]);
290 case H_CR_SPU : /* user stack pointer */
292 return CPU (h_gr[H_GR_SP]);
294 return CPU (h_cr[H_CR_SPU]);
295 case H_CR_BPC : /* backup pc */
296 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
297 case H_CR_BBPC : /* backup backup pc */
298 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
299 case 4 : /* ??? unspecified, but apparently available */
300 case 5 : /* ??? unspecified, but apparently available */
301 return CPU (h_cr[cr]);
308 m32rbf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
312 case H_CR_PSW : /* psw */
314 int old_sm = (CPU (h_psw) & 0x80) != 0;
315 int new_sm = (newval & 0x80) != 0;
316 CPU (h_bpsw) = (newval >> 8) & 0xff;
317 CPU (h_psw) = newval & 0xff;
318 SET_H_COND (newval & 1);
319 /* When switching stack modes, update the registers. */
320 if (old_sm != new_sm)
324 /* Switching user -> system. */
325 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
326 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
330 /* Switching system -> user. */
331 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
332 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
337 case H_CR_BBPSW : /* backup backup psw */
338 CPU (h_bbpsw) = newval & 0xff;
340 case H_CR_CBR : /* condition bit */
341 SET_H_COND (newval & 1);
343 case H_CR_SPI : /* interrupt stack pointer */
345 CPU (h_gr[H_GR_SP]) = newval;
347 CPU (h_cr[H_CR_SPI]) = newval;
349 case H_CR_SPU : /* user stack pointer */
351 CPU (h_gr[H_GR_SP]) = newval;
353 CPU (h_cr[H_CR_SPU]) = newval;
355 case H_CR_BPC : /* backup pc */
356 CPU (h_cr[H_CR_BPC]) = newval;
358 case H_CR_BBPC : /* backup backup pc */
359 CPU (h_cr[H_CR_BBPC]) = newval;
361 case 4 : /* ??? unspecified, but apparently available */
362 case 5 : /* ??? unspecified, but apparently available */
363 CPU (h_cr[cr]) = newval;
371 /* Cover fns to access h-psw. */
374 m32rbf_h_psw_get_handler (SIM_CPU *current_cpu)
376 return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
380 m32rbf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
382 CPU (h_psw) = newval;
383 CPU (h_cond) = newval & 1;
386 /* Cover fns to access h-accum. */
389 m32rbf_h_accum_get_handler (SIM_CPU *current_cpu)
391 /* Sign extend the top 8 bits. */
394 r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
395 r = XORDI (r, MAKEDI (0x800000, 0));
396 r = SUBDI (r, MAKEDI (0x800000, 0));
402 hi = ((hi & 0xffffff) ^ 0x800000) - 0x800000;
409 m32rbf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
411 CPU (h_accum) = newval;
414 #if WITH_PROFILE_MODEL_P
416 /* FIXME: Some of these should be inline or macros. Later. */
418 /* Initialize cycle counting for an insn.
419 FIRST_P is non-zero if this is the first insn in a set of parallel
423 m32rbf_model_insn_before (SIM_CPU *cpu, int first_p)
425 M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
430 mp->load_regs_pending = 0;
431 mp->biggest_cycles = 0;
435 /* Record the cycles computed for an insn.
436 LAST_P is non-zero if this is the last insn in a set of parallel insns,
437 and we update the total cycle count.
438 CYCLES is the cycle count of the insn. */
441 m32rbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
443 PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
444 M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
445 unsigned long total = cycles + mp->cti_stall + mp->load_stall;
449 unsigned long biggest = total > mp->biggest_cycles ? total : mp->biggest_cycles;
450 PROFILE_MODEL_TOTAL_CYCLES (p) += biggest;
451 PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
455 /* Here we take advantage of the fact that !last_p -> first_p. */
456 mp->biggest_cycles = total;
457 PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
460 /* Branch and load stall counts are recorded independently of the
461 total cycle count. */
462 PROFILE_MODEL_CTI_STALL_CYCLES (p) += mp->cti_stall;
463 PROFILE_MODEL_LOAD_STALL_CYCLES (p) += mp->load_stall;
465 mp->load_regs = mp->load_regs_pending;
469 check_load_stall (SIM_CPU *cpu, int regno)
471 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
474 && (h_gr & (1 << regno)) != 0)
476 CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
477 if (TRACE_INSN_P (cpu))
478 cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
483 m32rbf_model_m32r_d_u_exec (SIM_CPU *cpu, const IDESC *idesc,
484 int unit_num, int referenced,
485 INT sr, INT sr2, INT dr)
487 check_load_stall (cpu, sr);
488 check_load_stall (cpu, sr2);
489 return idesc->timing->units[unit_num].done;
493 m32rbf_model_m32r_d_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
494 int unit_num, int referenced,
497 check_load_stall (cpu, src1);
498 check_load_stall (cpu, src2);
499 return idesc->timing->units[unit_num].done;
503 m32rbf_model_m32r_d_u_mac (SIM_CPU *cpu, const IDESC *idesc,
504 int unit_num, int referenced,
507 check_load_stall (cpu, src1);
508 check_load_stall (cpu, src2);
509 return idesc->timing->units[unit_num].done;
513 m32rbf_model_m32r_d_u_cti (SIM_CPU *cpu, const IDESC *idesc,
514 int unit_num, int referenced,
517 PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
518 int taken_p = (referenced & (1 << 1)) != 0;
520 check_load_stall (cpu, sr);
523 CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
524 PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
527 PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
528 return idesc->timing->units[unit_num].done;
532 m32rbf_model_m32r_d_u_load (SIM_CPU *cpu, const IDESC *idesc,
533 int unit_num, int referenced,
536 CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
537 check_load_stall (cpu, sr);
538 return idesc->timing->units[unit_num].done;
542 m32rbf_model_m32r_d_u_store (SIM_CPU *cpu, const IDESC *idesc,
543 int unit_num, int referenced,
546 check_load_stall (cpu, src1);
547 check_load_stall (cpu, src2);
548 return idesc->timing->units[unit_num].done;
552 m32rbf_model_test_u_exec (SIM_CPU *cpu, const IDESC *idesc,
553 int unit_num, int referenced)
555 return idesc->timing->units[unit_num].done;
558 #endif /* WITH_PROFILE_MODEL_P */