1 /* collection of junk waiting time to sort out
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of the GNU Simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* gdb register numbers */
31 #define ACCL_REGNUM 22
32 #define ACCH_REGNUM 23
33 #define ACC1L_REGNUM 24
34 #define ACC1H_REGNUM 25
35 #define BBPSW_REGNUM 26
36 #define BBPC_REGNUM 27
39 extern int m32r_decode_gdb_ctrl_regnum (int);
41 /* Cover macros for hardware accesses.
42 FIXME: Eventually move to cgen. */
43 #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
45 extern SI a_m32r_h_gr_get (SIM_CPU *, UINT);
46 extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
47 extern USI a_m32r_h_cr_get (SIM_CPU *, UINT);
48 extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
50 extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
51 extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
53 extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
54 extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
56 extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
57 extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
59 extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT);
60 extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI);
61 extern UQI m32rxf_h_psw_get_handler (SIM_CPU *);
62 extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI);
63 extern DI m32rxf_h_accum_get_handler (SIM_CPU *);
64 extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI);
66 extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT);
67 extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI);
69 /* Misc. profile data. */
72 /* nop insn slot filler count */
73 unsigned int fillnop_count;
74 /* number of parallel insns */
75 unsigned int parallel_count;
77 /* FIXME: generalize this to handle all insn lengths, move to common. */
78 /* number of short insns, not including parallel ones */
79 unsigned int short_count;
80 /* number of long insns */
81 unsigned int long_count;
83 /* Working area for computing cycle counts. */
84 unsigned long insn_cycles; /* FIXME: delete */
85 unsigned long cti_stall;
86 unsigned long load_stall;
87 unsigned long biggest_cycles;
89 /* Bitmask of registers loaded by previous insn. */
90 unsigned int load_regs;
91 /* Bitmask of registers loaded by current insn. */
92 unsigned int load_regs_pending;
95 /* Initialize the working area. */
96 void m32r_init_insn_cycles (SIM_CPU *, int);
97 /* Update the totals for the insn. */
98 void m32r_record_insn_cycles (SIM_CPU *, int);
100 /* This is invoked by the nop pattern in the .cpu file. */
101 #define PROFILE_COUNT_FILLNOPS(cpu, addr) \
103 if (PROFILE_INSN_P (cpu) \
104 && (addr & 3) != 0) \
105 ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
108 /* This is invoked by the execute section of mloop{,x}.in. */
109 #define PROFILE_COUNT_PARINSNS(cpu) \
111 if (PROFILE_INSN_P (cpu)) \
112 ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
115 /* This is invoked by the execute section of mloop{,x}.in. */
116 #define PROFILE_COUNT_SHORTINSNS(cpu) \
118 if (PROFILE_INSN_P (cpu)) \
119 ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
122 /* This is invoked by the execute section of mloop{,x}.in. */
123 #define PROFILE_COUNT_LONGINSNS(cpu) \
125 if (PROFILE_INSN_P (cpu)) \
126 ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
129 #define GETTWI GETTSI
130 #define SETTWI SETTSI
132 /* Additional execution support. */
134 /* Result of semantic function is one of
135 - next address, branch only
136 - NEW_PC_SKIP, sc/snc insn
137 - NEW_PC_2, 2 byte non-branch non-sc/snc insn
138 - NEW_PC_4, 4 byte non-branch insn
139 The special values have bit 1 set so it's cheap to distinguish them.
140 This works because all cti's are defined to zero the bottom two bits
141 Note that the m32rx no longer doesn't implement its semantics with
142 functions, so this isn't used. It's kept around should it be needed
144 /* FIXME: replace 0xffff0001 with 1? */
145 #define NEW_PC_BASE 0xffff0001
146 #define NEW_PC_SKIP NEW_PC_BASE
147 #define NEW_PC_2 (NEW_PC_BASE + 2)
148 #define NEW_PC_4 (NEW_PC_BASE + 4)
149 #define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0)
151 /* Modify "next pc" support to handle parallel execution.
152 This is for the non-pbb case. The m32rx no longer implements this.
153 It's kept around should it be needed again. */
154 #if defined (WANT_CPU_M32RXF) && ! WITH_SCACHE_PBB_M32RXF
156 #define SEM_NEXT_VPC(abuf, len) (NEW_PC_BASE + (len))
158 #define SEM_SKIP_INSN(cpu, sc, vpcvar, yes) FIXME
161 /* Hardware/device support.
162 ??? Will eventually want to move device stuff to config files. */
164 /* Exception, Interrupt, and Trap addresses */
165 #define EIT_SYSBREAK_ADDR 0x10
166 #define EIT_RSVD_INSN_ADDR 0x20
167 #define EIT_ADDR_EXCP_ADDR 0x30
168 #define EIT_TRAP_BASE_ADDR 0x40
169 #define EIT_EXTERN_ADDR 0x80
170 #define EIT_RESET_ADDR 0x7ffffff0
171 #define EIT_WAKEUP_ADDR 0x7ffffff0
173 /* Special purpose traps. */
174 #define TRAP_SYSCALL 0
175 #define TRAP_BREAKPOINT 1
177 /* Support for the MSPR register (Cache Purge Control Register)
178 and the MCCR register (Cache Control Register) are needed in order for
179 overlays to work correctly with the scache.
180 MSPR no longer exists but is supported for upward compatibility with
181 early overlay support. */
183 /* Cache Purge Control (only exists on early versions of chips) */
184 #define MSPR_ADDR 0xfffffff7
187 /* Lock Control Register (not supported) */
188 #define MLCR_ADDR 0xfffffff7
191 /* Power Management Control Register (not supported) */
192 #define MPMR_ADDR 0xfffffffb
194 /* Cache Control Register */
195 #define MCCR_ADDR 0xffffffff
201 /* Serial device addresses. */
202 #ifdef M32R_EVA /* orig eva board, no longer supported */
203 #define UART_INCHAR_ADDR 0xff102013
204 #define UART_OUTCHAR_ADDR 0xff10200f
205 #define UART_STATUS_ADDR 0xff102006
206 /* Indicate ready bit is inverted. */
207 #define UART_INPUT_READY0
209 /* These are the values for the MSA2000 board.
210 ??? Will eventually need to move this to a config file. */
211 #define UART_INCHAR_ADDR 0xff004009
212 #define UART_OUTCHAR_ADDR 0xff004007
213 #define UART_STATUS_ADDR 0xff004002
216 #define UART_INPUT_READY 0x4
217 #define UART_OUTPUT_READY 0x1
219 /* Start address and length of all device support. */
220 #define M32R_DEVICE_ADDR 0xff000000
221 #define M32R_DEVICE_LEN 0x01000000
223 /* sim_core_attach device argument. */
224 extern device m32r_devices;
226 /* FIXME: Temporary, until device support ready. */
227 struct _device { int foo; };
229 /* Handle the trap insn. */
230 USI m32r_trap (SIM_CPU *, PCADDR, int);
232 #endif /* M32R_SIM_H */