1 /* Simulator instruction decoder for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #define WANT_CPU m32rxf
26 #define WANT_CPU_M32RXF
29 #include "sim-assert.h"
31 /* Insn can't be executed in parallel.
32 Or is that "do NOt Pass to Air defense Radar"? :-) */
35 /* The instruction descriptor array.
36 This is computed at runtime. Space for it is not malloc'd to save a
37 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
38 but won't be done until necessary (we don't currently support the runtime
39 addition of instructions nor an SMP machine with different cpus). */
40 static IDESC m32rxf_insn_data[M32RXF_INSN__MAX];
42 /* Commas between elements are contained in the macros.
43 Some of these are conditionally compiled out. */
45 static const struct insn_sem m32rxf_insn_sem[] =
47 { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
48 { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
49 { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
50 { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
51 { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
52 { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
53 { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD },
54 { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR },
55 { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND },
56 { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR },
57 { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR },
58 { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR },
59 { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR },
60 { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR },
61 { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI },
62 { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV },
63 { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR },
64 { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX },
65 { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 },
66 { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR },
67 { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR },
68 { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
69 { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
70 { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
71 { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
72 { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
73 { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
74 { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 },
75 { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR },
76 { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 },
77 { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR },
78 { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 },
79 { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR },
80 { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR },
81 { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 },
82 { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR },
83 { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 },
84 { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR },
85 { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP },
86 { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR },
87 { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU },
88 { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR },
89 { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ },
90 { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ },
91 { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR },
92 { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR },
93 { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR },
94 { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR },
95 { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR },
96 { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC },
97 { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC },
98 { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL },
99 { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP },
100 { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD },
101 { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
102 { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB },
103 { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR },
104 { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH },
105 { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR },
106 { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB },
107 { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR },
108 { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH },
109 { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR },
110 { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS },
111 { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR },
112 { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 },
113 { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR },
114 { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK },
115 { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A },
116 { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A },
117 { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A },
118 { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A },
119 { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL },
120 { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A },
121 { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A },
122 { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A },
123 { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A },
124 { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV },
125 { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A },
126 { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A },
127 { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A },
128 { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC },
129 { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A },
130 { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A },
131 { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC },
132 { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG },
133 { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP },
134 { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT },
135 { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI },
136 { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI },
137 { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE },
138 { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR },
139 { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL },
140 { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
141 { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI },
142 { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA },
143 { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
144 { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI },
145 { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL },
146 { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
147 { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI },
148 { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST },
149 { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR },
150 { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB },
151 { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR },
152 { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH },
153 { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR },
154 { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS },
155 { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS },
156 { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB },
157 { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV },
158 { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX },
159 { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP },
160 { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK },
161 { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR },
162 { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR },
163 { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR },
164 { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ },
165 { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD },
166 { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 },
167 { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO },
168 { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 },
169 { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 },
170 { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC },
171 { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC },
174 static const struct insn_sem m32rxf_insn_sem_invalid = {
175 VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR
178 /* Initialize an IDESC from the compile-time computable parts. */
181 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
183 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
187 if ((int) t->type <= 0)
188 id->idata = & cgen_virtual_insn_table[- (int) t->type];
190 id->idata = & insn_table[t->type];
191 id->attrs = CGEN_INSN_ATTRS (id->idata);
192 /* Oh my god, a magic number. */
193 id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
195 #if WITH_PROFILE_MODEL_P
196 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
198 SIM_DESC sd = CPU_STATE (cpu);
199 SIM_ASSERT (t->index == id->timing->num);
203 /* Semantic pointers are initialized elsewhere. */
206 /* Initialize the instruction descriptor table. */
209 m32rxf_init_idesc_table (SIM_CPU *cpu)
212 const struct insn_sem *t,*tend;
213 int tabsize = M32RXF_INSN__MAX;
214 IDESC *table = m32rxf_insn_data;
216 memset (table, 0, tabsize * sizeof (IDESC));
218 /* First set all entries to the `invalid insn'. */
219 t = & m32rxf_insn_sem_invalid;
220 for (id = table, tabend = table + tabsize; id < tabend; ++id)
221 init_idesc (cpu, id, t);
223 /* Now fill in the values for the chosen cpu. */
224 for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
227 init_idesc (cpu, & table[t->index], t);
228 if (t->par_index != NOPAR)
230 init_idesc (cpu, &table[t->par_index], t);
231 table[t->index].par_idesc = &table[t->par_index];
233 if (t->par_index != NOPAR)
235 init_idesc (cpu, &table[t->write_index], t);
236 table[t->par_index].par_idesc = &table[t->write_index];
240 /* Link the IDESC table into the cpu. */
241 CPU_IDESC (cpu) = table;
244 /* Given an instruction, return a pointer to its IDESC entry. */
247 m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
248 CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
251 /* Result of decoder. */
252 M32RXF_INSN_TYPE itype;
255 CGEN_INSN_INT insn = base_insn;
258 unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
261 case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv;
262 case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx;
263 case 2 : itype = M32RXF_INSN_SUB; goto extract_sfmt_add;
264 case 3 : itype = M32RXF_INSN_NEG; goto extract_sfmt_mv;
265 case 4 : itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp;
266 case 5 : itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp;
267 case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp;
270 unsigned int val = (((insn >> 8) & (3 << 0)));
273 case 0 : itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz;
274 case 3 : itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz;
275 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
278 case 8 : itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv;
279 case 9 : itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx;
280 case 10 : itype = M32RXF_INSN_ADD; goto extract_sfmt_add;
281 case 11 : itype = M32RXF_INSN_NOT; goto extract_sfmt_mv;
282 case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add;
283 case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add;
284 case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add;
285 case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add;
286 case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add;
287 case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add;
288 case 22 : itype = M32RXF_INSN_MUL; goto extract_sfmt_add;
289 case 24 : itype = M32RXF_INSN_MV; goto extract_sfmt_mv;
290 case 25 : itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc;
291 case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc;
294 unsigned int val = (((insn >> 8) & (3 << 0)));
297 case 0 : itype = M32RXF_INSN_JC; goto extract_sfmt_jc;
298 case 1 : itype = M32RXF_INSN_JNC; goto extract_sfmt_jc;
299 case 2 : itype = M32RXF_INSN_JL; goto extract_sfmt_jl;
300 case 3 : itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp;
301 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
304 case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte;
305 case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap;
306 case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb;
307 case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth;
308 case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st;
309 case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock;
310 case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
311 case 39 : itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus;
312 case 40 : itype = M32RXF_INSN_LDB; goto extract_sfmt_ldb;
313 case 41 : itype = M32RXF_INSN_LDUB; goto extract_sfmt_ldb;
314 case 42 : itype = M32RXF_INSN_LDH; goto extract_sfmt_ldh;
315 case 43 : itype = M32RXF_INSN_LDUH; goto extract_sfmt_ldh;
316 case 44 : itype = M32RXF_INSN_LD; goto extract_sfmt_ld;
317 case 45 : itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock;
318 case 46 : itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
319 case 48 : /* fall through */
320 case 56 : itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a;
321 case 49 : /* fall through */
322 case 57 : itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a;
323 case 50 : /* fall through */
324 case 58 : itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;
325 case 51 : /* fall through */
326 case 59 : itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;
327 case 52 : /* fall through */
328 case 60 : itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a;
329 case 53 : /* fall through */
330 case 61 : itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a;
331 case 54 : /* fall through */
332 case 62 : itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a;
333 case 55 : /* fall through */
334 case 63 : itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a;
335 case 64 : /* fall through */
336 case 65 : /* fall through */
337 case 66 : /* fall through */
338 case 67 : /* fall through */
339 case 68 : /* fall through */
340 case 69 : /* fall through */
341 case 70 : /* fall through */
342 case 71 : /* fall through */
343 case 72 : /* fall through */
344 case 73 : /* fall through */
345 case 74 : /* fall through */
346 case 75 : /* fall through */
347 case 76 : /* fall through */
348 case 77 : /* fall through */
349 case 78 : /* fall through */
350 case 79 : itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi;
351 case 80 : /* fall through */
352 case 81 : itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli;
353 case 82 : /* fall through */
354 case 83 : itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli;
355 case 84 : /* fall through */
356 case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli;
359 unsigned int val = (((insn >> 0) & (1 << 0)));
362 case 0 : itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
363 case 1 : itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
364 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
367 case 88 : itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
368 case 89 : itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
369 case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1;
370 case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1;
371 case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1;
372 case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo;
373 case 94 : itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd;
376 unsigned int val = (((insn >> 0) & (3 << 0)));
379 case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
380 case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
381 case 2 : itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;
382 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
385 case 96 : /* fall through */
386 case 97 : /* fall through */
387 case 98 : /* fall through */
388 case 99 : /* fall through */
389 case 100 : /* fall through */
390 case 101 : /* fall through */
391 case 102 : /* fall through */
392 case 103 : /* fall through */
393 case 104 : /* fall through */
394 case 105 : /* fall through */
395 case 106 : /* fall through */
396 case 107 : /* fall through */
397 case 108 : /* fall through */
398 case 109 : /* fall through */
399 case 110 : /* fall through */
400 case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8;
403 unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
406 case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop;
407 case 9 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc;
408 case 11 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc;
409 case 16 : /* fall through */
410 case 17 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
411 case 18 : /* fall through */
412 case 19 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
413 case 24 : /* fall through */
414 case 25 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
415 case 26 : /* fall through */
416 case 27 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
417 case 28 : /* fall through */
418 case 29 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
419 case 30 : /* fall through */
420 case 31 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
421 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
424 case 113 : /* fall through */
425 case 114 : /* fall through */
426 case 115 : /* fall through */
427 case 116 : /* fall through */
428 case 117 : /* fall through */
429 case 118 : /* fall through */
430 case 119 : /* fall through */
431 case 120 : /* fall through */
432 case 121 : /* fall through */
433 case 122 : /* fall through */
434 case 123 : /* fall through */
435 case 124 : /* fall through */
436 case 125 : /* fall through */
437 case 126 : /* fall through */
440 unsigned int val = (((insn >> 8) & (7 << 0)));
443 case 0 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
444 case 1 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
445 case 4 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
446 case 5 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
447 case 6 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
448 case 7 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
449 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
452 case 132 : itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi;
453 case 133 : itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi;
456 unsigned int val = (((insn >> -8) & (3 << 0)));
459 case 0 : itype = M32RXF_INSN_SAT; goto extract_sfmt_sat;
460 case 2 : itype = M32RXF_INSN_SATH; goto extract_sfmt_satb;
461 case 3 : itype = M32RXF_INSN_SATB; goto extract_sfmt_satb;
462 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
465 case 136 : itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3;
466 case 138 : itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3;
467 case 140 : itype = M32RXF_INSN_AND3; goto extract_sfmt_and3;
468 case 141 : itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3;
469 case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;
472 unsigned int val = (((insn >> -12) & (1 << 0)));
475 case 0 : itype = M32RXF_INSN_DIV; goto extract_sfmt_div;
476 case 1 : itype = M32RXF_INSN_DIVH; goto extract_sfmt_div;
477 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
480 case 145 : itype = M32RXF_INSN_DIVU; goto extract_sfmt_div;
481 case 146 : itype = M32RXF_INSN_REM; goto extract_sfmt_div;
482 case 147 : itype = M32RXF_INSN_REMU; goto extract_sfmt_div;
483 case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3;
484 case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3;
485 case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3;
486 case 159 : itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16;
487 case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d;
488 case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d;
489 case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d;
490 case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ldb_d;
491 case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ldb_d;
492 case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ldh_d;
493 case 171 : itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ldh_d;
494 case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d;
495 case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq;
496 case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq;
497 case 184 : itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz;
498 case 185 : itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz;
499 case 186 : itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz;
500 case 187 : itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz;
501 case 188 : itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz;
502 case 189 : itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz;
503 case 220 : itype = M32RXF_INSN_SETH; goto extract_sfmt_seth;
504 case 224 : /* fall through */
505 case 225 : /* fall through */
506 case 226 : /* fall through */
507 case 227 : /* fall through */
508 case 228 : /* fall through */
509 case 229 : /* fall through */
510 case 230 : /* fall through */
511 case 231 : /* fall through */
512 case 232 : /* fall through */
513 case 233 : /* fall through */
514 case 234 : /* fall through */
515 case 235 : /* fall through */
516 case 236 : /* fall through */
517 case 237 : /* fall through */
518 case 238 : /* fall through */
519 case 239 : itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24;
520 case 240 : /* fall through */
521 case 241 : /* fall through */
522 case 242 : /* fall through */
523 case 243 : /* fall through */
524 case 244 : /* fall through */
525 case 245 : /* fall through */
526 case 246 : /* fall through */
527 case 247 : /* fall through */
528 case 248 : /* fall through */
529 case 249 : /* fall through */
530 case 250 : /* fall through */
531 case 251 : /* fall through */
532 case 252 : /* fall through */
533 case 253 : /* fall through */
534 case 254 : /* fall through */
537 unsigned int val = (((insn >> 8) & (7 << 0)));
540 case 0 : itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24;
541 case 1 : itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24;
542 case 4 : itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24;
543 case 5 : itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24;
544 case 6 : itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24;
545 case 7 : itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24;
546 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
549 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
554 /* The instruction has been decoded, now extract the fields. */
558 const IDESC *idesc = &m32rxf_insn_data[itype];
559 #define FLD(f) abuf->fields.fmt_empty.f
562 /* Record the fields for the semantic handler. */
563 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
571 const IDESC *idesc = &m32rxf_insn_data[itype];
572 CGEN_INSN_INT insn = entire_insn;
573 #define FLD(f) abuf->fields.sfmt_add.f
577 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
578 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
580 /* Record the fields for the semantic handler. */
583 FLD (i_dr) = & CPU (h_gr)[f_r1];
584 FLD (i_sr) = & CPU (h_gr)[f_r2];
585 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
587 #if WITH_PROFILE_MODEL_P
588 /* Record the fields for profiling. */
589 if (PROFILE_MODEL_P (current_cpu))
602 const IDESC *idesc = &m32rxf_insn_data[itype];
603 CGEN_INSN_INT insn = entire_insn;
604 #define FLD(f) abuf->fields.sfmt_add3.f
609 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
610 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
611 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
613 /* Record the fields for the semantic handler. */
614 FLD (f_simm16) = f_simm16;
617 FLD (i_sr) = & CPU (h_gr)[f_r2];
618 FLD (i_dr) = & CPU (h_gr)[f_r1];
619 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
621 #if WITH_PROFILE_MODEL_P
622 /* Record the fields for profiling. */
623 if (PROFILE_MODEL_P (current_cpu))
635 const IDESC *idesc = &m32rxf_insn_data[itype];
636 CGEN_INSN_INT insn = entire_insn;
637 #define FLD(f) abuf->fields.sfmt_and3.f
642 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
643 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
644 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
646 /* Record the fields for the semantic handler. */
648 FLD (f_uimm16) = f_uimm16;
650 FLD (i_sr) = & CPU (h_gr)[f_r2];
651 FLD (i_dr) = & CPU (h_gr)[f_r1];
652 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
654 #if WITH_PROFILE_MODEL_P
655 /* Record the fields for profiling. */
656 if (PROFILE_MODEL_P (current_cpu))
668 const IDESC *idesc = &m32rxf_insn_data[itype];
669 CGEN_INSN_INT insn = entire_insn;
670 #define FLD(f) abuf->fields.sfmt_and3.f
675 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
676 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
677 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
679 /* Record the fields for the semantic handler. */
681 FLD (f_uimm16) = f_uimm16;
683 FLD (i_sr) = & CPU (h_gr)[f_r2];
684 FLD (i_dr) = & CPU (h_gr)[f_r1];
685 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
687 #if WITH_PROFILE_MODEL_P
688 /* Record the fields for profiling. */
689 if (PROFILE_MODEL_P (current_cpu))
701 const IDESC *idesc = &m32rxf_insn_data[itype];
702 CGEN_INSN_INT insn = entire_insn;
703 #define FLD(f) abuf->fields.sfmt_addi.f
707 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
708 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
710 /* Record the fields for the semantic handler. */
712 FLD (f_simm8) = f_simm8;
713 FLD (i_dr) = & CPU (h_gr)[f_r1];
714 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
716 #if WITH_PROFILE_MODEL_P
717 /* Record the fields for profiling. */
718 if (PROFILE_MODEL_P (current_cpu))
730 const IDESC *idesc = &m32rxf_insn_data[itype];
731 CGEN_INSN_INT insn = entire_insn;
732 #define FLD(f) abuf->fields.sfmt_add.f
736 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
737 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
739 /* Record the fields for the semantic handler. */
742 FLD (i_dr) = & CPU (h_gr)[f_r1];
743 FLD (i_sr) = & CPU (h_gr)[f_r2];
744 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
746 #if WITH_PROFILE_MODEL_P
747 /* Record the fields for profiling. */
748 if (PROFILE_MODEL_P (current_cpu))
761 const IDESC *idesc = &m32rxf_insn_data[itype];
762 CGEN_INSN_INT insn = entire_insn;
763 #define FLD(f) abuf->fields.sfmt_add3.f
768 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
769 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
770 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
772 /* Record the fields for the semantic handler. */
773 FLD (f_simm16) = f_simm16;
776 FLD (i_sr) = & CPU (h_gr)[f_r2];
777 FLD (i_dr) = & CPU (h_gr)[f_r1];
778 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
780 #if WITH_PROFILE_MODEL_P
781 /* Record the fields for profiling. */
782 if (PROFILE_MODEL_P (current_cpu))
794 const IDESC *idesc = &m32rxf_insn_data[itype];
795 CGEN_INSN_INT insn = entire_insn;
796 #define FLD(f) abuf->fields.sfmt_add.f
800 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
801 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
803 /* Record the fields for the semantic handler. */
806 FLD (i_dr) = & CPU (h_gr)[f_r1];
807 FLD (i_sr) = & CPU (h_gr)[f_r2];
808 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
810 #if WITH_PROFILE_MODEL_P
811 /* Record the fields for profiling. */
812 if (PROFILE_MODEL_P (current_cpu))
825 const IDESC *idesc = &m32rxf_insn_data[itype];
826 CGEN_INSN_INT insn = entire_insn;
827 #define FLD(f) abuf->fields.sfmt_bl8.f
830 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
832 /* Record the fields for the semantic handler. */
833 FLD (i_disp8) = f_disp8;
834 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
836 #if WITH_PROFILE_MODEL_P
837 /* Record the fields for profiling. */
838 if (PROFILE_MODEL_P (current_cpu))
848 const IDESC *idesc = &m32rxf_insn_data[itype];
849 CGEN_INSN_INT insn = entire_insn;
850 #define FLD(f) abuf->fields.sfmt_bl24.f
853 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
855 /* Record the fields for the semantic handler. */
856 FLD (i_disp24) = f_disp24;
857 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
859 #if WITH_PROFILE_MODEL_P
860 /* Record the fields for profiling. */
861 if (PROFILE_MODEL_P (current_cpu))
871 const IDESC *idesc = &m32rxf_insn_data[itype];
872 CGEN_INSN_INT insn = entire_insn;
873 #define FLD(f) abuf->fields.sfmt_beq.f
878 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
879 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
880 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
882 /* Record the fields for the semantic handler. */
885 FLD (i_disp16) = f_disp16;
886 FLD (i_src1) = & CPU (h_gr)[f_r1];
887 FLD (i_src2) = & CPU (h_gr)[f_r2];
888 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
890 #if WITH_PROFILE_MODEL_P
891 /* Record the fields for profiling. */
892 if (PROFILE_MODEL_P (current_cpu))
894 FLD (in_src1) = f_r1;
895 FLD (in_src2) = f_r2;
904 const IDESC *idesc = &m32rxf_insn_data[itype];
905 CGEN_INSN_INT insn = entire_insn;
906 #define FLD(f) abuf->fields.sfmt_beq.f
910 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
911 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
913 /* Record the fields for the semantic handler. */
915 FLD (i_disp16) = f_disp16;
916 FLD (i_src2) = & CPU (h_gr)[f_r2];
917 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
919 #if WITH_PROFILE_MODEL_P
920 /* Record the fields for profiling. */
921 if (PROFILE_MODEL_P (current_cpu))
923 FLD (in_src2) = f_r2;
932 const IDESC *idesc = &m32rxf_insn_data[itype];
933 CGEN_INSN_INT insn = entire_insn;
934 #define FLD(f) abuf->fields.sfmt_bl8.f
937 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
939 /* Record the fields for the semantic handler. */
940 FLD (i_disp8) = f_disp8;
941 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
943 #if WITH_PROFILE_MODEL_P
944 /* Record the fields for profiling. */
945 if (PROFILE_MODEL_P (current_cpu))
947 FLD (out_h_gr_SI_14) = 14;
956 const IDESC *idesc = &m32rxf_insn_data[itype];
957 CGEN_INSN_INT insn = entire_insn;
958 #define FLD(f) abuf->fields.sfmt_bl24.f
961 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
963 /* Record the fields for the semantic handler. */
964 FLD (i_disp24) = f_disp24;
965 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
967 #if WITH_PROFILE_MODEL_P
968 /* Record the fields for profiling. */
969 if (PROFILE_MODEL_P (current_cpu))
971 FLD (out_h_gr_SI_14) = 14;
980 const IDESC *idesc = &m32rxf_insn_data[itype];
981 CGEN_INSN_INT insn = entire_insn;
982 #define FLD(f) abuf->fields.sfmt_bl8.f
985 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
987 /* Record the fields for the semantic handler. */
988 FLD (i_disp8) = f_disp8;
989 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
991 #if WITH_PROFILE_MODEL_P
992 /* Record the fields for profiling. */
993 if (PROFILE_MODEL_P (current_cpu))
995 FLD (out_h_gr_SI_14) = 14;
1004 const IDESC *idesc = &m32rxf_insn_data[itype];
1005 CGEN_INSN_INT insn = entire_insn;
1006 #define FLD(f) abuf->fields.sfmt_bl24.f
1009 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1011 /* Record the fields for the semantic handler. */
1012 FLD (i_disp24) = f_disp24;
1013 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1015 #if WITH_PROFILE_MODEL_P
1016 /* Record the fields for profiling. */
1017 if (PROFILE_MODEL_P (current_cpu))
1019 FLD (out_h_gr_SI_14) = 14;
1028 const IDESC *idesc = &m32rxf_insn_data[itype];
1029 CGEN_INSN_INT insn = entire_insn;
1030 #define FLD(f) abuf->fields.sfmt_bl8.f
1033 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1035 /* Record the fields for the semantic handler. */
1036 FLD (i_disp8) = f_disp8;
1037 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1039 #if WITH_PROFILE_MODEL_P
1040 /* Record the fields for profiling. */
1041 if (PROFILE_MODEL_P (current_cpu))
1051 const IDESC *idesc = &m32rxf_insn_data[itype];
1052 CGEN_INSN_INT insn = entire_insn;
1053 #define FLD(f) abuf->fields.sfmt_bl24.f
1056 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1058 /* Record the fields for the semantic handler. */
1059 FLD (i_disp24) = f_disp24;
1060 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1062 #if WITH_PROFILE_MODEL_P
1063 /* Record the fields for profiling. */
1064 if (PROFILE_MODEL_P (current_cpu))
1074 const IDESC *idesc = &m32rxf_insn_data[itype];
1075 CGEN_INSN_INT insn = entire_insn;
1076 #define FLD(f) abuf->fields.sfmt_st_plus.f
1080 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1081 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1083 /* Record the fields for the semantic handler. */
1086 FLD (i_src1) = & CPU (h_gr)[f_r1];
1087 FLD (i_src2) = & CPU (h_gr)[f_r2];
1088 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1090 #if WITH_PROFILE_MODEL_P
1091 /* Record the fields for profiling. */
1092 if (PROFILE_MODEL_P (current_cpu))
1094 FLD (in_src1) = f_r1;
1095 FLD (in_src2) = f_r2;
1104 const IDESC *idesc = &m32rxf_insn_data[itype];
1105 CGEN_INSN_INT insn = entire_insn;
1106 #define FLD(f) abuf->fields.sfmt_st_d.f
1110 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1111 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1113 /* Record the fields for the semantic handler. */
1114 FLD (f_simm16) = f_simm16;
1116 FLD (i_src2) = & CPU (h_gr)[f_r2];
1117 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1119 #if WITH_PROFILE_MODEL_P
1120 /* Record the fields for profiling. */
1121 if (PROFILE_MODEL_P (current_cpu))
1123 FLD (in_src2) = f_r2;
1132 const IDESC *idesc = &m32rxf_insn_data[itype];
1133 CGEN_INSN_INT insn = entire_insn;
1134 #define FLD(f) abuf->fields.sfmt_st_plus.f
1137 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1139 /* Record the fields for the semantic handler. */
1141 FLD (i_src2) = & CPU (h_gr)[f_r2];
1142 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1144 #if WITH_PROFILE_MODEL_P
1145 /* Record the fields for profiling. */
1146 if (PROFILE_MODEL_P (current_cpu))
1148 FLD (in_src2) = f_r2;
1157 const IDESC *idesc = &m32rxf_insn_data[itype];
1158 CGEN_INSN_INT insn = entire_insn;
1159 #define FLD(f) abuf->fields.sfmt_add.f
1163 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1164 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1166 /* Record the fields for the semantic handler. */
1169 FLD (i_dr) = & CPU (h_gr)[f_r1];
1170 FLD (i_sr) = & CPU (h_gr)[f_r2];
1171 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1173 #if WITH_PROFILE_MODEL_P
1174 /* Record the fields for profiling. */
1175 if (PROFILE_MODEL_P (current_cpu))
1179 FLD (out_dr) = f_r1;
1188 const IDESC *idesc = &m32rxf_insn_data[itype];
1189 CGEN_INSN_INT insn = entire_insn;
1190 #define FLD(f) abuf->fields.sfmt_jl.f
1193 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1195 /* Record the fields for the semantic handler. */
1197 FLD (i_sr) = & CPU (h_gr)[f_r2];
1198 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1200 #if WITH_PROFILE_MODEL_P
1201 /* Record the fields for profiling. */
1202 if (PROFILE_MODEL_P (current_cpu))
1213 const IDESC *idesc = &m32rxf_insn_data[itype];
1214 CGEN_INSN_INT insn = entire_insn;
1215 #define FLD(f) abuf->fields.sfmt_jl.f
1218 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1220 /* Record the fields for the semantic handler. */
1222 FLD (i_sr) = & CPU (h_gr)[f_r2];
1223 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1225 #if WITH_PROFILE_MODEL_P
1226 /* Record the fields for profiling. */
1227 if (PROFILE_MODEL_P (current_cpu))
1230 FLD (out_h_gr_SI_14) = 14;
1239 const IDESC *idesc = &m32rxf_insn_data[itype];
1240 CGEN_INSN_INT insn = entire_insn;
1241 #define FLD(f) abuf->fields.sfmt_jl.f
1244 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1246 /* Record the fields for the semantic handler. */
1248 FLD (i_sr) = & CPU (h_gr)[f_r2];
1249 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1251 #if WITH_PROFILE_MODEL_P
1252 /* Record the fields for profiling. */
1253 if (PROFILE_MODEL_P (current_cpu))
1264 const IDESC *idesc = &m32rxf_insn_data[itype];
1265 CGEN_INSN_INT insn = entire_insn;
1266 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1270 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1271 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1273 /* Record the fields for the semantic handler. */
1276 FLD (i_sr) = & CPU (h_gr)[f_r2];
1277 FLD (i_dr) = & CPU (h_gr)[f_r1];
1278 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1280 #if WITH_PROFILE_MODEL_P
1281 /* Record the fields for profiling. */
1282 if (PROFILE_MODEL_P (current_cpu))
1285 FLD (out_dr) = f_r1;
1294 const IDESC *idesc = &m32rxf_insn_data[itype];
1295 CGEN_INSN_INT insn = entire_insn;
1296 #define FLD(f) abuf->fields.sfmt_add3.f
1301 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1302 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1303 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1305 /* Record the fields for the semantic handler. */
1306 FLD (f_simm16) = f_simm16;
1309 FLD (i_sr) = & CPU (h_gr)[f_r2];
1310 FLD (i_dr) = & CPU (h_gr)[f_r1];
1311 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1313 #if WITH_PROFILE_MODEL_P
1314 /* Record the fields for profiling. */
1315 if (PROFILE_MODEL_P (current_cpu))
1318 FLD (out_dr) = f_r1;
1327 const IDESC *idesc = &m32rxf_insn_data[itype];
1328 CGEN_INSN_INT insn = entire_insn;
1329 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1333 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1334 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1336 /* Record the fields for the semantic handler. */
1339 FLD (i_sr) = & CPU (h_gr)[f_r2];
1340 FLD (i_dr) = & CPU (h_gr)[f_r1];
1341 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1343 #if WITH_PROFILE_MODEL_P
1344 /* Record the fields for profiling. */
1345 if (PROFILE_MODEL_P (current_cpu))
1348 FLD (out_dr) = f_r1;
1357 const IDESC *idesc = &m32rxf_insn_data[itype];
1358 CGEN_INSN_INT insn = entire_insn;
1359 #define FLD(f) abuf->fields.sfmt_add3.f
1364 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1365 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1366 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1368 /* Record the fields for the semantic handler. */
1369 FLD (f_simm16) = f_simm16;
1372 FLD (i_sr) = & CPU (h_gr)[f_r2];
1373 FLD (i_dr) = & CPU (h_gr)[f_r1];
1374 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1376 #if WITH_PROFILE_MODEL_P
1377 /* Record the fields for profiling. */
1378 if (PROFILE_MODEL_P (current_cpu))
1381 FLD (out_dr) = f_r1;
1390 const IDESC *idesc = &m32rxf_insn_data[itype];
1391 CGEN_INSN_INT insn = entire_insn;
1392 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1396 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1397 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1399 /* Record the fields for the semantic handler. */
1402 FLD (i_sr) = & CPU (h_gr)[f_r2];
1403 FLD (i_dr) = & CPU (h_gr)[f_r1];
1404 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1406 #if WITH_PROFILE_MODEL_P
1407 /* Record the fields for profiling. */
1408 if (PROFILE_MODEL_P (current_cpu))
1411 FLD (out_dr) = f_r1;
1420 const IDESC *idesc = &m32rxf_insn_data[itype];
1421 CGEN_INSN_INT insn = entire_insn;
1422 #define FLD(f) abuf->fields.sfmt_add3.f
1427 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1428 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1429 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1431 /* Record the fields for the semantic handler. */
1432 FLD (f_simm16) = f_simm16;
1435 FLD (i_sr) = & CPU (h_gr)[f_r2];
1436 FLD (i_dr) = & CPU (h_gr)[f_r1];
1437 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1439 #if WITH_PROFILE_MODEL_P
1440 /* Record the fields for profiling. */
1441 if (PROFILE_MODEL_P (current_cpu))
1444 FLD (out_dr) = f_r1;
1451 extract_sfmt_ld_plus:
1453 const IDESC *idesc = &m32rxf_insn_data[itype];
1454 CGEN_INSN_INT insn = entire_insn;
1455 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1459 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1460 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1462 /* Record the fields for the semantic handler. */
1465 FLD (i_sr) = & CPU (h_gr)[f_r2];
1466 FLD (i_dr) = & CPU (h_gr)[f_r1];
1467 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1469 #if WITH_PROFILE_MODEL_P
1470 /* Record the fields for profiling. */
1471 if (PROFILE_MODEL_P (current_cpu))
1474 FLD (out_dr) = f_r1;
1475 FLD (out_sr) = f_r2;
1484 const IDESC *idesc = &m32rxf_insn_data[itype];
1485 CGEN_INSN_INT insn = entire_insn;
1486 #define FLD(f) abuf->fields.sfmt_ld24.f
1490 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1491 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
1493 /* Record the fields for the semantic handler. */
1495 FLD (i_uimm24) = f_uimm24;
1496 FLD (i_dr) = & CPU (h_gr)[f_r1];
1497 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1499 #if WITH_PROFILE_MODEL_P
1500 /* Record the fields for profiling. */
1501 if (PROFILE_MODEL_P (current_cpu))
1503 FLD (out_dr) = f_r1;
1512 const IDESC *idesc = &m32rxf_insn_data[itype];
1513 CGEN_INSN_INT insn = entire_insn;
1514 #define FLD(f) abuf->fields.sfmt_addi.f
1518 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1519 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
1521 /* Record the fields for the semantic handler. */
1522 FLD (f_simm8) = f_simm8;
1524 FLD (i_dr) = & CPU (h_gr)[f_r1];
1525 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1527 #if WITH_PROFILE_MODEL_P
1528 /* Record the fields for profiling. */
1529 if (PROFILE_MODEL_P (current_cpu))
1531 FLD (out_dr) = f_r1;
1540 const IDESC *idesc = &m32rxf_insn_data[itype];
1541 CGEN_INSN_INT insn = entire_insn;
1542 #define FLD(f) abuf->fields.sfmt_add3.f
1546 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1547 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1549 /* Record the fields for the semantic handler. */
1550 FLD (f_simm16) = f_simm16;
1552 FLD (i_dr) = & CPU (h_gr)[f_r1];
1553 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1555 #if WITH_PROFILE_MODEL_P
1556 /* Record the fields for profiling. */
1557 if (PROFILE_MODEL_P (current_cpu))
1559 FLD (out_dr) = f_r1;
1568 const IDESC *idesc = &m32rxf_insn_data[itype];
1569 CGEN_INSN_INT insn = entire_insn;
1570 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1574 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1575 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1577 /* Record the fields for the semantic handler. */
1580 FLD (i_sr) = & CPU (h_gr)[f_r2];
1581 FLD (i_dr) = & CPU (h_gr)[f_r1];
1582 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1584 #if WITH_PROFILE_MODEL_P
1585 /* Record the fields for profiling. */
1586 if (PROFILE_MODEL_P (current_cpu))
1589 FLD (out_dr) = f_r1;
1596 extract_sfmt_machi_a:
1598 const IDESC *idesc = &m32rxf_insn_data[itype];
1599 CGEN_INSN_INT insn = entire_insn;
1600 #define FLD(f) abuf->fields.sfmt_machi_a.f
1605 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1606 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1607 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1609 /* Record the fields for the semantic handler. */
1610 FLD (f_acc) = f_acc;
1613 FLD (i_src1) = & CPU (h_gr)[f_r1];
1614 FLD (i_src2) = & CPU (h_gr)[f_r2];
1615 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1617 #if WITH_PROFILE_MODEL_P
1618 /* Record the fields for profiling. */
1619 if (PROFILE_MODEL_P (current_cpu))
1621 FLD (in_src1) = f_r1;
1622 FLD (in_src2) = f_r2;
1629 extract_sfmt_mulhi_a:
1631 const IDESC *idesc = &m32rxf_insn_data[itype];
1632 CGEN_INSN_INT insn = entire_insn;
1633 #define FLD(f) abuf->fields.sfmt_machi_a.f
1638 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1639 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1640 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1642 /* Record the fields for the semantic handler. */
1645 FLD (f_acc) = f_acc;
1646 FLD (i_src1) = & CPU (h_gr)[f_r1];
1647 FLD (i_src2) = & CPU (h_gr)[f_r2];
1648 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1650 #if WITH_PROFILE_MODEL_P
1651 /* Record the fields for profiling. */
1652 if (PROFILE_MODEL_P (current_cpu))
1654 FLD (in_src1) = f_r1;
1655 FLD (in_src2) = f_r2;
1664 const IDESC *idesc = &m32rxf_insn_data[itype];
1665 CGEN_INSN_INT insn = entire_insn;
1666 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1670 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1671 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1673 /* Record the fields for the semantic handler. */
1676 FLD (i_sr) = & CPU (h_gr)[f_r2];
1677 FLD (i_dr) = & CPU (h_gr)[f_r1];
1678 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1680 #if WITH_PROFILE_MODEL_P
1681 /* Record the fields for profiling. */
1682 if (PROFILE_MODEL_P (current_cpu))
1685 FLD (out_dr) = f_r1;
1692 extract_sfmt_mvfachi_a:
1694 const IDESC *idesc = &m32rxf_insn_data[itype];
1695 CGEN_INSN_INT insn = entire_insn;
1696 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1700 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1701 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1703 /* Record the fields for the semantic handler. */
1704 FLD (f_accs) = f_accs;
1706 FLD (i_dr) = & CPU (h_gr)[f_r1];
1707 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1709 #if WITH_PROFILE_MODEL_P
1710 /* Record the fields for profiling. */
1711 if (PROFILE_MODEL_P (current_cpu))
1713 FLD (out_dr) = f_r1;
1722 const IDESC *idesc = &m32rxf_insn_data[itype];
1723 CGEN_INSN_INT insn = entire_insn;
1724 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1728 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1729 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1731 /* Record the fields for the semantic handler. */
1734 FLD (i_dr) = & CPU (h_gr)[f_r1];
1735 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1737 #if WITH_PROFILE_MODEL_P
1738 /* Record the fields for profiling. */
1739 if (PROFILE_MODEL_P (current_cpu))
1741 FLD (out_dr) = f_r1;
1748 extract_sfmt_mvtachi_a:
1750 const IDESC *idesc = &m32rxf_insn_data[itype];
1751 CGEN_INSN_INT insn = entire_insn;
1752 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1756 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1757 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1759 /* Record the fields for the semantic handler. */
1760 FLD (f_accs) = f_accs;
1762 FLD (i_src1) = & CPU (h_gr)[f_r1];
1763 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
1765 #if WITH_PROFILE_MODEL_P
1766 /* Record the fields for profiling. */
1767 if (PROFILE_MODEL_P (current_cpu))
1769 FLD (in_src1) = f_r1;
1778 const IDESC *idesc = &m32rxf_insn_data[itype];
1779 CGEN_INSN_INT insn = entire_insn;
1780 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1784 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1785 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1787 /* Record the fields for the semantic handler. */
1790 FLD (i_sr) = & CPU (h_gr)[f_r2];
1791 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1793 #if WITH_PROFILE_MODEL_P
1794 /* Record the fields for profiling. */
1795 if (PROFILE_MODEL_P (current_cpu))
1806 const IDESC *idesc = &m32rxf_insn_data[itype];
1807 #define FLD(f) abuf->fields.fmt_empty.f
1810 /* Record the fields for the semantic handler. */
1811 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
1817 extract_sfmt_rac_dsi:
1819 const IDESC *idesc = &m32rxf_insn_data[itype];
1820 CGEN_INSN_INT insn = entire_insn;
1821 #define FLD(f) abuf->fields.sfmt_rac_dsi.f
1826 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
1827 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1828 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
1830 /* Record the fields for the semantic handler. */
1831 FLD (f_accs) = f_accs;
1832 FLD (f_imm1) = f_imm1;
1833 FLD (f_accd) = f_accd;
1834 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
1842 const IDESC *idesc = &m32rxf_insn_data[itype];
1843 #define FLD(f) abuf->fields.fmt_empty.f
1846 /* Record the fields for the semantic handler. */
1847 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
1849 #if WITH_PROFILE_MODEL_P
1850 /* Record the fields for profiling. */
1851 if (PROFILE_MODEL_P (current_cpu))
1861 const IDESC *idesc = &m32rxf_insn_data[itype];
1862 CGEN_INSN_INT insn = entire_insn;
1863 #define FLD(f) abuf->fields.sfmt_seth.f
1867 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1868 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
1870 /* Record the fields for the semantic handler. */
1871 FLD (f_hi16) = f_hi16;
1873 FLD (i_dr) = & CPU (h_gr)[f_r1];
1874 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1876 #if WITH_PROFILE_MODEL_P
1877 /* Record the fields for profiling. */
1878 if (PROFILE_MODEL_P (current_cpu))
1880 FLD (out_dr) = f_r1;
1889 const IDESC *idesc = &m32rxf_insn_data[itype];
1890 CGEN_INSN_INT insn = entire_insn;
1891 #define FLD(f) abuf->fields.sfmt_add3.f
1896 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1897 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1898 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1900 /* Record the fields for the semantic handler. */
1901 FLD (f_simm16) = f_simm16;
1904 FLD (i_sr) = & CPU (h_gr)[f_r2];
1905 FLD (i_dr) = & CPU (h_gr)[f_r1];
1906 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1908 #if WITH_PROFILE_MODEL_P
1909 /* Record the fields for profiling. */
1910 if (PROFILE_MODEL_P (current_cpu))
1913 FLD (out_dr) = f_r1;
1922 const IDESC *idesc = &m32rxf_insn_data[itype];
1923 CGEN_INSN_INT insn = entire_insn;
1924 #define FLD(f) abuf->fields.sfmt_slli.f
1928 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1929 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
1931 /* Record the fields for the semantic handler. */
1933 FLD (f_uimm5) = f_uimm5;
1934 FLD (i_dr) = & CPU (h_gr)[f_r1];
1935 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
1937 #if WITH_PROFILE_MODEL_P
1938 /* Record the fields for profiling. */
1939 if (PROFILE_MODEL_P (current_cpu))
1942 FLD (out_dr) = f_r1;
1951 const IDESC *idesc = &m32rxf_insn_data[itype];
1952 CGEN_INSN_INT insn = entire_insn;
1953 #define FLD(f) abuf->fields.sfmt_st_plus.f
1957 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1958 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1960 /* Record the fields for the semantic handler. */
1963 FLD (i_src1) = & CPU (h_gr)[f_r1];
1964 FLD (i_src2) = & CPU (h_gr)[f_r2];
1965 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1967 #if WITH_PROFILE_MODEL_P
1968 /* Record the fields for profiling. */
1969 if (PROFILE_MODEL_P (current_cpu))
1971 FLD (in_src1) = f_r1;
1972 FLD (in_src2) = f_r2;
1981 const IDESC *idesc = &m32rxf_insn_data[itype];
1982 CGEN_INSN_INT insn = entire_insn;
1983 #define FLD(f) abuf->fields.sfmt_st_d.f
1988 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1989 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1990 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1992 /* Record the fields for the semantic handler. */
1993 FLD (f_simm16) = f_simm16;
1996 FLD (i_src1) = & CPU (h_gr)[f_r1];
1997 FLD (i_src2) = & CPU (h_gr)[f_r2];
1998 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2000 #if WITH_PROFILE_MODEL_P
2001 /* Record the fields for profiling. */
2002 if (PROFILE_MODEL_P (current_cpu))
2004 FLD (in_src1) = f_r1;
2005 FLD (in_src2) = f_r2;
2014 const IDESC *idesc = &m32rxf_insn_data[itype];
2015 CGEN_INSN_INT insn = entire_insn;
2016 #define FLD(f) abuf->fields.sfmt_st_plus.f
2020 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2021 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2023 /* Record the fields for the semantic handler. */
2026 FLD (i_src1) = & CPU (h_gr)[f_r1];
2027 FLD (i_src2) = & CPU (h_gr)[f_r2];
2028 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2030 #if WITH_PROFILE_MODEL_P
2031 /* Record the fields for profiling. */
2032 if (PROFILE_MODEL_P (current_cpu))
2034 FLD (in_src1) = f_r1;
2035 FLD (in_src2) = f_r2;
2044 const IDESC *idesc = &m32rxf_insn_data[itype];
2045 CGEN_INSN_INT insn = entire_insn;
2046 #define FLD(f) abuf->fields.sfmt_st_d.f
2051 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2052 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2053 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
2055 /* Record the fields for the semantic handler. */
2056 FLD (f_simm16) = f_simm16;
2059 FLD (i_src1) = & CPU (h_gr)[f_r1];
2060 FLD (i_src2) = & CPU (h_gr)[f_r2];
2061 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2063 #if WITH_PROFILE_MODEL_P
2064 /* Record the fields for profiling. */
2065 if (PROFILE_MODEL_P (current_cpu))
2067 FLD (in_src1) = f_r1;
2068 FLD (in_src2) = f_r2;
2077 const IDESC *idesc = &m32rxf_insn_data[itype];
2078 CGEN_INSN_INT insn = entire_insn;
2079 #define FLD(f) abuf->fields.sfmt_st_plus.f
2083 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2084 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2086 /* Record the fields for the semantic handler. */
2089 FLD (i_src1) = & CPU (h_gr)[f_r1];
2090 FLD (i_src2) = & CPU (h_gr)[f_r2];
2091 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2093 #if WITH_PROFILE_MODEL_P
2094 /* Record the fields for profiling. */
2095 if (PROFILE_MODEL_P (current_cpu))
2097 FLD (in_src1) = f_r1;
2098 FLD (in_src2) = f_r2;
2107 const IDESC *idesc = &m32rxf_insn_data[itype];
2108 CGEN_INSN_INT insn = entire_insn;
2109 #define FLD(f) abuf->fields.sfmt_st_d.f
2114 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2115 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2116 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
2118 /* Record the fields for the semantic handler. */
2119 FLD (f_simm16) = f_simm16;
2122 FLD (i_src1) = & CPU (h_gr)[f_r1];
2123 FLD (i_src2) = & CPU (h_gr)[f_r2];
2124 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2126 #if WITH_PROFILE_MODEL_P
2127 /* Record the fields for profiling. */
2128 if (PROFILE_MODEL_P (current_cpu))
2130 FLD (in_src1) = f_r1;
2131 FLD (in_src2) = f_r2;
2138 extract_sfmt_st_plus:
2140 const IDESC *idesc = &m32rxf_insn_data[itype];
2141 CGEN_INSN_INT insn = entire_insn;
2142 #define FLD(f) abuf->fields.sfmt_st_plus.f
2146 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2147 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2149 /* Record the fields for the semantic handler. */
2152 FLD (i_src1) = & CPU (h_gr)[f_r1];
2153 FLD (i_src2) = & CPU (h_gr)[f_r2];
2154 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2156 #if WITH_PROFILE_MODEL_P
2157 /* Record the fields for profiling. */
2158 if (PROFILE_MODEL_P (current_cpu))
2160 FLD (in_src1) = f_r1;
2161 FLD (in_src2) = f_r2;
2162 FLD (out_src2) = f_r2;
2171 const IDESC *idesc = &m32rxf_insn_data[itype];
2172 CGEN_INSN_INT insn = entire_insn;
2173 #define FLD(f) abuf->fields.sfmt_trap.f
2176 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2178 /* Record the fields for the semantic handler. */
2179 FLD (f_uimm4) = f_uimm4;
2180 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
2182 #if WITH_PROFILE_MODEL_P
2183 /* Record the fields for profiling. */
2184 if (PROFILE_MODEL_P (current_cpu))
2192 extract_sfmt_unlock:
2194 const IDESC *idesc = &m32rxf_insn_data[itype];
2195 CGEN_INSN_INT insn = entire_insn;
2196 #define FLD(f) abuf->fields.sfmt_st_plus.f
2200 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2201 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2203 /* Record the fields for the semantic handler. */
2206 FLD (i_src1) = & CPU (h_gr)[f_r1];
2207 FLD (i_src2) = & CPU (h_gr)[f_r2];
2208 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2210 #if WITH_PROFILE_MODEL_P
2211 /* Record the fields for profiling. */
2212 if (PROFILE_MODEL_P (current_cpu))
2214 FLD (in_src1) = f_r1;
2215 FLD (in_src2) = f_r2;
2224 const IDESC *idesc = &m32rxf_insn_data[itype];
2225 CGEN_INSN_INT insn = entire_insn;
2226 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2230 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2231 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2233 /* Record the fields for the semantic handler. */
2236 FLD (i_sr) = & CPU (h_gr)[f_r2];
2237 FLD (i_dr) = & CPU (h_gr)[f_r1];
2238 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2240 #if WITH_PROFILE_MODEL_P
2241 /* Record the fields for profiling. */
2242 if (PROFILE_MODEL_P (current_cpu))
2245 FLD (out_dr) = f_r1;
2254 const IDESC *idesc = &m32rxf_insn_data[itype];
2255 CGEN_INSN_INT insn = entire_insn;
2256 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2260 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2261 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2263 /* Record the fields for the semantic handler. */
2266 FLD (i_sr) = & CPU (h_gr)[f_r2];
2267 FLD (i_dr) = & CPU (h_gr)[f_r1];
2268 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2270 #if WITH_PROFILE_MODEL_P
2271 /* Record the fields for profiling. */
2272 if (PROFILE_MODEL_P (current_cpu))
2275 FLD (out_dr) = f_r1;
2284 const IDESC *idesc = &m32rxf_insn_data[itype];
2285 #define FLD(f) abuf->fields.fmt_empty.f
2288 /* Record the fields for the semantic handler. */
2289 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
2295 extract_sfmt_macwu1:
2297 const IDESC *idesc = &m32rxf_insn_data[itype];
2298 CGEN_INSN_INT insn = entire_insn;
2299 #define FLD(f) abuf->fields.sfmt_st_plus.f
2303 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2304 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2306 /* Record the fields for the semantic handler. */
2309 FLD (i_src1) = & CPU (h_gr)[f_r1];
2310 FLD (i_src2) = & CPU (h_gr)[f_r2];
2311 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2313 #if WITH_PROFILE_MODEL_P
2314 /* Record the fields for profiling. */
2315 if (PROFILE_MODEL_P (current_cpu))
2317 FLD (in_src1) = f_r1;
2318 FLD (in_src2) = f_r2;
2327 const IDESC *idesc = &m32rxf_insn_data[itype];
2328 CGEN_INSN_INT insn = entire_insn;
2329 #define FLD(f) abuf->fields.sfmt_st_plus.f
2333 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2334 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2336 /* Record the fields for the semantic handler. */
2339 FLD (i_src1) = & CPU (h_gr)[f_r1];
2340 FLD (i_src2) = & CPU (h_gr)[f_r2];
2341 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2343 #if WITH_PROFILE_MODEL_P
2344 /* Record the fields for profiling. */
2345 if (PROFILE_MODEL_P (current_cpu))
2347 FLD (in_src1) = f_r1;
2348 FLD (in_src2) = f_r2;
2355 extract_sfmt_mulwu1:
2357 const IDESC *idesc = &m32rxf_insn_data[itype];
2358 CGEN_INSN_INT insn = entire_insn;
2359 #define FLD(f) abuf->fields.sfmt_st_plus.f
2363 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2364 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2366 /* Record the fields for the semantic handler. */
2369 FLD (i_src1) = & CPU (h_gr)[f_r1];
2370 FLD (i_src2) = & CPU (h_gr)[f_r2];
2371 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2373 #if WITH_PROFILE_MODEL_P
2374 /* Record the fields for profiling. */
2375 if (PROFILE_MODEL_P (current_cpu))
2377 FLD (in_src1) = f_r1;
2378 FLD (in_src2) = f_r2;
2387 const IDESC *idesc = &m32rxf_insn_data[itype];
2388 #define FLD(f) abuf->fields.fmt_empty.f
2391 /* Record the fields for the semantic handler. */
2392 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));