1 /* CPU family header for m32rx.
3 This file is machine generated with CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 2
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 #define GET_H_CR(a1) CPU (h_cr)[a1]
50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
53 #define GET_H_ACCUM() CPU (h_accum)
54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
55 /* start-sanitize-m32rx */
58 /* end-sanitize-m32rx */
59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
61 /* start-sanitize-m32rx */
64 /* end-sanitize-m32rx */
65 #define GET_H_ABORT() CPU (h_abort)
66 #define SET_H_ABORT(x) (CPU (h_abort) = (x))
69 #define GET_H_COND() CPU (h_cond)
70 #define SET_H_COND(x) (CPU (h_cond) = (x))
73 #define GET_H_SM() CPU (h_sm)
74 #define SET_H_SM(x) (CPU (h_sm) = (x))
77 #define GET_H_BSM() CPU (h_bsm)
78 #define SET_H_BSM(x) (CPU (h_bsm) = (x))
81 #define GET_H_IE() CPU (h_ie)
82 #define SET_H_IE(x) (CPU (h_ie) = (x))
85 #define GET_H_BIE() CPU (h_bie)
86 #define SET_H_BIE(x) (CPU (h_bie) = (x))
89 #define GET_H_BCOND() CPU (h_bcond)
90 #define SET_H_BCOND(x) (CPU (h_bcond) = (x))
93 #define GET_H_BPC() CPU (h_bpc)
94 #define SET_H_BPC(x) (CPU (h_bpc) = (x))
96 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
97 /* CPU profiling state information. */
99 /* general registers */
102 #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
105 extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t);
107 /* The ARGBUF struct. */
109 /* These are the baseclass definitions. */
112 const struct cgen_insn *opcode;
113 #if ! defined (SCACHE_P)
116 /* cpu specific data follows */
118 struct { /* e.g. add $dr,$sr */
122 struct { /* e.g. add3 $dr,$sr,#$slo16 */
127 struct { /* e.g. and3 $dr,$sr,#$uimm16 */
132 struct { /* e.g. or3 $dr,$sr,#$ulo16 */
137 struct { /* e.g. addi $dr,#$simm8 */
141 struct { /* e.g. addv3 $dr,$sr,#$simm16 */
146 struct { /* e.g. addx $dr,$sr */
150 struct { /* e.g. bc $disp8 */
153 struct { /* e.g. bc $disp24 */
156 struct { /* e.g. beq $src1,$src2,$disp16 */
161 struct { /* e.g. beqz $src2,$disp16 */
165 struct { /* e.g. bl $disp8 */
168 struct { /* e.g. bl $disp24 */
171 struct { /* e.g. bcl $disp8 */
174 struct { /* e.g. bcl $disp24 */
177 struct { /* e.g. bra $disp8 */
180 struct { /* e.g. bra $disp24 */
183 struct { /* e.g. cmp $src1,$src2 */
187 struct { /* e.g. cmpi $src2,#$simm16 */
191 struct { /* e.g. cmpui $src2,#$uimm16 */
195 struct { /* e.g. cmpz $src2 */
198 struct { /* e.g. div $dr,$sr */
202 struct { /* e.g. jc $sr */
205 struct { /* e.g. jl $sr */
208 struct { /* e.g. jmp $sr */
211 struct { /* e.g. ld $dr,@$sr */
215 struct { /* e.g. ld $dr,@($slo16,$sr) */
220 struct { /* e.g. ldb $dr,@$sr */
224 struct { /* e.g. ldb $dr,@($slo16,$sr) */
229 struct { /* e.g. ldh $dr,@$sr */
233 struct { /* e.g. ldh $dr,@($slo16,$sr) */
238 struct { /* e.g. ld24 $dr,#$uimm24 */
242 struct { /* e.g. ldi $dr,#$simm8 */
246 struct { /* e.g. ldi $dr,$slo16 */
250 struct { /* e.g. machi $src1,$src2,$acc */
255 struct { /* e.g. mulhi $src1,$src2,$acc */
260 struct { /* e.g. mv $dr,$sr */
264 struct { /* e.g. mvfachi $dr,$accs */
268 struct { /* e.g. mvfc $dr,$scr */
272 struct { /* e.g. mvtachi $src1,$accs */
276 struct { /* e.g. mvtc $sr,$dcr */
280 struct { /* e.g. nop */
283 struct { /* e.g. rac $accd */
286 struct { /* e.g. rac $accd,$accs */
290 struct { /* e.g. rac $accd,$accs,#$imm1 */
295 struct { /* e.g. rte */
298 struct { /* e.g. seth $dr,#$hi16 */
302 struct { /* e.g. slli $dr,#$uimm5 */
306 struct { /* e.g. st $src1,@($slo16,$src2) */
311 struct { /* e.g. trap #$uimm4 */
314 struct { /* e.g. satb $dr,$src2 */
318 struct { /* e.g. sat $dr,$src2 */
322 struct { /* e.g. sadd */
325 struct { /* e.g. macwu1 $src1,$src2 */
329 struct { /* e.g. msblo $src1,$src2 */
333 struct { /* e.g. sc */
337 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
338 unsigned long h_gr_get;
339 unsigned long h_gr_set;
344 This is also used in the non-scache case. In this situation we assume
345 the cache size is 1, and do a few things a little differently. */
350 #if ! WITH_SEM_SWITCH_FULL
353 #if ! WITH_SEM_SWITCH_FAST
355 SEMANTIC_CACHE_FN *sem_fast_fn;
357 SEMANTIC_FN *sem_fast_fn;
360 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
368 struct argbuf argbuf;
371 /* Macros to simplify extraction, reading and semantic code.
372 These define and assign the local vars that contain the insn's fields. */
374 #define EXTRACT_FMT_0_ADD_VARS \
375 /* Instruction fields. */ \
381 #define EXTRACT_FMT_0_ADD_CODE \
383 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
384 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
385 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
386 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
388 #define EXTRACT_FMT_1_ADD3_VARS \
389 /* Instruction fields. */ \
396 #define EXTRACT_FMT_1_ADD3_CODE \
398 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
399 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
400 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
401 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
402 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
404 #define EXTRACT_FMT_2_AND3_VARS \
405 /* Instruction fields. */ \
412 #define EXTRACT_FMT_2_AND3_CODE \
414 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
415 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
416 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
417 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
418 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
420 #define EXTRACT_FMT_3_OR3_VARS \
421 /* Instruction fields. */ \
428 #define EXTRACT_FMT_3_OR3_CODE \
430 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
431 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
432 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
433 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
434 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
436 #define EXTRACT_FMT_4_ADDI_VARS \
437 /* Instruction fields. */ \
442 #define EXTRACT_FMT_4_ADDI_CODE \
444 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
445 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
446 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
448 #define EXTRACT_FMT_5_ADDV3_VARS \
449 /* Instruction fields. */ \
456 #define EXTRACT_FMT_5_ADDV3_CODE \
458 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
459 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
460 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
461 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
462 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
464 #define EXTRACT_FMT_6_ADDX_VARS \
465 /* Instruction fields. */ \
471 #define EXTRACT_FMT_6_ADDX_CODE \
473 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
474 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
475 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
476 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
478 #define EXTRACT_FMT_7_BC8_VARS \
479 /* Instruction fields. */ \
484 #define EXTRACT_FMT_7_BC8_CODE \
486 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
487 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
488 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
490 #define EXTRACT_FMT_8_BC24_VARS \
491 /* Instruction fields. */ \
496 #define EXTRACT_FMT_8_BC24_CODE \
498 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
499 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
500 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
502 #define EXTRACT_FMT_9_BEQ_VARS \
503 /* Instruction fields. */ \
510 #define EXTRACT_FMT_9_BEQ_CODE \
512 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
513 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
514 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
515 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
516 f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
518 #define EXTRACT_FMT_10_BEQZ_VARS \
519 /* Instruction fields. */ \
526 #define EXTRACT_FMT_10_BEQZ_CODE \
528 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
529 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
530 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
531 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
532 f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
534 #define EXTRACT_FMT_11_BL8_VARS \
535 /* Instruction fields. */ \
540 #define EXTRACT_FMT_11_BL8_CODE \
542 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
543 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
544 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
546 #define EXTRACT_FMT_12_BL24_VARS \
547 /* Instruction fields. */ \
552 #define EXTRACT_FMT_12_BL24_CODE \
554 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
555 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
556 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
558 #define EXTRACT_FMT_13_BCL8_VARS \
559 /* Instruction fields. */ \
564 #define EXTRACT_FMT_13_BCL8_CODE \
566 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
567 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
568 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
570 #define EXTRACT_FMT_14_BCL24_VARS \
571 /* Instruction fields. */ \
576 #define EXTRACT_FMT_14_BCL24_CODE \
578 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
579 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
580 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
582 #define EXTRACT_FMT_15_BRA8_VARS \
583 /* Instruction fields. */ \
588 #define EXTRACT_FMT_15_BRA8_CODE \
590 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
591 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
592 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
594 #define EXTRACT_FMT_16_BRA24_VARS \
595 /* Instruction fields. */ \
600 #define EXTRACT_FMT_16_BRA24_CODE \
602 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
603 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
604 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
606 #define EXTRACT_FMT_17_CMP_VARS \
607 /* Instruction fields. */ \
613 #define EXTRACT_FMT_17_CMP_CODE \
615 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
616 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
617 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
618 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
620 #define EXTRACT_FMT_18_CMPI_VARS \
621 /* Instruction fields. */ \
628 #define EXTRACT_FMT_18_CMPI_CODE \
630 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
631 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
632 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
633 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
634 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
636 #define EXTRACT_FMT_19_CMPUI_VARS \
637 /* Instruction fields. */ \
644 #define EXTRACT_FMT_19_CMPUI_CODE \
646 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
647 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
648 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
649 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
650 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
652 #define EXTRACT_FMT_20_CMPZ_VARS \
653 /* Instruction fields. */ \
659 #define EXTRACT_FMT_20_CMPZ_CODE \
661 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
662 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
663 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
664 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
666 #define EXTRACT_FMT_21_DIV_VARS \
667 /* Instruction fields. */ \
674 #define EXTRACT_FMT_21_DIV_CODE \
676 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
677 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
678 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
679 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
680 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
682 #define EXTRACT_FMT_22_JC_VARS \
683 /* Instruction fields. */ \
689 #define EXTRACT_FMT_22_JC_CODE \
691 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
692 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
693 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
694 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
696 #define EXTRACT_FMT_23_JL_VARS \
697 /* Instruction fields. */ \
703 #define EXTRACT_FMT_23_JL_CODE \
705 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
706 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
707 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
708 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
710 #define EXTRACT_FMT_24_JMP_VARS \
711 /* Instruction fields. */ \
717 #define EXTRACT_FMT_24_JMP_CODE \
719 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
720 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
721 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
722 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
724 #define EXTRACT_FMT_25_LD_VARS \
725 /* Instruction fields. */ \
731 #define EXTRACT_FMT_25_LD_CODE \
733 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
734 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
735 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
736 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
738 #define EXTRACT_FMT_26_LD_D_VARS \
739 /* Instruction fields. */ \
746 #define EXTRACT_FMT_26_LD_D_CODE \
748 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
749 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
750 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
751 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
752 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
754 #define EXTRACT_FMT_27_LDB_VARS \
755 /* Instruction fields. */ \
761 #define EXTRACT_FMT_27_LDB_CODE \
763 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
764 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
765 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
766 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
768 #define EXTRACT_FMT_28_LDB_D_VARS \
769 /* Instruction fields. */ \
776 #define EXTRACT_FMT_28_LDB_D_CODE \
778 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
779 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
780 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
781 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
782 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
784 #define EXTRACT_FMT_29_LDH_VARS \
785 /* Instruction fields. */ \
791 #define EXTRACT_FMT_29_LDH_CODE \
793 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
794 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
795 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
796 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
798 #define EXTRACT_FMT_30_LDH_D_VARS \
799 /* Instruction fields. */ \
806 #define EXTRACT_FMT_30_LDH_D_CODE \
808 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
809 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
810 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
811 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
812 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
814 #define EXTRACT_FMT_31_LD24_VARS \
815 /* Instruction fields. */ \
820 #define EXTRACT_FMT_31_LD24_CODE \
822 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
823 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
824 f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
826 #define EXTRACT_FMT_32_LDI8_VARS \
827 /* Instruction fields. */ \
832 #define EXTRACT_FMT_32_LDI8_CODE \
834 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
835 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
836 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
838 #define EXTRACT_FMT_33_LDI16_VARS \
839 /* Instruction fields. */ \
846 #define EXTRACT_FMT_33_LDI16_CODE \
848 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
849 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
850 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
851 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
852 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
854 #define EXTRACT_FMT_34_MACHI_A_VARS \
855 /* Instruction fields. */ \
862 #define EXTRACT_FMT_34_MACHI_A_CODE \
864 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
865 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
866 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
867 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
868 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
870 #define EXTRACT_FMT_35_MULHI_A_VARS \
871 /* Instruction fields. */ \
878 #define EXTRACT_FMT_35_MULHI_A_CODE \
880 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
881 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
882 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
883 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
884 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
886 #define EXTRACT_FMT_36_MV_VARS \
887 /* Instruction fields. */ \
893 #define EXTRACT_FMT_36_MV_CODE \
895 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
896 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
897 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
898 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
900 #define EXTRACT_FMT_37_MVFACHI_A_VARS \
901 /* Instruction fields. */ \
908 #define EXTRACT_FMT_37_MVFACHI_A_CODE \
910 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
911 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
912 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
913 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
914 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
916 #define EXTRACT_FMT_38_MVFC_VARS \
917 /* Instruction fields. */ \
923 #define EXTRACT_FMT_38_MVFC_CODE \
925 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
926 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
927 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
928 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
930 #define EXTRACT_FMT_39_MVTACHI_A_VARS \
931 /* Instruction fields. */ \
938 #define EXTRACT_FMT_39_MVTACHI_A_CODE \
940 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
941 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
942 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
943 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
944 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
946 #define EXTRACT_FMT_40_MVTC_VARS \
947 /* Instruction fields. */ \
953 #define EXTRACT_FMT_40_MVTC_CODE \
955 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
956 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
957 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
958 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
960 #define EXTRACT_FMT_41_NOP_VARS \
961 /* Instruction fields. */ \
967 #define EXTRACT_FMT_41_NOP_CODE \
969 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
970 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
971 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
972 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
974 #define EXTRACT_FMT_42_RAC_D_VARS \
975 /* Instruction fields. */ \
984 #define EXTRACT_FMT_42_RAC_D_CODE \
986 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
987 f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
988 f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
989 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
990 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
991 f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
992 f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \
994 #define EXTRACT_FMT_43_RAC_DS_VARS \
995 /* Instruction fields. */ \
1003 unsigned int length;
1004 #define EXTRACT_FMT_43_RAC_DS_CODE \
1006 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1007 f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
1008 f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
1009 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1010 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1011 f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
1012 f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \
1014 #define EXTRACT_FMT_44_RAC_DSI_VARS \
1015 /* Instruction fields. */ \
1023 unsigned int length;
1024 #define EXTRACT_FMT_44_RAC_DSI_CODE \
1026 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1027 f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
1028 f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
1029 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1030 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1031 f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
1032 f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \
1034 #define EXTRACT_FMT_45_RTE_VARS \
1035 /* Instruction fields. */ \
1040 unsigned int length;
1041 #define EXTRACT_FMT_45_RTE_CODE \
1043 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1044 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1045 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1046 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1048 #define EXTRACT_FMT_46_SETH_VARS \
1049 /* Instruction fields. */ \
1055 unsigned int length;
1056 #define EXTRACT_FMT_46_SETH_CODE \
1058 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1059 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1060 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1061 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1062 f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1064 #define EXTRACT_FMT_47_SLLI_VARS \
1065 /* Instruction fields. */ \
1070 unsigned int length;
1071 #define EXTRACT_FMT_47_SLLI_CODE \
1073 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1074 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1075 f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1076 f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1078 #define EXTRACT_FMT_48_ST_D_VARS \
1079 /* Instruction fields. */ \
1085 unsigned int length;
1086 #define EXTRACT_FMT_48_ST_D_CODE \
1088 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1089 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1090 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1091 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1092 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1094 #define EXTRACT_FMT_49_TRAP_VARS \
1095 /* Instruction fields. */ \
1100 unsigned int length;
1101 #define EXTRACT_FMT_49_TRAP_CODE \
1103 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1104 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1105 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1106 f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1108 #define EXTRACT_FMT_50_SATB_VARS \
1109 /* Instruction fields. */ \
1115 unsigned int length;
1116 #define EXTRACT_FMT_50_SATB_CODE \
1118 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1119 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1120 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1121 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1122 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1124 #define EXTRACT_FMT_51_SAT_VARS \
1125 /* Instruction fields. */ \
1131 unsigned int length;
1132 #define EXTRACT_FMT_51_SAT_CODE \
1134 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1135 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1136 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1137 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1138 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1140 #define EXTRACT_FMT_52_SADD_VARS \
1141 /* Instruction fields. */ \
1146 unsigned int length;
1147 #define EXTRACT_FMT_52_SADD_CODE \
1149 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1150 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1151 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1152 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1154 #define EXTRACT_FMT_53_MACWU1_VARS \
1155 /* Instruction fields. */ \
1160 unsigned int length;
1161 #define EXTRACT_FMT_53_MACWU1_CODE \
1163 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1164 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1165 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1166 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1168 #define EXTRACT_FMT_54_MSBLO_VARS \
1169 /* Instruction fields. */ \
1174 unsigned int length;
1175 #define EXTRACT_FMT_54_MSBLO_CODE \
1177 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1178 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1179 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1180 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1182 #define EXTRACT_FMT_55_SC_VARS \
1183 /* Instruction fields. */ \
1188 unsigned int length;
1189 #define EXTRACT_FMT_55_SC_CODE \
1191 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1192 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1193 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1194 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1196 /* Fetched input values of an instruction. */
1200 struct { /* e.g. add $dr,$sr */
1204 struct { /* e.g. add3 $dr,$sr,#$slo16 */
1208 struct { /* e.g. and3 $dr,$sr,#$uimm16 */
1212 struct { /* e.g. or3 $dr,$sr,#$ulo16 */
1216 struct { /* e.g. addi $dr,#$simm8 */
1220 struct { /* e.g. addv3 $dr,$sr,#$simm16 */
1224 struct { /* e.g. addx $dr,$sr */
1229 struct { /* e.g. bc $disp8 */
1233 struct { /* e.g. bc $disp24 */
1237 struct { /* e.g. beq $src1,$src2,$disp16 */
1242 struct { /* e.g. beqz $src2,$disp16 */
1246 struct { /* e.g. bl $disp8 */
1250 struct { /* e.g. bl $disp24 */
1254 struct { /* e.g. bcl $disp8 */
1259 struct { /* e.g. bcl $disp24 */
1264 struct { /* e.g. bra $disp8 */
1267 struct { /* e.g. bra $disp24 */
1270 struct { /* e.g. cmp $src1,$src2 */
1274 struct { /* e.g. cmpi $src2,#$simm16 */
1278 struct { /* e.g. cmpui $src2,#$uimm16 */
1282 struct { /* e.g. cmpz $src2 */
1285 struct { /* e.g. div $dr,$sr */
1289 struct { /* e.g. jc $sr */
1293 struct { /* e.g. jl $sr */
1297 struct { /* e.g. jmp $sr */
1300 struct { /* e.g. ld $dr,@$sr */
1304 struct { /* e.g. ld $dr,@($slo16,$sr) */
1305 UQI h_memory_add_WI_sr_slo16;
1309 struct { /* e.g. ldb $dr,@$sr */
1313 struct { /* e.g. ldb $dr,@($slo16,$sr) */
1314 UQI h_memory_add_WI_sr_slo16;
1318 struct { /* e.g. ldh $dr,@$sr */
1322 struct { /* e.g. ldh $dr,@($slo16,$sr) */
1323 UQI h_memory_add_WI_sr_slo16;
1327 struct { /* e.g. ld24 $dr,#$uimm24 */
1330 struct { /* e.g. ldi $dr,#$simm8 */
1333 struct { /* e.g. ldi $dr,$slo16 */
1336 struct { /* e.g. machi $src1,$src2,$acc */
1341 struct { /* e.g. mulhi $src1,$src2,$acc */
1345 struct { /* e.g. mv $dr,$sr */
1348 struct { /* e.g. mvfachi $dr,$accs */
1351 struct { /* e.g. mvfc $dr,$scr */
1354 struct { /* e.g. mvtachi $src1,$accs */
1358 struct { /* e.g. mvtc $sr,$dcr */
1361 struct { /* e.g. nop */
1364 struct { /* e.g. rac $accd */
1367 struct { /* e.g. rac $accd,$accs */
1370 struct { /* e.g. rac $accd,$accs,#$imm1 */
1374 struct { /* e.g. rte */
1380 struct { /* e.g. seth $dr,#$hi16 */
1383 struct { /* e.g. slli $dr,#$uimm5 */
1387 struct { /* e.g. st $src1,@($slo16,$src2) */
1392 struct { /* e.g. trap #$uimm4 */
1395 struct { /* e.g. satb $dr,$src2 */
1398 struct { /* e.g. sat $dr,$src2 */
1402 struct { /* e.g. sadd */
1406 struct { /* e.g. macwu1 $src1,$src2 */
1411 struct { /* e.g. msblo $src1,$src2 */
1416 struct { /* e.g. sc */
1422 #endif /* CPU_M32RX_H */