1 /* CPU family header for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2010, 2012 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 2
35 /* The size of an "int" needed to hold an instruction word.
36 This is usually 32 bits, but some architectures needs 64 bits. */
37 typedef CGEN_INSN_INT CGEN_INSN_WORD;
39 #include "cgen-engine.h"
41 /* CPU state information. */
43 /* Hardware elements. */
47 #define GET_H_PC() CPU (h_pc)
48 #define SET_H_PC(x) (CPU (h_pc) = (x))
49 /* general registers */
51 #define GET_H_GR(a1) CPU (h_gr)[a1]
52 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
53 /* control registers */
55 #define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
56 #define SET_H_CR(index, x) \
58 m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
62 #define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
63 #define SET_H_ACCUM(x) \
65 m32rxf_h_accum_set_handler (current_cpu, (x));\
69 #define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
70 #define SET_H_ACCUMS(index, x) \
72 m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
76 #define GET_H_COND() CPU (h_cond)
77 #define SET_H_COND(x) (CPU (h_cond) = (x))
80 #define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
81 #define SET_H_PSW(x) \
83 m32rxf_h_psw_set_handler (current_cpu, (x));\
87 #define GET_H_BPSW() CPU (h_bpsw)
88 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
91 #define GET_H_BBPSW() CPU (h_bbpsw)
92 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
95 #define GET_H_LOCK() CPU (h_lock)
96 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
98 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
101 /* Cover fns for register access. */
102 USI m32rxf_h_pc_get (SIM_CPU *);
103 void m32rxf_h_pc_set (SIM_CPU *, USI);
104 SI m32rxf_h_gr_get (SIM_CPU *, UINT);
105 void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
106 USI m32rxf_h_cr_get (SIM_CPU *, UINT);
107 void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
108 DI m32rxf_h_accum_get (SIM_CPU *);
109 void m32rxf_h_accum_set (SIM_CPU *, DI);
110 DI m32rxf_h_accums_get (SIM_CPU *, UINT);
111 void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
112 BI m32rxf_h_cond_get (SIM_CPU *);
113 void m32rxf_h_cond_set (SIM_CPU *, BI);
114 UQI m32rxf_h_psw_get (SIM_CPU *);
115 void m32rxf_h_psw_set (SIM_CPU *, UQI);
116 UQI m32rxf_h_bpsw_get (SIM_CPU *);
117 void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
118 UQI m32rxf_h_bbpsw_get (SIM_CPU *);
119 void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
120 BI m32rxf_h_lock_get (SIM_CPU *);
121 void m32rxf_h_lock_set (SIM_CPU *, BI);
123 /* These must be hand-written. */
124 extern CPUREG_FETCH_FN m32rxf_fetch_register;
125 extern CPUREG_STORE_FN m32rxf_store_register;
131 /* Instruction argument buffer. */
134 struct { /* no operands */
145 unsigned char out_h_gr_SI_14;
149 unsigned char out_h_gr_SI_14;
160 unsigned char out_dr;
166 unsigned char in_src1;
172 unsigned char out_dr;
178 unsigned char out_dr;
184 unsigned char out_h_gr_SI_14;
198 unsigned char out_dr;
205 unsigned char out_dr;
212 unsigned char in_src1;
213 unsigned char in_src2;
214 unsigned char out_src2;
222 unsigned char in_src1;
223 unsigned char in_src2;
231 unsigned char in_src1;
232 unsigned char in_src2;
240 unsigned char out_dr;
241 unsigned char out_sr;
249 unsigned char in_src1;
250 unsigned char in_src2;
259 unsigned char out_dr;
268 unsigned char out_dr;
277 unsigned char out_dr;
280 /* Writeback handler. */
282 /* Pointer to argbuf entry for insn whose results need writing back. */
283 const struct argbuf *abuf;
285 /* x-before handler */
287 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
290 /* x-after handler */
294 /* This entry is used to terminate each pbb. */
296 /* Number of insns in pbb. */
298 /* Next pbb to execute. */
300 SCACHE *branch_target;
305 /* The ARGBUF struct. */
307 /* These are the baseclass definitions. */
312 /* ??? Temporary hack for skip insns. */
315 /* cpu specific data follows */
318 union sem_fields fields;
323 ??? SCACHE used to contain more than just argbuf. We could delete the
324 type entirely and always just use ARGBUF, but for future concerns and as
325 a level of abstraction it is left in. */
328 struct argbuf argbuf;
331 /* Macros to simplify extraction, reading and semantic code.
332 These define and assign the local vars that contain the insn's fields. */
334 #define EXTRACT_IFMT_EMPTY_VARS \
336 #define EXTRACT_IFMT_EMPTY_CODE \
339 #define EXTRACT_IFMT_ADD_VARS \
345 #define EXTRACT_IFMT_ADD_CODE \
347 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
348 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
349 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
350 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
352 #define EXTRACT_IFMT_ADD3_VARS \
359 #define EXTRACT_IFMT_ADD3_CODE \
361 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
362 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
363 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
364 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
365 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
367 #define EXTRACT_IFMT_AND3_VARS \
374 #define EXTRACT_IFMT_AND3_CODE \
376 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
377 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
378 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
379 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
380 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
382 #define EXTRACT_IFMT_OR3_VARS \
389 #define EXTRACT_IFMT_OR3_CODE \
391 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
392 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
393 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
394 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
395 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
397 #define EXTRACT_IFMT_ADDI_VARS \
402 #define EXTRACT_IFMT_ADDI_CODE \
404 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
405 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
406 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
408 #define EXTRACT_IFMT_ADDV3_VARS \
415 #define EXTRACT_IFMT_ADDV3_CODE \
417 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
418 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
419 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
420 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
421 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
423 #define EXTRACT_IFMT_BC8_VARS \
428 #define EXTRACT_IFMT_BC8_CODE \
430 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
431 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
432 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
434 #define EXTRACT_IFMT_BC24_VARS \
439 #define EXTRACT_IFMT_BC24_CODE \
441 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
442 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
443 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
445 #define EXTRACT_IFMT_BEQ_VARS \
452 #define EXTRACT_IFMT_BEQ_CODE \
454 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
455 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
456 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
457 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
458 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
460 #define EXTRACT_IFMT_BEQZ_VARS \
467 #define EXTRACT_IFMT_BEQZ_CODE \
469 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
470 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
471 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
472 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
473 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
475 #define EXTRACT_IFMT_CMP_VARS \
481 #define EXTRACT_IFMT_CMP_CODE \
483 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
484 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
485 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
486 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
488 #define EXTRACT_IFMT_CMPI_VARS \
495 #define EXTRACT_IFMT_CMPI_CODE \
497 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
498 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
499 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
500 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
501 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
503 #define EXTRACT_IFMT_CMPZ_VARS \
509 #define EXTRACT_IFMT_CMPZ_CODE \
511 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
512 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
513 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
514 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
516 #define EXTRACT_IFMT_DIV_VARS \
523 #define EXTRACT_IFMT_DIV_CODE \
525 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
526 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
527 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
528 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
529 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
531 #define EXTRACT_IFMT_JC_VARS \
537 #define EXTRACT_IFMT_JC_CODE \
539 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
540 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
541 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
542 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
544 #define EXTRACT_IFMT_LD24_VARS \
549 #define EXTRACT_IFMT_LD24_CODE \
551 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
552 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
553 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
555 #define EXTRACT_IFMT_LDI16_VARS \
562 #define EXTRACT_IFMT_LDI16_CODE \
564 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
565 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
566 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
567 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
568 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
570 #define EXTRACT_IFMT_MACHI_A_VARS \
577 #define EXTRACT_IFMT_MACHI_A_CODE \
579 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
580 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
581 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
582 f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
583 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
585 #define EXTRACT_IFMT_MVFACHI_A_VARS \
592 #define EXTRACT_IFMT_MVFACHI_A_CODE \
594 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
595 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
596 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
597 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
598 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
600 #define EXTRACT_IFMT_MVFC_VARS \
606 #define EXTRACT_IFMT_MVFC_CODE \
608 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
609 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
610 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
611 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
613 #define EXTRACT_IFMT_MVTACHI_A_VARS \
620 #define EXTRACT_IFMT_MVTACHI_A_CODE \
622 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
623 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
624 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
625 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
626 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
628 #define EXTRACT_IFMT_MVTC_VARS \
634 #define EXTRACT_IFMT_MVTC_CODE \
636 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
637 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
638 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
639 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
641 #define EXTRACT_IFMT_NOP_VARS \
647 #define EXTRACT_IFMT_NOP_CODE \
649 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
650 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
651 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
652 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
654 #define EXTRACT_IFMT_RAC_DSI_VARS \
663 #define EXTRACT_IFMT_RAC_DSI_CODE \
665 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
666 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
667 f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
668 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
669 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
670 f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
671 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
673 #define EXTRACT_IFMT_SETH_VARS \
680 #define EXTRACT_IFMT_SETH_CODE \
682 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
683 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
684 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
685 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
686 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
688 #define EXTRACT_IFMT_SLLI_VARS \
694 #define EXTRACT_IFMT_SLLI_CODE \
696 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
697 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
698 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
699 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
701 #define EXTRACT_IFMT_ST_D_VARS \
708 #define EXTRACT_IFMT_ST_D_CODE \
710 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
711 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
712 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
713 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
714 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
716 #define EXTRACT_IFMT_TRAP_VARS \
722 #define EXTRACT_IFMT_TRAP_CODE \
724 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
725 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
726 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
727 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
729 #define EXTRACT_IFMT_SATB_VARS \
736 #define EXTRACT_IFMT_SATB_CODE \
738 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
739 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
740 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
741 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
742 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
744 #define EXTRACT_IFMT_CLRPSW_VARS \
749 #define EXTRACT_IFMT_CLRPSW_CODE \
751 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
752 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
753 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
755 #define EXTRACT_IFMT_BSET_VARS \
763 #define EXTRACT_IFMT_BSET_CODE \
765 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
766 f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
767 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
768 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
769 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
770 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
772 #define EXTRACT_IFMT_BTST_VARS \
779 #define EXTRACT_IFMT_BTST_CODE \
781 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
782 f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
783 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
784 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
785 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
787 /* Queued output values of an instruction. */
791 struct { /* empty sformat for unspecified field list */
794 struct { /* e.g. add $dr,$sr */
797 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
800 struct { /* e.g. and3 $dr,$sr,$uimm16 */
803 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
806 struct { /* e.g. addi $dr,$simm8 */
809 struct { /* e.g. addv $dr,$sr */
813 struct { /* e.g. addv3 $dr,$sr,$simm16 */
817 struct { /* e.g. addx $dr,$sr */
821 struct { /* e.g. bc.s $disp8 */
824 struct { /* e.g. bc.l $disp24 */
827 struct { /* e.g. beq $src1,$src2,$disp16 */
830 struct { /* e.g. beqz $src2,$disp16 */
833 struct { /* e.g. bl.s $disp8 */
837 struct { /* e.g. bl.l $disp24 */
841 struct { /* e.g. bcl.s $disp8 */
845 struct { /* e.g. bcl.l $disp24 */
849 struct { /* e.g. bra.s $disp8 */
852 struct { /* e.g. bra.l $disp24 */
855 struct { /* e.g. cmp $src1,$src2 */
858 struct { /* e.g. cmpi $src2,$simm16 */
861 struct { /* e.g. cmpz $src2 */
864 struct { /* e.g. div $dr,$sr */
867 struct { /* e.g. jc $sr */
870 struct { /* e.g. jl $sr */
874 struct { /* e.g. jmp $sr */
877 struct { /* e.g. ld $dr,@$sr */
880 struct { /* e.g. ld $dr,@($slo16,$sr) */
883 struct { /* e.g. ldb $dr,@$sr */
886 struct { /* e.g. ldb $dr,@($slo16,$sr) */
889 struct { /* e.g. ldh $dr,@$sr */
892 struct { /* e.g. ldh $dr,@($slo16,$sr) */
895 struct { /* e.g. ld $dr,@$sr+ */
899 struct { /* e.g. ld24 $dr,$uimm24 */
902 struct { /* e.g. ldi8 $dr,$simm8 */
905 struct { /* e.g. ldi16 $dr,$hash$slo16 */
908 struct { /* e.g. lock $dr,@$sr */
912 struct { /* e.g. machi $src1,$src2,$acc */
915 struct { /* e.g. mulhi $src1,$src2,$acc */
918 struct { /* e.g. mv $dr,$sr */
921 struct { /* e.g. mvfachi $dr,$accs */
924 struct { /* e.g. mvfc $dr,$scr */
927 struct { /* e.g. mvtachi $src1,$accs */
930 struct { /* e.g. mvtc $sr,$dcr */
933 struct { /* e.g. nop */
936 struct { /* e.g. rac $accd,$accs,$imm1 */
939 struct { /* e.g. rte */
945 struct { /* e.g. seth $dr,$hash$hi16 */
948 struct { /* e.g. sll3 $dr,$sr,$simm16 */
951 struct { /* e.g. slli $dr,$uimm5 */
954 struct { /* e.g. st $src1,@$src2 */
956 USI h_memory_SI_src2_idx;
958 struct { /* e.g. st $src1,@($slo16,$src2) */
959 SI h_memory_SI_add__SI_src2_slo16;
960 USI h_memory_SI_add__SI_src2_slo16_idx;
962 struct { /* e.g. stb $src1,@$src2 */
964 USI h_memory_QI_src2_idx;
966 struct { /* e.g. stb $src1,@($slo16,$src2) */
967 QI h_memory_QI_add__SI_src2_slo16;
968 USI h_memory_QI_add__SI_src2_slo16_idx;
970 struct { /* e.g. sth $src1,@$src2 */
972 USI h_memory_HI_src2_idx;
974 struct { /* e.g. sth $src1,@($slo16,$src2) */
975 HI h_memory_HI_add__SI_src2_slo16;
976 USI h_memory_HI_add__SI_src2_slo16_idx;
978 struct { /* e.g. st $src1,@+$src2 */
979 SI h_memory_SI_new_src2;
980 USI h_memory_SI_new_src2_idx;
983 struct { /* e.g. sth $src1,@$src2+ */
984 HI h_memory_HI_new_src2;
985 USI h_memory_HI_new_src2_idx;
988 struct { /* e.g. stb $src1,@$src2+ */
989 QI h_memory_QI_new_src2;
990 USI h_memory_QI_new_src2_idx;
993 struct { /* e.g. trap $uimm4 */
1001 struct { /* e.g. unlock $src1,@$src2 */
1003 SI h_memory_SI_src2;
1004 USI h_memory_SI_src2_idx;
1006 struct { /* e.g. satb $dr,$sr */
1009 struct { /* e.g. sat $dr,$sr */
1012 struct { /* e.g. sadd */
1015 struct { /* e.g. macwu1 $src1,$src2 */
1018 struct { /* e.g. msblo $src1,$src2 */
1021 struct { /* e.g. mulwu1 $src1,$src2 */
1024 struct { /* e.g. sc */
1027 struct { /* e.g. clrpsw $uimm8 */
1030 struct { /* e.g. setpsw $uimm8 */
1033 struct { /* e.g. bset $uimm3,@($slo16,$sr) */
1034 QI h_memory_QI_add__SI_sr_slo16;
1035 USI h_memory_QI_add__SI_sr_slo16_idx;
1037 struct { /* e.g. btst $uimm3,$sr */
1041 /* For conditionally written operands, bitmask of which ones were. */
1045 /* Collection of various things for the trace handler to use. */
1047 typedef struct trace_record {
1052 #endif /* CPU_M32RXF_H */