1 /* CPU family header for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 2
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 #define GET_H_CR(a1) CPU (h_cr)[a1]
50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
53 #define GET_H_ACCUM() CPU (h_accum)
54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
55 /* start-sanitize-m32rx */
58 /* end-sanitize-m32rx */
59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
63 #define GET_H_COND() CPU (h_cond)
64 #define SET_H_COND(x) (CPU (h_cond) = (x))
67 #define GET_H_PSW() CPU (h_psw)
68 #define SET_H_PSW(x) (CPU (h_psw) = (x))
71 #define GET_H_BPSW() CPU (h_bpsw)
72 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
75 #define GET_H_BBPSW() CPU (h_bbpsw)
76 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
79 #define GET_H_LOCK() CPU (h_lock)
80 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
82 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
85 /* Cover fns for register access. */
86 USI m32rxf_h_pc_get (SIM_CPU *);
87 void m32rxf_h_pc_set (SIM_CPU *, USI);
88 SI m32rxf_h_gr_get (SIM_CPU *, UINT);
89 void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
90 USI m32rxf_h_cr_get (SIM_CPU *, UINT);
91 void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
92 DI m32rxf_h_accum_get (SIM_CPU *);
93 void m32rxf_h_accum_set (SIM_CPU *, DI);
94 DI m32rxf_h_accums_get (SIM_CPU *, UINT);
95 void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
96 BI m32rxf_h_cond_get (SIM_CPU *);
97 void m32rxf_h_cond_set (SIM_CPU *, BI);
98 UQI m32rxf_h_psw_get (SIM_CPU *);
99 void m32rxf_h_psw_set (SIM_CPU *, UQI);
100 UQI m32rxf_h_bpsw_get (SIM_CPU *);
101 void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
102 UQI m32rxf_h_bbpsw_get (SIM_CPU *);
103 void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
104 BI m32rxf_h_lock_get (SIM_CPU *);
105 void m32rxf_h_lock_set (SIM_CPU *, BI);
107 /* These must be hand-written. */
108 extern CPUREG_FETCH_FN m32rxf_fetch_register;
109 extern CPUREG_STORE_FN m32rxf_store_register;
115 /* The ARGBUF struct. */
117 /* These are the baseclass definitions. */
120 /* cpu specific data follows */
124 struct { /* e.g. add $dr,$sr */
129 unsigned char out_dr;
131 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
136 unsigned char out_dr;
138 struct { /* e.g. and3 $dr,$sr,$uimm16 */
143 unsigned char out_dr;
145 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
150 unsigned char out_dr;
152 struct { /* e.g. addi $dr,$simm8 */
156 unsigned char out_dr;
158 struct { /* e.g. addv $dr,$sr */
163 unsigned char out_dr;
165 struct { /* e.g. addv3 $dr,$sr,$simm16 */
170 unsigned char out_dr;
172 struct { /* e.g. addx $dr,$sr */
177 unsigned char out_dr;
179 struct { /* e.g. cmp $src1,$src2 */
182 unsigned char in_src1;
183 unsigned char in_src2;
185 struct { /* e.g. cmpi $src2,$simm16 */
188 unsigned char in_src2;
190 struct { /* e.g. cmpz $src2 */
192 unsigned char in_src2;
194 struct { /* e.g. div $dr,$sr */
199 unsigned char out_dr;
201 struct { /* e.g. ld $dr,@$sr */
205 unsigned char out_dr;
207 struct { /* e.g. ld $dr,@($slo16,$sr) */
212 unsigned char out_dr;
214 struct { /* e.g. ldb $dr,@$sr */
218 unsigned char out_dr;
220 struct { /* e.g. ldb $dr,@($slo16,$sr) */
225 unsigned char out_dr;
227 struct { /* e.g. ldh $dr,@$sr */
231 unsigned char out_dr;
233 struct { /* e.g. ldh $dr,@($slo16,$sr) */
238 unsigned char out_dr;
240 struct { /* e.g. ld $dr,@$sr+ */
244 unsigned char out_dr;
245 unsigned char out_sr;
247 struct { /* e.g. ld24 $dr,$uimm24 */
250 unsigned char out_dr;
252 struct { /* e.g. ldi8 $dr,$simm8 */
255 unsigned char out_dr;
257 struct { /* e.g. ldi16 $dr,$hash$slo16 */
260 unsigned char out_dr;
262 struct { /* e.g. lock $dr,@$sr */
266 unsigned char out_dr;
268 struct { /* e.g. machi $src1,$src2,$acc */
272 unsigned char in_src1;
273 unsigned char in_src2;
275 struct { /* e.g. mulhi $src1,$src2,$acc */
279 unsigned char in_src1;
280 unsigned char in_src2;
282 struct { /* e.g. mv $dr,$sr */
286 unsigned char out_dr;
288 struct { /* e.g. mvfachi $dr,$accs */
291 unsigned char out_dr;
293 struct { /* e.g. mvfc $dr,$scr */
296 unsigned char out_dr;
298 struct { /* e.g. mvtachi $src1,$accs */
301 unsigned char in_src1;
303 struct { /* e.g. mvtc $sr,$dcr */
308 struct { /* e.g. nop */
311 struct { /* e.g. rac $accd,$accs,$imm1 */
316 struct { /* e.g. seth $dr,$hash$hi16 */
319 unsigned char out_dr;
321 struct { /* e.g. sll3 $dr,$sr,$simm16 */
326 unsigned char out_dr;
328 struct { /* e.g. slli $dr,$uimm5 */
332 unsigned char out_dr;
334 struct { /* e.g. st $src1,@$src2 */
337 unsigned char in_src2;
338 unsigned char in_src1;
340 struct { /* e.g. st $src1,@($slo16,$src2) */
344 unsigned char in_src2;
345 unsigned char in_src1;
347 struct { /* e.g. stb $src1,@$src2 */
350 unsigned char in_src2;
351 unsigned char in_src1;
353 struct { /* e.g. stb $src1,@($slo16,$src2) */
357 unsigned char in_src2;
358 unsigned char in_src1;
360 struct { /* e.g. sth $src1,@$src2 */
363 unsigned char in_src2;
364 unsigned char in_src1;
366 struct { /* e.g. sth $src1,@($slo16,$src2) */
370 unsigned char in_src2;
371 unsigned char in_src1;
373 struct { /* e.g. st $src1,@+$src2 */
376 unsigned char in_src2;
377 unsigned char in_src1;
378 unsigned char out_src2;
380 struct { /* e.g. unlock $src1,@$src2 */
383 unsigned char in_src2;
384 unsigned char in_src1;
386 struct { /* e.g. satb $dr,$sr */
390 unsigned char out_dr;
392 struct { /* e.g. sat $dr,$sr */
396 unsigned char out_dr;
398 struct { /* e.g. sadd */
401 struct { /* e.g. macwu1 $src1,$src2 */
404 unsigned char in_src1;
405 unsigned char in_src2;
407 struct { /* e.g. msblo $src1,$src2 */
410 unsigned char in_src1;
411 unsigned char in_src2;
413 struct { /* e.g. mulwu1 $src1,$src2 */
416 unsigned char in_src1;
417 unsigned char in_src2;
419 /* cti insns, kept separately so addr_cache is in fixed place */
422 struct { /* e.g. bc.s $disp8 */
425 struct { /* e.g. bc.l $disp24 */
428 struct { /* e.g. beq $src1,$src2,$disp16 */
432 unsigned char in_src1;
433 unsigned char in_src2;
435 struct { /* e.g. beqz $src2,$disp16 */
438 unsigned char in_src2;
440 struct { /* e.g. bl.s $disp8 */
442 unsigned char out_h_gr_14;
444 struct { /* e.g. bl.l $disp24 */
446 unsigned char out_h_gr_14;
448 struct { /* e.g. bcl.s $disp8 */
450 unsigned char out_h_gr_14;
452 struct { /* e.g. bcl.l $disp24 */
454 unsigned char out_h_gr_14;
456 struct { /* e.g. bra.s $disp8 */
459 struct { /* e.g. bra.l $disp24 */
462 struct { /* e.g. jc $sr */
466 struct { /* e.g. jl $sr */
469 unsigned char out_h_gr_14;
471 struct { /* e.g. jmp $sr */
475 struct { /* e.g. rte */
478 struct { /* e.g. trap $uimm4 */
481 struct { /* e.g. sc */
485 #if WITH_SCACHE_PBB_M32RXF
489 #if WITH_SCACHE_PBB_M32RXF
490 /* Writeback handler. */
492 /* Pointer to argbuf entry for insn whose results need writing back. */
493 const struct argbuf *abuf;
495 /* x-before handler */
497 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
500 /* x-after handler */
504 /* This entry is used to terminate each pbb. */
506 /* Number of insns in pbb. */
508 /* Next pbb to execute. */
517 ??? SCACHE used to contain more than just argbuf. We could delete the
518 type entirely and always just use ARGBUF, but for future concerns and as
519 a level of abstraction it is left in. */
522 struct argbuf argbuf;
525 /* Macros to simplify extraction, reading and semantic code.
526 These define and assign the local vars that contain the insn's fields. */
528 #define EXTRACT_FMT_ADD_VARS \
529 /* Instruction fields. */ \
535 #define EXTRACT_FMT_ADD_CODE \
537 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
538 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
539 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
540 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
542 #define EXTRACT_FMT_ADD3_VARS \
543 /* Instruction fields. */ \
550 #define EXTRACT_FMT_ADD3_CODE \
552 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
553 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
554 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
555 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
556 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
558 #define EXTRACT_FMT_AND3_VARS \
559 /* Instruction fields. */ \
566 #define EXTRACT_FMT_AND3_CODE \
568 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
569 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
570 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
571 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
572 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
574 #define EXTRACT_FMT_OR3_VARS \
575 /* Instruction fields. */ \
582 #define EXTRACT_FMT_OR3_CODE \
584 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
585 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
586 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
587 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
588 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
590 #define EXTRACT_FMT_ADDI_VARS \
591 /* Instruction fields. */ \
596 #define EXTRACT_FMT_ADDI_CODE \
598 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
599 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
600 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
602 #define EXTRACT_FMT_ADDV_VARS \
603 /* Instruction fields. */ \
609 #define EXTRACT_FMT_ADDV_CODE \
611 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
612 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
613 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
614 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
616 #define EXTRACT_FMT_ADDV3_VARS \
617 /* Instruction fields. */ \
624 #define EXTRACT_FMT_ADDV3_CODE \
626 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
627 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
628 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
629 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
630 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
632 #define EXTRACT_FMT_ADDX_VARS \
633 /* Instruction fields. */ \
639 #define EXTRACT_FMT_ADDX_CODE \
641 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
642 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
643 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
644 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
646 #define EXTRACT_FMT_BC8_VARS \
647 /* Instruction fields. */ \
652 #define EXTRACT_FMT_BC8_CODE \
654 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
655 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
656 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
658 #define EXTRACT_FMT_BC24_VARS \
659 /* Instruction fields. */ \
664 #define EXTRACT_FMT_BC24_CODE \
666 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
667 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
668 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
670 #define EXTRACT_FMT_BEQ_VARS \
671 /* Instruction fields. */ \
678 #define EXTRACT_FMT_BEQ_CODE \
680 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
681 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
682 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
683 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
684 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
686 #define EXTRACT_FMT_BEQZ_VARS \
687 /* Instruction fields. */ \
694 #define EXTRACT_FMT_BEQZ_CODE \
696 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
697 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
698 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
699 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
700 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
702 #define EXTRACT_FMT_BL8_VARS \
703 /* Instruction fields. */ \
708 #define EXTRACT_FMT_BL8_CODE \
710 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
711 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
712 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
714 #define EXTRACT_FMT_BL24_VARS \
715 /* Instruction fields. */ \
720 #define EXTRACT_FMT_BL24_CODE \
722 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
723 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
724 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
726 #define EXTRACT_FMT_BCL8_VARS \
727 /* Instruction fields. */ \
732 #define EXTRACT_FMT_BCL8_CODE \
734 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
735 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
736 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
738 #define EXTRACT_FMT_BCL24_VARS \
739 /* Instruction fields. */ \
744 #define EXTRACT_FMT_BCL24_CODE \
746 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
747 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
748 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
750 #define EXTRACT_FMT_BRA8_VARS \
751 /* Instruction fields. */ \
756 #define EXTRACT_FMT_BRA8_CODE \
758 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
759 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
760 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
762 #define EXTRACT_FMT_BRA24_VARS \
763 /* Instruction fields. */ \
768 #define EXTRACT_FMT_BRA24_CODE \
770 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
771 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
772 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
774 #define EXTRACT_FMT_CMP_VARS \
775 /* Instruction fields. */ \
781 #define EXTRACT_FMT_CMP_CODE \
783 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
784 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
785 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
786 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
788 #define EXTRACT_FMT_CMPI_VARS \
789 /* Instruction fields. */ \
796 #define EXTRACT_FMT_CMPI_CODE \
798 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
799 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
800 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
801 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
802 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
804 #define EXTRACT_FMT_CMPZ_VARS \
805 /* Instruction fields. */ \
811 #define EXTRACT_FMT_CMPZ_CODE \
813 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
814 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
815 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
816 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
818 #define EXTRACT_FMT_DIV_VARS \
819 /* Instruction fields. */ \
826 #define EXTRACT_FMT_DIV_CODE \
828 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
829 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
830 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
831 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
832 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
834 #define EXTRACT_FMT_JC_VARS \
835 /* Instruction fields. */ \
841 #define EXTRACT_FMT_JC_CODE \
843 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
844 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
845 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
846 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
848 #define EXTRACT_FMT_JL_VARS \
849 /* Instruction fields. */ \
855 #define EXTRACT_FMT_JL_CODE \
857 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
858 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
859 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
860 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
862 #define EXTRACT_FMT_JMP_VARS \
863 /* Instruction fields. */ \
869 #define EXTRACT_FMT_JMP_CODE \
871 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
872 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
873 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
874 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
876 #define EXTRACT_FMT_LD_VARS \
877 /* Instruction fields. */ \
883 #define EXTRACT_FMT_LD_CODE \
885 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
886 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
887 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
888 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
890 #define EXTRACT_FMT_LD_D_VARS \
891 /* Instruction fields. */ \
898 #define EXTRACT_FMT_LD_D_CODE \
900 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
901 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
902 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
903 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
904 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
906 #define EXTRACT_FMT_LDB_VARS \
907 /* Instruction fields. */ \
913 #define EXTRACT_FMT_LDB_CODE \
915 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
916 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
917 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
918 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
920 #define EXTRACT_FMT_LDB_D_VARS \
921 /* Instruction fields. */ \
928 #define EXTRACT_FMT_LDB_D_CODE \
930 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
931 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
932 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
933 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
934 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
936 #define EXTRACT_FMT_LDH_VARS \
937 /* Instruction fields. */ \
943 #define EXTRACT_FMT_LDH_CODE \
945 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
946 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
947 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
948 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
950 #define EXTRACT_FMT_LDH_D_VARS \
951 /* Instruction fields. */ \
958 #define EXTRACT_FMT_LDH_D_CODE \
960 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
961 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
962 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
963 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
964 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
966 #define EXTRACT_FMT_LD_PLUS_VARS \
967 /* Instruction fields. */ \
973 #define EXTRACT_FMT_LD_PLUS_CODE \
975 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
976 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
977 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
978 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
980 #define EXTRACT_FMT_LD24_VARS \
981 /* Instruction fields. */ \
986 #define EXTRACT_FMT_LD24_CODE \
988 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
989 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
990 f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
992 #define EXTRACT_FMT_LDI8_VARS \
993 /* Instruction fields. */ \
998 #define EXTRACT_FMT_LDI8_CODE \
1000 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1001 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1002 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
1004 #define EXTRACT_FMT_LDI16_VARS \
1005 /* Instruction fields. */ \
1011 unsigned int length;
1012 #define EXTRACT_FMT_LDI16_CODE \
1014 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1015 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1016 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1017 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1018 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1020 #define EXTRACT_FMT_LOCK_VARS \
1021 /* Instruction fields. */ \
1026 unsigned int length;
1027 #define EXTRACT_FMT_LOCK_CODE \
1029 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1030 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1031 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1032 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1034 #define EXTRACT_FMT_MACHI_A_VARS \
1035 /* Instruction fields. */ \
1041 unsigned int length;
1042 #define EXTRACT_FMT_MACHI_A_CODE \
1044 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1045 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1046 f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1047 f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1048 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1050 #define EXTRACT_FMT_MULHI_A_VARS \
1051 /* Instruction fields. */ \
1057 unsigned int length;
1058 #define EXTRACT_FMT_MULHI_A_CODE \
1060 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1061 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1062 f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1063 f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1064 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1066 #define EXTRACT_FMT_MV_VARS \
1067 /* Instruction fields. */ \
1072 unsigned int length;
1073 #define EXTRACT_FMT_MV_CODE \
1075 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1076 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1077 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1078 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1080 #define EXTRACT_FMT_MVFACHI_A_VARS \
1081 /* Instruction fields. */ \
1087 unsigned int length;
1088 #define EXTRACT_FMT_MVFACHI_A_CODE \
1090 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1091 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1092 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1093 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1094 f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1096 #define EXTRACT_FMT_MVFC_VARS \
1097 /* Instruction fields. */ \
1102 unsigned int length;
1103 #define EXTRACT_FMT_MVFC_CODE \
1105 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1106 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1107 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1108 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1110 #define EXTRACT_FMT_MVTACHI_A_VARS \
1111 /* Instruction fields. */ \
1117 unsigned int length;
1118 #define EXTRACT_FMT_MVTACHI_A_CODE \
1120 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1121 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1122 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1123 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1124 f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1126 #define EXTRACT_FMT_MVTC_VARS \
1127 /* Instruction fields. */ \
1132 unsigned int length;
1133 #define EXTRACT_FMT_MVTC_CODE \
1135 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1136 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1137 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1138 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1140 #define EXTRACT_FMT_NOP_VARS \
1141 /* Instruction fields. */ \
1146 unsigned int length;
1147 #define EXTRACT_FMT_NOP_CODE \
1149 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1150 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1151 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1152 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1154 #define EXTRACT_FMT_RAC_DSI_VARS \
1155 /* Instruction fields. */ \
1163 unsigned int length;
1164 #define EXTRACT_FMT_RAC_DSI_CODE \
1166 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1167 f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
1168 f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
1169 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1170 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1171 f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
1172 f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
1174 #define EXTRACT_FMT_RTE_VARS \
1175 /* Instruction fields. */ \
1180 unsigned int length;
1181 #define EXTRACT_FMT_RTE_CODE \
1183 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1184 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1185 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1186 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1188 #define EXTRACT_FMT_SETH_VARS \
1189 /* Instruction fields. */ \
1195 unsigned int length;
1196 #define EXTRACT_FMT_SETH_CODE \
1198 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1199 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1200 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1201 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1202 f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1204 #define EXTRACT_FMT_SLL3_VARS \
1205 /* Instruction fields. */ \
1211 unsigned int length;
1212 #define EXTRACT_FMT_SLL3_CODE \
1214 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1215 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1216 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1217 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1218 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1220 #define EXTRACT_FMT_SLLI_VARS \
1221 /* Instruction fields. */ \
1226 unsigned int length;
1227 #define EXTRACT_FMT_SLLI_CODE \
1229 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1230 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1231 f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1232 f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1234 #define EXTRACT_FMT_ST_VARS \
1235 /* Instruction fields. */ \
1240 unsigned int length;
1241 #define EXTRACT_FMT_ST_CODE \
1243 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1244 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1245 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1246 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1248 #define EXTRACT_FMT_ST_D_VARS \
1249 /* Instruction fields. */ \
1255 unsigned int length;
1256 #define EXTRACT_FMT_ST_D_CODE \
1258 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1259 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1260 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1261 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1262 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1264 #define EXTRACT_FMT_STB_VARS \
1265 /* Instruction fields. */ \
1270 unsigned int length;
1271 #define EXTRACT_FMT_STB_CODE \
1273 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1274 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1275 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1276 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1278 #define EXTRACT_FMT_STB_D_VARS \
1279 /* Instruction fields. */ \
1285 unsigned int length;
1286 #define EXTRACT_FMT_STB_D_CODE \
1288 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1289 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1290 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1291 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1292 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1294 #define EXTRACT_FMT_STH_VARS \
1295 /* Instruction fields. */ \
1300 unsigned int length;
1301 #define EXTRACT_FMT_STH_CODE \
1303 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1304 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1305 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1306 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1308 #define EXTRACT_FMT_STH_D_VARS \
1309 /* Instruction fields. */ \
1315 unsigned int length;
1316 #define EXTRACT_FMT_STH_D_CODE \
1318 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1319 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1320 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1321 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1322 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1324 #define EXTRACT_FMT_ST_PLUS_VARS \
1325 /* Instruction fields. */ \
1330 unsigned int length;
1331 #define EXTRACT_FMT_ST_PLUS_CODE \
1333 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1334 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1335 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1336 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1338 #define EXTRACT_FMT_TRAP_VARS \
1339 /* Instruction fields. */ \
1344 unsigned int length;
1345 #define EXTRACT_FMT_TRAP_CODE \
1347 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1348 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1349 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1350 f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1352 #define EXTRACT_FMT_UNLOCK_VARS \
1353 /* Instruction fields. */ \
1358 unsigned int length;
1359 #define EXTRACT_FMT_UNLOCK_CODE \
1361 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1362 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1363 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1364 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1366 #define EXTRACT_FMT_SATB_VARS \
1367 /* Instruction fields. */ \
1373 unsigned int length;
1374 #define EXTRACT_FMT_SATB_CODE \
1376 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1377 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1378 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1379 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1380 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1382 #define EXTRACT_FMT_SAT_VARS \
1383 /* Instruction fields. */ \
1389 unsigned int length;
1390 #define EXTRACT_FMT_SAT_CODE \
1392 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1393 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1394 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1395 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1396 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1398 #define EXTRACT_FMT_SADD_VARS \
1399 /* Instruction fields. */ \
1404 unsigned int length;
1405 #define EXTRACT_FMT_SADD_CODE \
1407 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1408 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1409 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1410 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1412 #define EXTRACT_FMT_MACWU1_VARS \
1413 /* Instruction fields. */ \
1418 unsigned int length;
1419 #define EXTRACT_FMT_MACWU1_CODE \
1421 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1422 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1423 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1424 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1426 #define EXTRACT_FMT_MSBLO_VARS \
1427 /* Instruction fields. */ \
1432 unsigned int length;
1433 #define EXTRACT_FMT_MSBLO_CODE \
1435 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1436 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1437 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1438 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1440 #define EXTRACT_FMT_MULWU1_VARS \
1441 /* Instruction fields. */ \
1446 unsigned int length;
1447 #define EXTRACT_FMT_MULWU1_CODE \
1449 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1450 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1451 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1452 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1454 #define EXTRACT_FMT_SC_VARS \
1455 /* Instruction fields. */ \
1460 unsigned int length;
1461 #define EXTRACT_FMT_SC_CODE \
1463 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1464 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1465 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1466 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1468 /* Queued output values of an instruction. */
1472 struct { /* e.g. add $dr,$sr */
1475 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
1478 struct { /* e.g. and3 $dr,$sr,$uimm16 */
1481 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
1484 struct { /* e.g. addi $dr,$simm8 */
1487 struct { /* e.g. addv $dr,$sr */
1491 struct { /* e.g. addv3 $dr,$sr,$simm16 */
1495 struct { /* e.g. addx $dr,$sr */
1499 struct { /* e.g. bc.s $disp8 */
1502 struct { /* e.g. bc.l $disp24 */
1505 struct { /* e.g. beq $src1,$src2,$disp16 */
1508 struct { /* e.g. beqz $src2,$disp16 */
1511 struct { /* e.g. bl.s $disp8 */
1515 struct { /* e.g. bl.l $disp24 */
1519 struct { /* e.g. bcl.s $disp8 */
1523 struct { /* e.g. bcl.l $disp24 */
1527 struct { /* e.g. bra.s $disp8 */
1530 struct { /* e.g. bra.l $disp24 */
1533 struct { /* e.g. cmp $src1,$src2 */
1536 struct { /* e.g. cmpi $src2,$simm16 */
1539 struct { /* e.g. cmpz $src2 */
1542 struct { /* e.g. div $dr,$sr */
1545 struct { /* e.g. jc $sr */
1548 struct { /* e.g. jl $sr */
1552 struct { /* e.g. jmp $sr */
1555 struct { /* e.g. ld $dr,@$sr */
1558 struct { /* e.g. ld $dr,@($slo16,$sr) */
1561 struct { /* e.g. ldb $dr,@$sr */
1564 struct { /* e.g. ldb $dr,@($slo16,$sr) */
1567 struct { /* e.g. ldh $dr,@$sr */
1570 struct { /* e.g. ldh $dr,@($slo16,$sr) */
1573 struct { /* e.g. ld $dr,@$sr+ */
1577 struct { /* e.g. ld24 $dr,$uimm24 */
1580 struct { /* e.g. ldi8 $dr,$simm8 */
1583 struct { /* e.g. ldi16 $dr,$hash$slo16 */
1586 struct { /* e.g. lock $dr,@$sr */
1590 struct { /* e.g. machi $src1,$src2,$acc */
1593 struct { /* e.g. mulhi $src1,$src2,$acc */
1596 struct { /* e.g. mv $dr,$sr */
1599 struct { /* e.g. mvfachi $dr,$accs */
1602 struct { /* e.g. mvfc $dr,$scr */
1605 struct { /* e.g. mvtachi $src1,$accs */
1608 struct { /* e.g. mvtc $sr,$dcr */
1611 struct { /* e.g. nop */
1614 struct { /* e.g. rac $accd,$accs,$imm1 */
1617 struct { /* e.g. rte */
1623 struct { /* e.g. seth $dr,$hash$hi16 */
1626 struct { /* e.g. sll3 $dr,$sr,$simm16 */
1629 struct { /* e.g. slli $dr,$uimm5 */
1632 struct { /* e.g. st $src1,@$src2 */
1634 USI h_memory_src2_idx;
1636 struct { /* e.g. st $src1,@($slo16,$src2) */
1637 SI h_memory_add__VM_src2_slo16;
1638 USI h_memory_add__VM_src2_slo16_idx;
1640 struct { /* e.g. stb $src1,@$src2 */
1642 USI h_memory_src2_idx;
1644 struct { /* e.g. stb $src1,@($slo16,$src2) */
1645 QI h_memory_add__VM_src2_slo16;
1646 USI h_memory_add__VM_src2_slo16_idx;
1648 struct { /* e.g. sth $src1,@$src2 */
1650 USI h_memory_src2_idx;
1652 struct { /* e.g. sth $src1,@($slo16,$src2) */
1653 HI h_memory_add__VM_src2_slo16;
1654 USI h_memory_add__VM_src2_slo16_idx;
1656 struct { /* e.g. st $src1,@+$src2 */
1657 SI h_memory_new_src2;
1658 USI h_memory_new_src2_idx;
1661 struct { /* e.g. trap $uimm4 */
1669 struct { /* e.g. unlock $src1,@$src2 */
1671 USI h_memory_src2_idx;
1674 struct { /* e.g. satb $dr,$sr */
1677 struct { /* e.g. sat $dr,$sr */
1680 struct { /* e.g. sadd */
1683 struct { /* e.g. macwu1 $src1,$src2 */
1686 struct { /* e.g. msblo $src1,$src2 */
1689 struct { /* e.g. mulwu1 $src1,$src2 */
1692 struct { /* e.g. sc */
1696 /* For conditionally written operands, bitmask of which ones were. */
1700 /* Collection of various things for the trace handler to use. */
1702 typedef struct trace_record {
1707 #endif /* CPU_M32RXF_H */