1 /* CPU family header for m32rx.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 2
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 #define GET_H_CR(a1) CPU (h_cr)[a1]
50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
53 #define GET_H_ACCUM() CPU (h_accum)
54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
55 /* start-sanitize-m32rx */
58 /* end-sanitize-m32rx */
59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
63 #define GET_H_COND() CPU (h_cond)
64 #define SET_H_COND(x) (CPU (h_cond) = (x))
67 #define GET_H_SM() CPU (h_sm)
68 #define SET_H_SM(x) (CPU (h_sm) = (x))
71 #define GET_H_BSM() CPU (h_bsm)
72 #define SET_H_BSM(x) (CPU (h_bsm) = (x))
75 #define GET_H_IE() CPU (h_ie)
76 #define SET_H_IE(x) (CPU (h_ie) = (x))
79 #define GET_H_BIE() CPU (h_bie)
80 #define SET_H_BIE(x) (CPU (h_bie) = (x))
83 #define GET_H_BCOND() CPU (h_bcond)
84 #define SET_H_BCOND(x) (CPU (h_bcond) = (x))
87 #define GET_H_BPC() CPU (h_bpc)
88 #define SET_H_BPC(x) (CPU (h_bpc) = (x))
91 #define GET_H_LOCK() CPU (h_lock)
92 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
94 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
95 /* CPU profiling state information. */
97 /* general registers */
100 #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
103 USI m32rx_h_pc_get (SIM_CPU *);
104 void m32rx_h_pc_set (SIM_CPU *, USI);
105 SI m32rx_h_gr_get (SIM_CPU *, UINT);
106 void m32rx_h_gr_set (SIM_CPU *, UINT, SI);
107 USI m32rx_h_cr_get (SIM_CPU *, UINT);
108 void m32rx_h_cr_set (SIM_CPU *, UINT, USI);
109 DI m32rx_h_accum_get (SIM_CPU *);
110 void m32rx_h_accum_set (SIM_CPU *, DI);
111 DI m32rx_h_accums_get (SIM_CPU *, UINT);
112 void m32rx_h_accums_set (SIM_CPU *, UINT, DI);
113 UBI m32rx_h_cond_get (SIM_CPU *);
114 void m32rx_h_cond_set (SIM_CPU *, UBI);
115 UBI m32rx_h_sm_get (SIM_CPU *);
116 void m32rx_h_sm_set (SIM_CPU *, UBI);
117 UBI m32rx_h_bsm_get (SIM_CPU *);
118 void m32rx_h_bsm_set (SIM_CPU *, UBI);
119 UBI m32rx_h_ie_get (SIM_CPU *);
120 void m32rx_h_ie_set (SIM_CPU *, UBI);
121 UBI m32rx_h_bie_get (SIM_CPU *);
122 void m32rx_h_bie_set (SIM_CPU *, UBI);
123 UBI m32rx_h_bcond_get (SIM_CPU *);
124 void m32rx_h_bcond_set (SIM_CPU *, UBI);
125 SI m32rx_h_bpc_get (SIM_CPU *);
126 void m32rx_h_bpc_set (SIM_CPU *, SI);
127 UBI m32rx_h_lock_get (SIM_CPU *);
128 void m32rx_h_lock_set (SIM_CPU *, UBI);
130 /* These must be hand-written. */
131 extern CPUREG_FETCH_FN m32rx_fetch_register;
132 extern CPUREG_STORE_FN m32rx_store_register;
134 /* The ARGBUF struct. */
136 /* These are the baseclass definitions. */
140 /* cpu specific data follows */
143 struct { /* e.g. add $dr,$sr */
147 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
152 struct { /* e.g. and3 $dr,$sr,$uimm16 */
157 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
162 struct { /* e.g. addi $dr,$simm8 */
166 struct { /* e.g. addv $dr,$sr */
170 struct { /* e.g. addv3 $dr,$sr,$simm16 */
175 struct { /* e.g. addx $dr,$sr */
179 struct { /* e.g. bc.s $disp8 */
182 struct { /* e.g. bc.l $disp24 */
185 struct { /* e.g. beq $src1,$src2,$disp16 */
190 struct { /* e.g. beqz $src2,$disp16 */
194 struct { /* e.g. bl.s $disp8 */
197 struct { /* e.g. bl.l $disp24 */
200 struct { /* e.g. bcl.s $disp8 */
203 struct { /* e.g. bcl.l $disp24 */
206 struct { /* e.g. bra.s $disp8 */
209 struct { /* e.g. bra.l $disp24 */
212 struct { /* e.g. cmp $src1,$src2 */
216 struct { /* e.g. cmpi $src2,$simm16 */
220 struct { /* e.g. cmpz $src2 */
223 struct { /* e.g. div $dr,$sr */
227 struct { /* e.g. jc $sr */
230 struct { /* e.g. jl $sr */
233 struct { /* e.g. jmp $sr */
236 struct { /* e.g. ld $dr,@$sr */
240 struct { /* e.g. ld $dr,@($slo16,$sr) */
245 struct { /* e.g. ldb $dr,@$sr */
249 struct { /* e.g. ldb $dr,@($slo16,$sr) */
254 struct { /* e.g. ldh $dr,@$sr */
258 struct { /* e.g. ldh $dr,@($slo16,$sr) */
263 struct { /* e.g. ld $dr,@$sr+ */
267 struct { /* e.g. ld24 $dr,$uimm24 */
271 struct { /* e.g. ldi8 $dr,$simm8 */
275 struct { /* e.g. ldi16 $dr,$hash$slo16 */
279 struct { /* e.g. lock $dr,@$sr */
283 struct { /* e.g. machi $src1,$src2,$acc */
288 struct { /* e.g. macwhi $src1,$src2 */
292 struct { /* e.g. mulhi $src1,$src2,$acc */
297 struct { /* e.g. mulwhi $src1,$src2 */
301 struct { /* e.g. mv $dr,$sr */
305 struct { /* e.g. mvfachi $dr,$accs */
309 struct { /* e.g. mvfc $dr,$scr */
313 struct { /* e.g. mvtachi $src1,$accs */
317 struct { /* e.g. mvtc $sr,$dcr */
321 struct { /* e.g. nop */
324 struct { /* e.g. rac $accd,$accs,$imm1 */
329 struct { /* e.g. rte */
332 struct { /* e.g. seth $dr,$hash$hi16 */
336 struct { /* e.g. sll3 $dr,$sr,$simm16 */
341 struct { /* e.g. slli $dr,$uimm5 */
345 struct { /* e.g. st $src1,@$src2 */
349 struct { /* e.g. st $src1,@($slo16,$src2) */
354 struct { /* e.g. stb $src1,@$src2 */
358 struct { /* e.g. stb $src1,@($slo16,$src2) */
363 struct { /* e.g. sth $src1,@$src2 */
367 struct { /* e.g. sth $src1,@($slo16,$src2) */
372 struct { /* e.g. st $src1,@+$src2 */
376 struct { /* e.g. trap $uimm4 */
379 struct { /* e.g. unlock $src1,@$src2 */
383 struct { /* e.g. satb $dr,$sr */
387 struct { /* e.g. sat $dr,$sr */
391 struct { /* e.g. sadd */
394 struct { /* e.g. macwu1 $src1,$src2 */
398 struct { /* e.g. mulwu1 $src1,$src2 */
402 struct { /* e.g. sc */
406 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
407 unsigned long h_gr_get;
408 unsigned long h_gr_set;
413 This is currently also used in the non-scache case. In this situation we
414 assume the cache size is 1, and do a few things a little differently. */
415 /* FIXME: non-scache version to be redone. */
420 #if ! WITH_SEM_SWITCH_FULL
421 SEMANTIC_FN *sem_full;
423 #if ! WITH_SEM_SWITCH_FAST
424 SEMANTIC_FN *sem_fast;
426 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
434 struct argbuf argbuf;
437 /* Macros to simplify extraction, reading and semantic code.
438 These define and assign the local vars that contain the insn's fields. */
440 #define EXTRACT_FMT_ADD_VARS \
441 /* Instruction fields. */ \
447 #define EXTRACT_FMT_ADD_CODE \
449 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
450 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
451 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
452 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
454 #define EXTRACT_FMT_ADD3_VARS \
455 /* Instruction fields. */ \
462 #define EXTRACT_FMT_ADD3_CODE \
464 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
465 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
466 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
467 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
468 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
470 #define EXTRACT_FMT_AND3_VARS \
471 /* Instruction fields. */ \
478 #define EXTRACT_FMT_AND3_CODE \
480 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
481 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
482 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
483 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
484 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
486 #define EXTRACT_FMT_OR3_VARS \
487 /* Instruction fields. */ \
494 #define EXTRACT_FMT_OR3_CODE \
496 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
497 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
498 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
499 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
500 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
502 #define EXTRACT_FMT_ADDI_VARS \
503 /* Instruction fields. */ \
508 #define EXTRACT_FMT_ADDI_CODE \
510 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
511 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
512 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
514 #define EXTRACT_FMT_ADDV_VARS \
515 /* Instruction fields. */ \
521 #define EXTRACT_FMT_ADDV_CODE \
523 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
524 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
525 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
526 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
528 #define EXTRACT_FMT_ADDV3_VARS \
529 /* Instruction fields. */ \
536 #define EXTRACT_FMT_ADDV3_CODE \
538 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
539 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
540 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
541 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
542 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
544 #define EXTRACT_FMT_ADDX_VARS \
545 /* Instruction fields. */ \
551 #define EXTRACT_FMT_ADDX_CODE \
553 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
554 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
555 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
556 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
558 #define EXTRACT_FMT_BC8_VARS \
559 /* Instruction fields. */ \
564 #define EXTRACT_FMT_BC8_CODE \
566 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
567 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
568 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
570 #define EXTRACT_FMT_BC24_VARS \
571 /* Instruction fields. */ \
576 #define EXTRACT_FMT_BC24_CODE \
578 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
579 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
580 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
582 #define EXTRACT_FMT_BEQ_VARS \
583 /* Instruction fields. */ \
590 #define EXTRACT_FMT_BEQ_CODE \
592 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
593 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
594 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
595 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
596 f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
598 #define EXTRACT_FMT_BEQZ_VARS \
599 /* Instruction fields. */ \
606 #define EXTRACT_FMT_BEQZ_CODE \
608 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
609 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
610 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
611 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
612 f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
614 #define EXTRACT_FMT_BL8_VARS \
615 /* Instruction fields. */ \
620 #define EXTRACT_FMT_BL8_CODE \
622 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
623 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
624 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
626 #define EXTRACT_FMT_BL24_VARS \
627 /* Instruction fields. */ \
632 #define EXTRACT_FMT_BL24_CODE \
634 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
635 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
636 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
638 #define EXTRACT_FMT_BCL8_VARS \
639 /* Instruction fields. */ \
644 #define EXTRACT_FMT_BCL8_CODE \
646 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
647 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
648 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
650 #define EXTRACT_FMT_BCL24_VARS \
651 /* Instruction fields. */ \
656 #define EXTRACT_FMT_BCL24_CODE \
658 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
659 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
660 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
662 #define EXTRACT_FMT_BRA8_VARS \
663 /* Instruction fields. */ \
668 #define EXTRACT_FMT_BRA8_CODE \
670 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
671 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
672 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
674 #define EXTRACT_FMT_BRA24_VARS \
675 /* Instruction fields. */ \
680 #define EXTRACT_FMT_BRA24_CODE \
682 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
683 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
684 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
686 #define EXTRACT_FMT_CMP_VARS \
687 /* Instruction fields. */ \
693 #define EXTRACT_FMT_CMP_CODE \
695 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
696 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
697 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
698 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
700 #define EXTRACT_FMT_CMPI_VARS \
701 /* Instruction fields. */ \
708 #define EXTRACT_FMT_CMPI_CODE \
710 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
711 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
712 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
713 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
714 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
716 #define EXTRACT_FMT_CMPZ_VARS \
717 /* Instruction fields. */ \
723 #define EXTRACT_FMT_CMPZ_CODE \
725 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
726 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
727 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
728 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
730 #define EXTRACT_FMT_DIV_VARS \
731 /* Instruction fields. */ \
738 #define EXTRACT_FMT_DIV_CODE \
740 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
741 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
742 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
743 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
744 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
746 #define EXTRACT_FMT_JC_VARS \
747 /* Instruction fields. */ \
753 #define EXTRACT_FMT_JC_CODE \
755 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
756 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
757 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
758 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
760 #define EXTRACT_FMT_JL_VARS \
761 /* Instruction fields. */ \
767 #define EXTRACT_FMT_JL_CODE \
769 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
770 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
771 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
772 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
774 #define EXTRACT_FMT_JMP_VARS \
775 /* Instruction fields. */ \
781 #define EXTRACT_FMT_JMP_CODE \
783 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
784 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
785 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
786 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
788 #define EXTRACT_FMT_LD_VARS \
789 /* Instruction fields. */ \
795 #define EXTRACT_FMT_LD_CODE \
797 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
798 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
799 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
800 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
802 #define EXTRACT_FMT_LD_D_VARS \
803 /* Instruction fields. */ \
810 #define EXTRACT_FMT_LD_D_CODE \
812 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
813 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
814 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
815 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
816 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
818 #define EXTRACT_FMT_LDB_VARS \
819 /* Instruction fields. */ \
825 #define EXTRACT_FMT_LDB_CODE \
827 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
828 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
829 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
830 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
832 #define EXTRACT_FMT_LDB_D_VARS \
833 /* Instruction fields. */ \
840 #define EXTRACT_FMT_LDB_D_CODE \
842 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
843 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
844 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
845 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
846 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
848 #define EXTRACT_FMT_LDH_VARS \
849 /* Instruction fields. */ \
855 #define EXTRACT_FMT_LDH_CODE \
857 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
858 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
859 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
860 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
862 #define EXTRACT_FMT_LDH_D_VARS \
863 /* Instruction fields. */ \
870 #define EXTRACT_FMT_LDH_D_CODE \
872 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
873 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
874 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
875 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
876 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
878 #define EXTRACT_FMT_LD_PLUS_VARS \
879 /* Instruction fields. */ \
885 #define EXTRACT_FMT_LD_PLUS_CODE \
887 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
888 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
889 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
890 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
892 #define EXTRACT_FMT_LD24_VARS \
893 /* Instruction fields. */ \
898 #define EXTRACT_FMT_LD24_CODE \
900 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
901 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
902 f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
904 #define EXTRACT_FMT_LDI8_VARS \
905 /* Instruction fields. */ \
910 #define EXTRACT_FMT_LDI8_CODE \
912 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
913 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
914 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
916 #define EXTRACT_FMT_LDI16_VARS \
917 /* Instruction fields. */ \
924 #define EXTRACT_FMT_LDI16_CODE \
926 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
927 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
928 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
929 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
930 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
932 #define EXTRACT_FMT_LOCK_VARS \
933 /* Instruction fields. */ \
939 #define EXTRACT_FMT_LOCK_CODE \
941 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
942 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
943 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
944 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
946 #define EXTRACT_FMT_MACHI_A_VARS \
947 /* Instruction fields. */ \
954 #define EXTRACT_FMT_MACHI_A_CODE \
956 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
957 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
958 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
959 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
960 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
962 #define EXTRACT_FMT_MACWHI_VARS \
963 /* Instruction fields. */ \
969 #define EXTRACT_FMT_MACWHI_CODE \
971 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
972 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
973 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
974 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
976 #define EXTRACT_FMT_MULHI_A_VARS \
977 /* Instruction fields. */ \
984 #define EXTRACT_FMT_MULHI_A_CODE \
986 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
987 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
988 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
989 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
990 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
992 #define EXTRACT_FMT_MULWHI_VARS \
993 /* Instruction fields. */ \
999 #define EXTRACT_FMT_MULWHI_CODE \
1001 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1002 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1003 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1004 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1006 #define EXTRACT_FMT_MV_VARS \
1007 /* Instruction fields. */ \
1012 unsigned int length;
1013 #define EXTRACT_FMT_MV_CODE \
1015 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1016 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1017 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1018 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1020 #define EXTRACT_FMT_MVFACHI_A_VARS \
1021 /* Instruction fields. */ \
1027 unsigned int length;
1028 #define EXTRACT_FMT_MVFACHI_A_CODE \
1030 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1031 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1032 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1033 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1034 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1036 #define EXTRACT_FMT_MVFC_VARS \
1037 /* Instruction fields. */ \
1042 unsigned int length;
1043 #define EXTRACT_FMT_MVFC_CODE \
1045 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1046 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1047 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1048 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1050 #define EXTRACT_FMT_MVTACHI_A_VARS \
1051 /* Instruction fields. */ \
1057 unsigned int length;
1058 #define EXTRACT_FMT_MVTACHI_A_CODE \
1060 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1061 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1062 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1063 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1064 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1066 #define EXTRACT_FMT_MVTC_VARS \
1067 /* Instruction fields. */ \
1072 unsigned int length;
1073 #define EXTRACT_FMT_MVTC_CODE \
1075 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1076 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1077 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1078 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1080 #define EXTRACT_FMT_NOP_VARS \
1081 /* Instruction fields. */ \
1086 unsigned int length;
1087 #define EXTRACT_FMT_NOP_CODE \
1089 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1090 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1091 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1092 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1094 #define EXTRACT_FMT_RAC_DSI_VARS \
1095 /* Instruction fields. */ \
1103 unsigned int length;
1104 #define EXTRACT_FMT_RAC_DSI_CODE \
1106 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1107 f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
1108 f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
1109 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1110 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1111 f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
1112 f_imm1 = ((EXTRACT_UNSIGNED (insn, 16, 15, 1)) + (1)); \
1114 #define EXTRACT_FMT_RTE_VARS \
1115 /* Instruction fields. */ \
1120 unsigned int length;
1121 #define EXTRACT_FMT_RTE_CODE \
1123 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1124 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1125 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1126 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1128 #define EXTRACT_FMT_SETH_VARS \
1129 /* Instruction fields. */ \
1135 unsigned int length;
1136 #define EXTRACT_FMT_SETH_CODE \
1138 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1139 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1140 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1141 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1142 f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1144 #define EXTRACT_FMT_SLL3_VARS \
1145 /* Instruction fields. */ \
1151 unsigned int length;
1152 #define EXTRACT_FMT_SLL3_CODE \
1154 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1155 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1156 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1157 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1158 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1160 #define EXTRACT_FMT_SLLI_VARS \
1161 /* Instruction fields. */ \
1166 unsigned int length;
1167 #define EXTRACT_FMT_SLLI_CODE \
1169 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1170 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1171 f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1172 f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1174 #define EXTRACT_FMT_ST_VARS \
1175 /* Instruction fields. */ \
1180 unsigned int length;
1181 #define EXTRACT_FMT_ST_CODE \
1183 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1184 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1185 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1186 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1188 #define EXTRACT_FMT_ST_D_VARS \
1189 /* Instruction fields. */ \
1195 unsigned int length;
1196 #define EXTRACT_FMT_ST_D_CODE \
1198 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1199 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1200 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1201 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1202 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1204 #define EXTRACT_FMT_STB_VARS \
1205 /* Instruction fields. */ \
1210 unsigned int length;
1211 #define EXTRACT_FMT_STB_CODE \
1213 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1214 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1215 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1216 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1218 #define EXTRACT_FMT_STB_D_VARS \
1219 /* Instruction fields. */ \
1225 unsigned int length;
1226 #define EXTRACT_FMT_STB_D_CODE \
1228 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1229 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1230 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1231 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1232 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1234 #define EXTRACT_FMT_STH_VARS \
1235 /* Instruction fields. */ \
1240 unsigned int length;
1241 #define EXTRACT_FMT_STH_CODE \
1243 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1244 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1245 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1246 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1248 #define EXTRACT_FMT_STH_D_VARS \
1249 /* Instruction fields. */ \
1255 unsigned int length;
1256 #define EXTRACT_FMT_STH_D_CODE \
1258 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1259 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1260 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1261 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1262 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1264 #define EXTRACT_FMT_ST_PLUS_VARS \
1265 /* Instruction fields. */ \
1270 unsigned int length;
1271 #define EXTRACT_FMT_ST_PLUS_CODE \
1273 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1274 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1275 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1276 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1278 #define EXTRACT_FMT_TRAP_VARS \
1279 /* Instruction fields. */ \
1284 unsigned int length;
1285 #define EXTRACT_FMT_TRAP_CODE \
1287 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1288 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1289 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1290 f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1292 #define EXTRACT_FMT_UNLOCK_VARS \
1293 /* Instruction fields. */ \
1298 unsigned int length;
1299 #define EXTRACT_FMT_UNLOCK_CODE \
1301 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1302 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1303 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1304 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1306 #define EXTRACT_FMT_SATB_VARS \
1307 /* Instruction fields. */ \
1313 unsigned int length;
1314 #define EXTRACT_FMT_SATB_CODE \
1316 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1317 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1318 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1319 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1320 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1322 #define EXTRACT_FMT_SAT_VARS \
1323 /* Instruction fields. */ \
1329 unsigned int length;
1330 #define EXTRACT_FMT_SAT_CODE \
1332 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1333 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1334 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1335 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1336 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1338 #define EXTRACT_FMT_SADD_VARS \
1339 /* Instruction fields. */ \
1344 unsigned int length;
1345 #define EXTRACT_FMT_SADD_CODE \
1347 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1348 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1349 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1350 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1352 #define EXTRACT_FMT_MACWU1_VARS \
1353 /* Instruction fields. */ \
1358 unsigned int length;
1359 #define EXTRACT_FMT_MACWU1_CODE \
1361 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1362 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1363 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1364 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1366 #define EXTRACT_FMT_MULWU1_VARS \
1367 /* Instruction fields. */ \
1372 unsigned int length;
1373 #define EXTRACT_FMT_MULWU1_CODE \
1375 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1376 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1377 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1378 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1380 #define EXTRACT_FMT_SC_VARS \
1381 /* Instruction fields. */ \
1386 unsigned int length;
1387 #define EXTRACT_FMT_SC_CODE \
1389 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1390 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1391 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1392 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1394 /* Fetched input values of an instruction. */
1398 struct { /* e.g. add $dr,$sr */
1402 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
1406 struct { /* e.g. and3 $dr,$sr,$uimm16 */
1410 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
1414 struct { /* e.g. addi $dr,$simm8 */
1418 struct { /* e.g. addv $dr,$sr */
1422 struct { /* e.g. addv3 $dr,$sr,$simm16 */
1426 struct { /* e.g. addx $dr,$sr */
1431 struct { /* e.g. bc.s $disp8 */
1435 struct { /* e.g. bc.l $disp24 */
1439 struct { /* e.g. beq $src1,$src2,$disp16 */
1444 struct { /* e.g. beqz $src2,$disp16 */
1448 struct { /* e.g. bl.s $disp8 */
1452 struct { /* e.g. bl.l $disp24 */
1456 struct { /* e.g. bcl.s $disp8 */
1461 struct { /* e.g. bcl.l $disp24 */
1466 struct { /* e.g. bra.s $disp8 */
1469 struct { /* e.g. bra.l $disp24 */
1472 struct { /* e.g. cmp $src1,$src2 */
1476 struct { /* e.g. cmpi $src2,$simm16 */
1480 struct { /* e.g. cmpz $src2 */
1483 struct { /* e.g. div $dr,$sr */
1487 struct { /* e.g. jc $sr */
1491 struct { /* e.g. jl $sr */
1495 struct { /* e.g. jmp $sr */
1498 struct { /* e.g. ld $dr,@$sr */
1502 struct { /* e.g. ld $dr,@($slo16,$sr) */
1503 SI h_memory_add__VM_sr_slo16;
1507 struct { /* e.g. ldb $dr,@$sr */
1511 struct { /* e.g. ldb $dr,@($slo16,$sr) */
1512 QI h_memory_add__VM_sr_slo16;
1516 struct { /* e.g. ldh $dr,@$sr */
1520 struct { /* e.g. ldh $dr,@($slo16,$sr) */
1521 HI h_memory_add__VM_sr_slo16;
1525 struct { /* e.g. ld $dr,@$sr+ */
1529 struct { /* e.g. ld24 $dr,$uimm24 */
1532 struct { /* e.g. ldi8 $dr,$simm8 */
1535 struct { /* e.g. ldi16 $dr,$hash$slo16 */
1538 struct { /* e.g. lock $dr,@$sr */
1542 struct { /* e.g. machi $src1,$src2,$acc */
1547 struct { /* e.g. macwhi $src1,$src2 */
1552 struct { /* e.g. mulhi $src1,$src2,$acc */
1556 struct { /* e.g. mulwhi $src1,$src2 */
1560 struct { /* e.g. mv $dr,$sr */
1563 struct { /* e.g. mvfachi $dr,$accs */
1566 struct { /* e.g. mvfc $dr,$scr */
1569 struct { /* e.g. mvtachi $src1,$accs */
1573 struct { /* e.g. mvtc $sr,$dcr */
1576 struct { /* e.g. nop */
1579 struct { /* e.g. rac $accd,$accs,$imm1 */
1583 struct { /* e.g. rte */
1589 struct { /* e.g. seth $dr,$hash$hi16 */
1592 struct { /* e.g. sll3 $dr,$sr,$simm16 */
1596 struct { /* e.g. slli $dr,$uimm5 */
1600 struct { /* e.g. st $src1,@$src2 */
1604 struct { /* e.g. st $src1,@($slo16,$src2) */
1609 struct { /* e.g. stb $src1,@$src2 */
1613 struct { /* e.g. stb $src1,@($slo16,$src2) */
1618 struct { /* e.g. sth $src1,@$src2 */
1622 struct { /* e.g. sth $src1,@($slo16,$src2) */
1627 struct { /* e.g. st $src1,@+$src2 */
1631 struct { /* e.g. trap $uimm4 */
1636 struct { /* e.g. unlock $src1,@$src2 */
1641 struct { /* e.g. satb $dr,$sr */
1644 struct { /* e.g. sat $dr,$sr */
1648 struct { /* e.g. sadd */
1652 struct { /* e.g. macwu1 $src1,$src2 */
1657 struct { /* e.g. mulwu1 $src1,$src2 */
1661 struct { /* e.g. sc */
1667 #endif /* CPU_M32RX_H */