1 /* CPU family header for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2017 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, see <http://www.gnu.org/licenses/>.
27 /* Maximum number of instructions that are fetched at a time.
28 This is for LIW type instructions sets (e.g. m32r). */
29 #define MAX_LIW_INSNS 2
31 /* Maximum number of instructions that can be executed in parallel. */
32 #define MAX_PARALLEL_INSNS 2
34 /* The size of an "int" needed to hold an instruction word.
35 This is usually 32 bits, but some architectures needs 64 bits. */
36 typedef CGEN_INSN_INT CGEN_INSN_WORD;
38 #include "cgen-engine.h"
40 /* CPU state information. */
42 /* Hardware elements. */
46 #define GET_H_PC() CPU (h_pc)
47 #define SET_H_PC(x) (CPU (h_pc) = (x))
48 /* general registers */
50 #define GET_H_GR(a1) CPU (h_gr)[a1]
51 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
52 /* control registers */
54 #define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
55 #define SET_H_CR(index, x) \
57 m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
61 #define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
62 #define SET_H_ACCUM(x) \
64 m32rxf_h_accum_set_handler (current_cpu, (x));\
68 #define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
69 #define SET_H_ACCUMS(index, x) \
71 m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
75 #define GET_H_COND() CPU (h_cond)
76 #define SET_H_COND(x) (CPU (h_cond) = (x))
79 #define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
80 #define SET_H_PSW(x) \
82 m32rxf_h_psw_set_handler (current_cpu, (x));\
86 #define GET_H_BPSW() CPU (h_bpsw)
87 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
90 #define GET_H_BBPSW() CPU (h_bbpsw)
91 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
94 #define GET_H_LOCK() CPU (h_lock)
95 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
97 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
100 /* Cover fns for register access. */
101 USI m32rxf_h_pc_get (SIM_CPU *);
102 void m32rxf_h_pc_set (SIM_CPU *, USI);
103 SI m32rxf_h_gr_get (SIM_CPU *, UINT);
104 void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
105 USI m32rxf_h_cr_get (SIM_CPU *, UINT);
106 void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
107 DI m32rxf_h_accum_get (SIM_CPU *);
108 void m32rxf_h_accum_set (SIM_CPU *, DI);
109 DI m32rxf_h_accums_get (SIM_CPU *, UINT);
110 void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
111 BI m32rxf_h_cond_get (SIM_CPU *);
112 void m32rxf_h_cond_set (SIM_CPU *, BI);
113 UQI m32rxf_h_psw_get (SIM_CPU *);
114 void m32rxf_h_psw_set (SIM_CPU *, UQI);
115 UQI m32rxf_h_bpsw_get (SIM_CPU *);
116 void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
117 UQI m32rxf_h_bbpsw_get (SIM_CPU *);
118 void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
119 BI m32rxf_h_lock_get (SIM_CPU *);
120 void m32rxf_h_lock_set (SIM_CPU *, BI);
122 /* These must be hand-written. */
123 extern CPUREG_FETCH_FN m32rxf_fetch_register;
124 extern CPUREG_STORE_FN m32rxf_store_register;
130 /* Instruction argument buffer. */
133 struct { /* no operands */
144 unsigned char out_h_gr_SI_14;
148 unsigned char out_h_gr_SI_14;
159 unsigned char out_dr;
165 unsigned char in_src1;
171 unsigned char out_dr;
177 unsigned char out_dr;
183 unsigned char out_h_gr_SI_14;
197 unsigned char out_dr;
204 unsigned char out_dr;
211 unsigned char in_src1;
212 unsigned char in_src2;
213 unsigned char out_src2;
221 unsigned char in_src1;
222 unsigned char in_src2;
230 unsigned char in_src1;
231 unsigned char in_src2;
239 unsigned char out_dr;
240 unsigned char out_sr;
248 unsigned char in_src1;
249 unsigned char in_src2;
258 unsigned char out_dr;
267 unsigned char out_dr;
276 unsigned char out_dr;
279 /* Writeback handler. */
281 /* Pointer to argbuf entry for insn whose results need writing back. */
282 const struct argbuf *abuf;
284 /* x-before handler */
286 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
289 /* x-after handler */
293 /* This entry is used to terminate each pbb. */
295 /* Number of insns in pbb. */
297 /* Next pbb to execute. */
299 SCACHE *branch_target;
304 /* The ARGBUF struct. */
306 /* These are the baseclass definitions. */
311 /* ??? Temporary hack for skip insns. */
314 /* cpu specific data follows */
317 union sem_fields fields;
322 ??? SCACHE used to contain more than just argbuf. We could delete the
323 type entirely and always just use ARGBUF, but for future concerns and as
324 a level of abstraction it is left in. */
327 struct argbuf argbuf;
330 /* Macros to simplify extraction, reading and semantic code.
331 These define and assign the local vars that contain the insn's fields. */
333 #define EXTRACT_IFMT_EMPTY_VARS \
335 #define EXTRACT_IFMT_EMPTY_CODE \
338 #define EXTRACT_IFMT_ADD_VARS \
344 #define EXTRACT_IFMT_ADD_CODE \
346 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
347 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
348 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
349 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
351 #define EXTRACT_IFMT_ADD3_VARS \
358 #define EXTRACT_IFMT_ADD3_CODE \
360 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
361 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
362 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
363 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
364 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
366 #define EXTRACT_IFMT_AND3_VARS \
373 #define EXTRACT_IFMT_AND3_CODE \
375 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
376 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
377 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
378 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
379 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
381 #define EXTRACT_IFMT_OR3_VARS \
388 #define EXTRACT_IFMT_OR3_CODE \
390 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
391 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
392 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
393 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
394 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
396 #define EXTRACT_IFMT_ADDI_VARS \
401 #define EXTRACT_IFMT_ADDI_CODE \
403 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
404 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
405 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
407 #define EXTRACT_IFMT_ADDV3_VARS \
414 #define EXTRACT_IFMT_ADDV3_CODE \
416 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
417 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
418 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
419 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
420 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
422 #define EXTRACT_IFMT_BC8_VARS \
427 #define EXTRACT_IFMT_BC8_CODE \
429 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
430 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
431 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
433 #define EXTRACT_IFMT_BC24_VARS \
438 #define EXTRACT_IFMT_BC24_CODE \
440 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
441 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
442 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
444 #define EXTRACT_IFMT_BEQ_VARS \
451 #define EXTRACT_IFMT_BEQ_CODE \
453 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
454 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
455 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
456 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
457 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
459 #define EXTRACT_IFMT_BEQZ_VARS \
466 #define EXTRACT_IFMT_BEQZ_CODE \
468 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
469 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
470 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
471 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
472 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
474 #define EXTRACT_IFMT_CMP_VARS \
480 #define EXTRACT_IFMT_CMP_CODE \
482 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
483 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
484 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
485 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
487 #define EXTRACT_IFMT_CMPI_VARS \
494 #define EXTRACT_IFMT_CMPI_CODE \
496 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
497 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
498 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
499 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
500 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
502 #define EXTRACT_IFMT_CMPZ_VARS \
508 #define EXTRACT_IFMT_CMPZ_CODE \
510 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
511 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
512 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
513 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
515 #define EXTRACT_IFMT_DIV_VARS \
522 #define EXTRACT_IFMT_DIV_CODE \
524 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
525 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
526 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
527 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
528 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
530 #define EXTRACT_IFMT_JC_VARS \
536 #define EXTRACT_IFMT_JC_CODE \
538 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
539 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
540 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
541 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
543 #define EXTRACT_IFMT_LD24_VARS \
548 #define EXTRACT_IFMT_LD24_CODE \
550 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
551 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
552 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
554 #define EXTRACT_IFMT_LDI16_VARS \
561 #define EXTRACT_IFMT_LDI16_CODE \
563 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
564 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
565 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
566 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
567 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
569 #define EXTRACT_IFMT_MACHI_A_VARS \
576 #define EXTRACT_IFMT_MACHI_A_CODE \
578 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
579 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
580 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
581 f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
582 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
584 #define EXTRACT_IFMT_MVFACHI_A_VARS \
591 #define EXTRACT_IFMT_MVFACHI_A_CODE \
593 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
594 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
595 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
596 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
597 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
599 #define EXTRACT_IFMT_MVFC_VARS \
605 #define EXTRACT_IFMT_MVFC_CODE \
607 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
608 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
609 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
610 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
612 #define EXTRACT_IFMT_MVTACHI_A_VARS \
619 #define EXTRACT_IFMT_MVTACHI_A_CODE \
621 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
622 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
623 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
624 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
625 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
627 #define EXTRACT_IFMT_MVTC_VARS \
633 #define EXTRACT_IFMT_MVTC_CODE \
635 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
636 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
637 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
638 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
640 #define EXTRACT_IFMT_NOP_VARS \
646 #define EXTRACT_IFMT_NOP_CODE \
648 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
649 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
650 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
651 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
653 #define EXTRACT_IFMT_RAC_DSI_VARS \
662 #define EXTRACT_IFMT_RAC_DSI_CODE \
664 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
665 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
666 f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
667 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
668 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
669 f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
670 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
672 #define EXTRACT_IFMT_SETH_VARS \
679 #define EXTRACT_IFMT_SETH_CODE \
681 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
682 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
683 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
684 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
685 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
687 #define EXTRACT_IFMT_SLLI_VARS \
693 #define EXTRACT_IFMT_SLLI_CODE \
695 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
696 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
697 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
698 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
700 #define EXTRACT_IFMT_ST_D_VARS \
707 #define EXTRACT_IFMT_ST_D_CODE \
709 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
710 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
711 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
712 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
713 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
715 #define EXTRACT_IFMT_TRAP_VARS \
721 #define EXTRACT_IFMT_TRAP_CODE \
723 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
724 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
725 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
726 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
728 #define EXTRACT_IFMT_SATB_VARS \
735 #define EXTRACT_IFMT_SATB_CODE \
737 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
738 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
739 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
740 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
741 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
743 #define EXTRACT_IFMT_CLRPSW_VARS \
748 #define EXTRACT_IFMT_CLRPSW_CODE \
750 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
751 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
752 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
754 #define EXTRACT_IFMT_BSET_VARS \
762 #define EXTRACT_IFMT_BSET_CODE \
764 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
765 f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
766 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
767 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
768 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
769 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
771 #define EXTRACT_IFMT_BTST_VARS \
778 #define EXTRACT_IFMT_BTST_CODE \
780 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
781 f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
782 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
783 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
784 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
786 /* Queued output values of an instruction. */
790 struct { /* empty sformat for unspecified field list */
793 struct { /* e.g. add $dr,$sr */
796 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
799 struct { /* e.g. and3 $dr,$sr,$uimm16 */
802 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
805 struct { /* e.g. addi $dr,$simm8 */
808 struct { /* e.g. addv $dr,$sr */
812 struct { /* e.g. addv3 $dr,$sr,$simm16 */
816 struct { /* e.g. addx $dr,$sr */
820 struct { /* e.g. bc.s $disp8 */
823 struct { /* e.g. bc.l $disp24 */
826 struct { /* e.g. beq $src1,$src2,$disp16 */
829 struct { /* e.g. beqz $src2,$disp16 */
832 struct { /* e.g. bl.s $disp8 */
836 struct { /* e.g. bl.l $disp24 */
840 struct { /* e.g. bcl.s $disp8 */
844 struct { /* e.g. bcl.l $disp24 */
848 struct { /* e.g. bra.s $disp8 */
851 struct { /* e.g. bra.l $disp24 */
854 struct { /* e.g. cmp $src1,$src2 */
857 struct { /* e.g. cmpi $src2,$simm16 */
860 struct { /* e.g. cmpz $src2 */
863 struct { /* e.g. div $dr,$sr */
866 struct { /* e.g. jc $sr */
869 struct { /* e.g. jl $sr */
873 struct { /* e.g. jmp $sr */
876 struct { /* e.g. ld $dr,@$sr */
879 struct { /* e.g. ld $dr,@($slo16,$sr) */
882 struct { /* e.g. ldb $dr,@$sr */
885 struct { /* e.g. ldb $dr,@($slo16,$sr) */
888 struct { /* e.g. ldh $dr,@$sr */
891 struct { /* e.g. ldh $dr,@($slo16,$sr) */
894 struct { /* e.g. ld $dr,@$sr+ */
898 struct { /* e.g. ld24 $dr,$uimm24 */
901 struct { /* e.g. ldi8 $dr,$simm8 */
904 struct { /* e.g. ldi16 $dr,$hash$slo16 */
907 struct { /* e.g. lock $dr,@$sr */
911 struct { /* e.g. machi $src1,$src2,$acc */
914 struct { /* e.g. mulhi $src1,$src2,$acc */
917 struct { /* e.g. mv $dr,$sr */
920 struct { /* e.g. mvfachi $dr,$accs */
923 struct { /* e.g. mvfc $dr,$scr */
926 struct { /* e.g. mvtachi $src1,$accs */
929 struct { /* e.g. mvtc $sr,$dcr */
932 struct { /* e.g. nop */
935 struct { /* e.g. rac $accd,$accs,$imm1 */
938 struct { /* e.g. rte */
944 struct { /* e.g. seth $dr,$hash$hi16 */
947 struct { /* e.g. sll3 $dr,$sr,$simm16 */
950 struct { /* e.g. slli $dr,$uimm5 */
953 struct { /* e.g. st $src1,@$src2 */
955 USI h_memory_SI_src2_idx;
957 struct { /* e.g. st $src1,@($slo16,$src2) */
958 SI h_memory_SI_add__SI_src2_slo16;
959 USI h_memory_SI_add__SI_src2_slo16_idx;
961 struct { /* e.g. stb $src1,@$src2 */
963 USI h_memory_QI_src2_idx;
965 struct { /* e.g. stb $src1,@($slo16,$src2) */
966 QI h_memory_QI_add__SI_src2_slo16;
967 USI h_memory_QI_add__SI_src2_slo16_idx;
969 struct { /* e.g. sth $src1,@$src2 */
971 USI h_memory_HI_src2_idx;
973 struct { /* e.g. sth $src1,@($slo16,$src2) */
974 HI h_memory_HI_add__SI_src2_slo16;
975 USI h_memory_HI_add__SI_src2_slo16_idx;
977 struct { /* e.g. st $src1,@+$src2 */
978 SI h_memory_SI_new_src2;
979 USI h_memory_SI_new_src2_idx;
982 struct { /* e.g. sth $src1,@$src2+ */
983 HI h_memory_HI_new_src2;
984 USI h_memory_HI_new_src2_idx;
987 struct { /* e.g. stb $src1,@$src2+ */
988 QI h_memory_QI_new_src2;
989 USI h_memory_QI_new_src2_idx;
992 struct { /* e.g. trap $uimm4 */
1000 struct { /* e.g. unlock $src1,@$src2 */
1002 SI h_memory_SI_src2;
1003 USI h_memory_SI_src2_idx;
1005 struct { /* e.g. satb $dr,$sr */
1008 struct { /* e.g. sat $dr,$sr */
1011 struct { /* e.g. sadd */
1014 struct { /* e.g. macwu1 $src1,$src2 */
1017 struct { /* e.g. msblo $src1,$src2 */
1020 struct { /* e.g. mulwu1 $src1,$src2 */
1023 struct { /* e.g. sc */
1026 struct { /* e.g. clrpsw $uimm8 */
1029 struct { /* e.g. setpsw $uimm8 */
1032 struct { /* e.g. bset $uimm3,@($slo16,$sr) */
1033 QI h_memory_QI_add__SI_sr_slo16;
1034 USI h_memory_QI_add__SI_sr_slo16_idx;
1036 struct { /* e.g. btst $uimm3,$sr */
1040 /* For conditionally written operands, bitmask of which ones were. */
1044 /* Collection of various things for the trace handler to use. */
1046 typedef struct trace_record {
1051 #endif /* CPU_M32RXF_H */