1 /* CPU family header for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 2
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 #define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
50 #define SET_H_CR(index, x) \
52 m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
56 #define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
57 #define SET_H_ACCUM(x) \
59 m32rxf_h_accum_set_handler (current_cpu, (x));\
63 #define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
64 #define SET_H_ACCUMS(index, x) \
66 m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
70 #define GET_H_COND() CPU (h_cond)
71 #define SET_H_COND(x) (CPU (h_cond) = (x))
74 #define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
75 #define SET_H_PSW(x) \
77 m32rxf_h_psw_set_handler (current_cpu, (x));\
81 #define GET_H_BPSW() CPU (h_bpsw)
82 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
85 #define GET_H_BBPSW() CPU (h_bbpsw)
86 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
89 #define GET_H_LOCK() CPU (h_lock)
90 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
92 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
95 /* Cover fns for register access. */
96 USI m32rxf_h_pc_get (SIM_CPU *);
97 void m32rxf_h_pc_set (SIM_CPU *, USI);
98 SI m32rxf_h_gr_get (SIM_CPU *, UINT);
99 void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
100 USI m32rxf_h_cr_get (SIM_CPU *, UINT);
101 void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
102 DI m32rxf_h_accum_get (SIM_CPU *);
103 void m32rxf_h_accum_set (SIM_CPU *, DI);
104 DI m32rxf_h_accums_get (SIM_CPU *, UINT);
105 void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
106 BI m32rxf_h_cond_get (SIM_CPU *);
107 void m32rxf_h_cond_set (SIM_CPU *, BI);
108 UQI m32rxf_h_psw_get (SIM_CPU *);
109 void m32rxf_h_psw_set (SIM_CPU *, UQI);
110 UQI m32rxf_h_bpsw_get (SIM_CPU *);
111 void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
112 UQI m32rxf_h_bbpsw_get (SIM_CPU *);
113 void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
114 BI m32rxf_h_lock_get (SIM_CPU *);
115 void m32rxf_h_lock_set (SIM_CPU *, BI);
117 /* These must be hand-written. */
118 extern CPUREG_FETCH_FN m32rxf_fetch_register;
119 extern CPUREG_STORE_FN m32rxf_store_register;
125 /* Instruction argument buffer. */
128 struct { /* no operands */
136 unsigned char out_h_gr_14;
140 unsigned char out_h_gr_14;
145 unsigned char out_dr;
160 unsigned char in_src1;
165 unsigned char out_dr;
170 unsigned char out_dr;
175 unsigned char out_dr;
180 unsigned char out_h_gr_14;
186 unsigned char out_dr;
192 unsigned char out_dr;
197 unsigned char in_src1;
198 unsigned char in_src2;
199 unsigned char out_src2;
205 unsigned char in_src1;
206 unsigned char in_src2;
212 unsigned char in_src1;
213 unsigned char in_src2;
219 unsigned char out_dr;
220 unsigned char out_sr;
226 unsigned char in_src1;
227 unsigned char in_src2;
234 unsigned char out_dr;
241 unsigned char out_dr;
248 unsigned char out_dr;
251 /* Writeback handler. */
253 /* Pointer to argbuf entry for insn whose results need writing back. */
254 const struct argbuf *abuf;
256 /* x-before handler */
258 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
261 /* x-after handler */
265 /* This entry is used to terminate each pbb. */
267 /* Number of insns in pbb. */
269 /* Next pbb to execute. */
271 SCACHE *branch_target;
276 /* The ARGBUF struct. */
278 /* These are the baseclass definitions. */
283 /* ??? Temporary hack for skip insns. */
286 /* cpu specific data follows */
289 union sem_fields fields;
294 ??? SCACHE used to contain more than just argbuf. We could delete the
295 type entirely and always just use ARGBUF, but for future concerns and as
296 a level of abstraction it is left in. */
299 struct argbuf argbuf;
302 /* Macros to simplify extraction, reading and semantic code.
303 These define and assign the local vars that contain the insn's fields. */
305 #define EXTRACT_IFMT_EMPTY_VARS \
307 #define EXTRACT_IFMT_EMPTY_CODE \
310 #define EXTRACT_IFMT_ADD_VARS \
316 #define EXTRACT_IFMT_ADD_CODE \
318 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
319 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
320 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
321 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
323 #define EXTRACT_IFMT_ADD3_VARS \
330 #define EXTRACT_IFMT_ADD3_CODE \
332 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
333 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
334 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
335 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
336 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
338 #define EXTRACT_IFMT_AND3_VARS \
345 #define EXTRACT_IFMT_AND3_CODE \
347 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
348 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
349 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
350 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
351 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
353 #define EXTRACT_IFMT_OR3_VARS \
360 #define EXTRACT_IFMT_OR3_CODE \
362 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
363 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
364 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
365 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
366 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
368 #define EXTRACT_IFMT_ADDI_VARS \
373 #define EXTRACT_IFMT_ADDI_CODE \
375 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
376 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
377 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
379 #define EXTRACT_IFMT_ADDV3_VARS \
386 #define EXTRACT_IFMT_ADDV3_CODE \
388 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
389 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
390 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
391 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
392 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
394 #define EXTRACT_IFMT_BC8_VARS \
399 #define EXTRACT_IFMT_BC8_CODE \
401 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
402 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
403 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
405 #define EXTRACT_IFMT_BC24_VARS \
410 #define EXTRACT_IFMT_BC24_CODE \
412 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
413 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
414 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
416 #define EXTRACT_IFMT_BEQ_VARS \
423 #define EXTRACT_IFMT_BEQ_CODE \
425 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
426 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
427 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
428 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
429 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
431 #define EXTRACT_IFMT_BEQZ_VARS \
438 #define EXTRACT_IFMT_BEQZ_CODE \
440 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
441 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
442 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
443 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
444 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
446 #define EXTRACT_IFMT_CMP_VARS \
452 #define EXTRACT_IFMT_CMP_CODE \
454 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
455 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
456 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
457 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
459 #define EXTRACT_IFMT_CMPI_VARS \
466 #define EXTRACT_IFMT_CMPI_CODE \
468 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
469 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
470 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
471 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
472 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
474 #define EXTRACT_IFMT_CMPZ_VARS \
480 #define EXTRACT_IFMT_CMPZ_CODE \
482 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
483 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
484 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
485 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
487 #define EXTRACT_IFMT_DIV_VARS \
494 #define EXTRACT_IFMT_DIV_CODE \
496 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
497 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
498 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
499 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
500 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
502 #define EXTRACT_IFMT_JC_VARS \
508 #define EXTRACT_IFMT_JC_CODE \
510 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
511 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
512 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
513 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
515 #define EXTRACT_IFMT_LD24_VARS \
520 #define EXTRACT_IFMT_LD24_CODE \
522 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
523 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
524 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
526 #define EXTRACT_IFMT_LDI16_VARS \
533 #define EXTRACT_IFMT_LDI16_CODE \
535 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
536 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
537 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
538 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
539 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
541 #define EXTRACT_IFMT_MACHI_A_VARS \
548 #define EXTRACT_IFMT_MACHI_A_CODE \
550 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
551 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
552 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
553 f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
554 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
556 #define EXTRACT_IFMT_MVFACHI_A_VARS \
563 #define EXTRACT_IFMT_MVFACHI_A_CODE \
565 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
566 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
567 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
568 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
569 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
571 #define EXTRACT_IFMT_MVFC_VARS \
577 #define EXTRACT_IFMT_MVFC_CODE \
579 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
580 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
581 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
582 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
584 #define EXTRACT_IFMT_MVTACHI_A_VARS \
591 #define EXTRACT_IFMT_MVTACHI_A_CODE \
593 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
594 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
595 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
596 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
597 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
599 #define EXTRACT_IFMT_MVTC_VARS \
605 #define EXTRACT_IFMT_MVTC_CODE \
607 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
608 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
609 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
610 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
612 #define EXTRACT_IFMT_NOP_VARS \
618 #define EXTRACT_IFMT_NOP_CODE \
620 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
621 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
622 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
623 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
625 #define EXTRACT_IFMT_RAC_DSI_VARS \
634 #define EXTRACT_IFMT_RAC_DSI_CODE \
636 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
637 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
638 f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
639 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
640 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
641 f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
642 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
644 #define EXTRACT_IFMT_SETH_VARS \
651 #define EXTRACT_IFMT_SETH_CODE \
653 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
654 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
655 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
656 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
657 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
659 #define EXTRACT_IFMT_SLLI_VARS \
665 #define EXTRACT_IFMT_SLLI_CODE \
667 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
668 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
669 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
670 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
672 #define EXTRACT_IFMT_ST_D_VARS \
679 #define EXTRACT_IFMT_ST_D_CODE \
681 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
682 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
683 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
684 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
685 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
687 #define EXTRACT_IFMT_TRAP_VARS \
693 #define EXTRACT_IFMT_TRAP_CODE \
695 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
696 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
697 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
698 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
700 #define EXTRACT_IFMT_SATB_VARS \
707 #define EXTRACT_IFMT_SATB_CODE \
709 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
710 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
711 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
712 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
713 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
715 /* Queued output values of an instruction. */
719 struct { /* empty sformat for unspecified field list */
722 struct { /* e.g. add $dr,$sr */
725 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
728 struct { /* e.g. and3 $dr,$sr,$uimm16 */
731 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
734 struct { /* e.g. addi $dr,$simm8 */
737 struct { /* e.g. addv $dr,$sr */
741 struct { /* e.g. addv3 $dr,$sr,$simm16 */
745 struct { /* e.g. addx $dr,$sr */
749 struct { /* e.g. bc.s $disp8 */
752 struct { /* e.g. bc.l $disp24 */
755 struct { /* e.g. beq $src1,$src2,$disp16 */
758 struct { /* e.g. beqz $src2,$disp16 */
761 struct { /* e.g. bl.s $disp8 */
765 struct { /* e.g. bl.l $disp24 */
769 struct { /* e.g. bcl.s $disp8 */
773 struct { /* e.g. bcl.l $disp24 */
777 struct { /* e.g. bra.s $disp8 */
780 struct { /* e.g. bra.l $disp24 */
783 struct { /* e.g. cmp $src1,$src2 */
786 struct { /* e.g. cmpi $src2,$simm16 */
789 struct { /* e.g. cmpz $src2 */
792 struct { /* e.g. div $dr,$sr */
795 struct { /* e.g. jc $sr */
798 struct { /* e.g. jl $sr */
802 struct { /* e.g. jmp $sr */
805 struct { /* e.g. ld $dr,@$sr */
808 struct { /* e.g. ld $dr,@($slo16,$sr) */
811 struct { /* e.g. ld $dr,@$sr+ */
815 struct { /* e.g. ld24 $dr,$uimm24 */
818 struct { /* e.g. ldi8 $dr,$simm8 */
821 struct { /* e.g. ldi16 $dr,$hash$slo16 */
824 struct { /* e.g. lock $dr,@$sr */
828 struct { /* e.g. machi $src1,$src2,$acc */
831 struct { /* e.g. mulhi $src1,$src2,$acc */
834 struct { /* e.g. mv $dr,$sr */
837 struct { /* e.g. mvfachi $dr,$accs */
840 struct { /* e.g. mvfc $dr,$scr */
843 struct { /* e.g. mvtachi $src1,$accs */
846 struct { /* e.g. mvtc $sr,$dcr */
849 struct { /* e.g. nop */
852 struct { /* e.g. rac $accd,$accs,$imm1 */
855 struct { /* e.g. rte */
861 struct { /* e.g. seth $dr,$hash$hi16 */
864 struct { /* e.g. sll3 $dr,$sr,$simm16 */
867 struct { /* e.g. slli $dr,$uimm5 */
870 struct { /* e.g. st $src1,@$src2 */
872 USI h_memory_src2_idx;
874 struct { /* e.g. st $src1,@($slo16,$src2) */
875 SI h_memory_add__DFLT_src2_slo16;
876 USI h_memory_add__DFLT_src2_slo16_idx;
878 struct { /* e.g. stb $src1,@$src2 */
880 USI h_memory_src2_idx;
882 struct { /* e.g. stb $src1,@($slo16,$src2) */
883 QI h_memory_add__DFLT_src2_slo16;
884 USI h_memory_add__DFLT_src2_slo16_idx;
886 struct { /* e.g. sth $src1,@$src2 */
888 USI h_memory_src2_idx;
890 struct { /* e.g. sth $src1,@($slo16,$src2) */
891 HI h_memory_add__DFLT_src2_slo16;
892 USI h_memory_add__DFLT_src2_slo16_idx;
894 struct { /* e.g. st $src1,@+$src2 */
895 SI h_memory_new_src2;
896 USI h_memory_new_src2_idx;
899 struct { /* e.g. trap $uimm4 */
907 struct { /* e.g. unlock $src1,@$src2 */
910 USI h_memory_src2_idx;
912 struct { /* e.g. satb $dr,$sr */
915 struct { /* e.g. sat $dr,$sr */
918 struct { /* e.g. sadd */
921 struct { /* e.g. macwu1 $src1,$src2 */
924 struct { /* e.g. msblo $src1,$src2 */
927 struct { /* e.g. mulwu1 $src1,$src2 */
930 struct { /* e.g. sc */
934 /* For conditionally written operands, bitmask of which ones were. */
938 /* Collection of various things for the trace handler to use. */
940 typedef struct trace_record {
945 #endif /* CPU_M32RXF_H */