1 /* CPU family header for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 2
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 #define GET_H_CR(a1) CPU (h_cr)[a1]
50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
53 #define GET_H_ACCUM() CPU (h_accum)
54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
55 /* start-sanitize-m32rx */
58 /* end-sanitize-m32rx */
59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
63 #define GET_H_COND() CPU (h_cond)
64 #define SET_H_COND(x) (CPU (h_cond) = (x))
67 #define GET_H_PSW() CPU (h_psw)
68 #define SET_H_PSW(x) (CPU (h_psw) = (x))
71 #define GET_H_BPSW() CPU (h_bpsw)
72 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
75 #define GET_H_BBPSW() CPU (h_bbpsw)
76 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
79 #define GET_H_LOCK() CPU (h_lock)
80 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
82 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
85 /* Cover fns for register access. */
86 USI m32rxf_h_pc_get (SIM_CPU *);
87 void m32rxf_h_pc_set (SIM_CPU *, USI);
88 SI m32rxf_h_gr_get (SIM_CPU *, UINT);
89 void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
90 USI m32rxf_h_cr_get (SIM_CPU *, UINT);
91 void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
92 DI m32rxf_h_accum_get (SIM_CPU *);
93 void m32rxf_h_accum_set (SIM_CPU *, DI);
94 DI m32rxf_h_accums_get (SIM_CPU *, UINT);
95 void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
96 BI m32rxf_h_cond_get (SIM_CPU *);
97 void m32rxf_h_cond_set (SIM_CPU *, BI);
98 UQI m32rxf_h_psw_get (SIM_CPU *);
99 void m32rxf_h_psw_set (SIM_CPU *, UQI);
100 UQI m32rxf_h_bpsw_get (SIM_CPU *);
101 void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
102 UQI m32rxf_h_bbpsw_get (SIM_CPU *);
103 void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
104 BI m32rxf_h_lock_get (SIM_CPU *);
105 void m32rxf_h_lock_set (SIM_CPU *, BI);
107 /* These must be hand-written. */
108 extern CPUREG_FETCH_FN m32rxf_fetch_register;
109 extern CPUREG_STORE_FN m32rxf_store_register;
115 /* The ARGBUF struct. */
117 /* These are the baseclass definitions. */
122 /* cpu specific data follows */
126 struct { /* e.g. add $dr,$sr */
131 unsigned char out_dr;
133 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
138 unsigned char out_dr;
140 struct { /* e.g. and3 $dr,$sr,$uimm16 */
145 unsigned char out_dr;
147 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
152 unsigned char out_dr;
154 struct { /* e.g. addi $dr,$simm8 */
158 unsigned char out_dr;
160 struct { /* e.g. addv $dr,$sr */
165 unsigned char out_dr;
167 struct { /* e.g. addv3 $dr,$sr,$simm16 */
172 unsigned char out_dr;
174 struct { /* e.g. addx $dr,$sr */
179 unsigned char out_dr;
181 struct { /* e.g. cmp $src1,$src2 */
184 unsigned char in_src1;
185 unsigned char in_src2;
187 struct { /* e.g. cmpi $src2,$simm16 */
190 unsigned char in_src2;
192 struct { /* e.g. cmpz $src2 */
194 unsigned char in_src2;
196 struct { /* e.g. div $dr,$sr */
201 unsigned char out_dr;
203 struct { /* e.g. ld $dr,@$sr */
207 unsigned char out_dr;
209 struct { /* e.g. ld $dr,@($slo16,$sr) */
214 unsigned char out_dr;
216 struct { /* e.g. ldb $dr,@$sr */
220 unsigned char out_dr;
222 struct { /* e.g. ldb $dr,@($slo16,$sr) */
227 unsigned char out_dr;
229 struct { /* e.g. ldh $dr,@$sr */
233 unsigned char out_dr;
235 struct { /* e.g. ldh $dr,@($slo16,$sr) */
240 unsigned char out_dr;
242 struct { /* e.g. ld $dr,@$sr+ */
246 unsigned char out_dr;
247 unsigned char out_sr;
249 struct { /* e.g. ld24 $dr,$uimm24 */
252 unsigned char out_dr;
254 struct { /* e.g. ldi8 $dr,$simm8 */
257 unsigned char out_dr;
259 struct { /* e.g. ldi16 $dr,$hash$slo16 */
262 unsigned char out_dr;
264 struct { /* e.g. lock $dr,@$sr */
268 unsigned char out_dr;
270 struct { /* e.g. machi $src1,$src2,$acc */
274 unsigned char in_src1;
275 unsigned char in_src2;
277 struct { /* e.g. mulhi $src1,$src2,$acc */
281 unsigned char in_src1;
282 unsigned char in_src2;
284 struct { /* e.g. mv $dr,$sr */
288 unsigned char out_dr;
290 struct { /* e.g. mvfachi $dr,$accs */
293 unsigned char out_dr;
295 struct { /* e.g. mvfc $dr,$scr */
298 unsigned char out_dr;
300 struct { /* e.g. mvtachi $src1,$accs */
303 unsigned char in_src1;
305 struct { /* e.g. mvtc $sr,$dcr */
310 struct { /* e.g. nop */
313 struct { /* e.g. rac $accd,$accs,$imm1 */
318 struct { /* e.g. seth $dr,$hash$hi16 */
321 unsigned char out_dr;
323 struct { /* e.g. sll3 $dr,$sr,$simm16 */
328 unsigned char out_dr;
330 struct { /* e.g. slli $dr,$uimm5 */
334 unsigned char out_dr;
336 struct { /* e.g. st $src1,@$src2 */
339 unsigned char in_src2;
340 unsigned char in_src1;
342 struct { /* e.g. st $src1,@($slo16,$src2) */
346 unsigned char in_src2;
347 unsigned char in_src1;
349 struct { /* e.g. stb $src1,@$src2 */
352 unsigned char in_src2;
353 unsigned char in_src1;
355 struct { /* e.g. stb $src1,@($slo16,$src2) */
359 unsigned char in_src2;
360 unsigned char in_src1;
362 struct { /* e.g. sth $src1,@$src2 */
365 unsigned char in_src2;
366 unsigned char in_src1;
368 struct { /* e.g. sth $src1,@($slo16,$src2) */
372 unsigned char in_src2;
373 unsigned char in_src1;
375 struct { /* e.g. st $src1,@+$src2 */
378 unsigned char in_src2;
379 unsigned char in_src1;
380 unsigned char out_src2;
382 struct { /* e.g. unlock $src1,@$src2 */
385 unsigned char in_src2;
386 unsigned char in_src1;
388 struct { /* e.g. satb $dr,$sr */
392 unsigned char out_dr;
394 struct { /* e.g. sat $dr,$sr */
398 unsigned char out_dr;
400 struct { /* e.g. sadd */
403 struct { /* e.g. macwu1 $src1,$src2 */
406 unsigned char in_src1;
407 unsigned char in_src2;
409 struct { /* e.g. msblo $src1,$src2 */
412 unsigned char in_src1;
413 unsigned char in_src2;
415 struct { /* e.g. mulwu1 $src1,$src2 */
418 unsigned char in_src1;
419 unsigned char in_src2;
421 /* cti insns, kept separately so addr_cache is in fixed place */
424 struct { /* e.g. bc.s $disp8 */
427 struct { /* e.g. bc.l $disp24 */
430 struct { /* e.g. beq $src1,$src2,$disp16 */
434 unsigned char in_src1;
435 unsigned char in_src2;
437 struct { /* e.g. beqz $src2,$disp16 */
440 unsigned char in_src2;
442 struct { /* e.g. bl.s $disp8 */
444 unsigned char out_h_gr_14;
446 struct { /* e.g. bl.l $disp24 */
448 unsigned char out_h_gr_14;
450 struct { /* e.g. bcl.s $disp8 */
452 unsigned char out_h_gr_14;
454 struct { /* e.g. bcl.l $disp24 */
456 unsigned char out_h_gr_14;
458 struct { /* e.g. bra.s $disp8 */
461 struct { /* e.g. bra.l $disp24 */
464 struct { /* e.g. jc $sr */
468 struct { /* e.g. jl $sr */
471 unsigned char out_h_gr_14;
473 struct { /* e.g. jmp $sr */
477 struct { /* e.g. rte */
480 struct { /* e.g. trap $uimm4 */
483 struct { /* e.g. sc */
487 #if WITH_SCACHE_PBB_M32RXF
491 #if WITH_SCACHE_PBB_M32RXF
492 /* Writeback handler. */
494 /* Pointer to argbuf entry for insn whose results need writing back. */
495 const struct argbuf *abuf;
497 /* x-before handler */
499 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
502 /* x-after handler */
506 /* This entry is used to terminate each pbb. */
508 /* Number of insns in pbb. */
510 /* Next pbb to execute. */
519 ??? SCACHE used to contain more than just argbuf. We could delete the
520 type entirely and always just use ARGBUF, but for future concerns and as
521 a level of abstraction it is left in. */
524 struct argbuf argbuf;
527 /* Macros to simplify extraction, reading and semantic code.
528 These define and assign the local vars that contain the insn's fields. */
530 #define EXTRACT_FMT_ADD_VARS \
531 /* Instruction fields. */ \
537 #define EXTRACT_FMT_ADD_CODE \
539 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
540 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
541 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
542 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
544 #define EXTRACT_FMT_ADD3_VARS \
545 /* Instruction fields. */ \
552 #define EXTRACT_FMT_ADD3_CODE \
554 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
555 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
556 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
557 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
558 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
560 #define EXTRACT_FMT_AND3_VARS \
561 /* Instruction fields. */ \
568 #define EXTRACT_FMT_AND3_CODE \
570 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
571 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
572 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
573 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
574 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
576 #define EXTRACT_FMT_OR3_VARS \
577 /* Instruction fields. */ \
584 #define EXTRACT_FMT_OR3_CODE \
586 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
587 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
588 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
589 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
590 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
592 #define EXTRACT_FMT_ADDI_VARS \
593 /* Instruction fields. */ \
598 #define EXTRACT_FMT_ADDI_CODE \
600 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
601 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
602 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
604 #define EXTRACT_FMT_ADDV_VARS \
605 /* Instruction fields. */ \
611 #define EXTRACT_FMT_ADDV_CODE \
613 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
614 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
615 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
616 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
618 #define EXTRACT_FMT_ADDV3_VARS \
619 /* Instruction fields. */ \
626 #define EXTRACT_FMT_ADDV3_CODE \
628 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
629 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
630 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
631 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
632 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
634 #define EXTRACT_FMT_ADDX_VARS \
635 /* Instruction fields. */ \
641 #define EXTRACT_FMT_ADDX_CODE \
643 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
644 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
645 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
646 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
648 #define EXTRACT_FMT_BC8_VARS \
649 /* Instruction fields. */ \
654 #define EXTRACT_FMT_BC8_CODE \
656 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
657 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
658 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
660 #define EXTRACT_FMT_BC24_VARS \
661 /* Instruction fields. */ \
666 #define EXTRACT_FMT_BC24_CODE \
668 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
669 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
670 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
672 #define EXTRACT_FMT_BEQ_VARS \
673 /* Instruction fields. */ \
680 #define EXTRACT_FMT_BEQ_CODE \
682 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
683 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
684 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
685 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
686 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
688 #define EXTRACT_FMT_BEQZ_VARS \
689 /* Instruction fields. */ \
696 #define EXTRACT_FMT_BEQZ_CODE \
698 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
699 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
700 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
701 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
702 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
704 #define EXTRACT_FMT_BL8_VARS \
705 /* Instruction fields. */ \
710 #define EXTRACT_FMT_BL8_CODE \
712 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
713 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
714 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
716 #define EXTRACT_FMT_BL24_VARS \
717 /* Instruction fields. */ \
722 #define EXTRACT_FMT_BL24_CODE \
724 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
725 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
726 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
728 #define EXTRACT_FMT_BCL8_VARS \
729 /* Instruction fields. */ \
734 #define EXTRACT_FMT_BCL8_CODE \
736 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
737 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
738 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
740 #define EXTRACT_FMT_BCL24_VARS \
741 /* Instruction fields. */ \
746 #define EXTRACT_FMT_BCL24_CODE \
748 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
749 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
750 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
752 #define EXTRACT_FMT_BRA8_VARS \
753 /* Instruction fields. */ \
758 #define EXTRACT_FMT_BRA8_CODE \
760 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
761 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
762 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
764 #define EXTRACT_FMT_BRA24_VARS \
765 /* Instruction fields. */ \
770 #define EXTRACT_FMT_BRA24_CODE \
772 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
773 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
774 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
776 #define EXTRACT_FMT_CMP_VARS \
777 /* Instruction fields. */ \
783 #define EXTRACT_FMT_CMP_CODE \
785 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
786 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
787 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
788 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
790 #define EXTRACT_FMT_CMPI_VARS \
791 /* Instruction fields. */ \
798 #define EXTRACT_FMT_CMPI_CODE \
800 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
801 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
802 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
803 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
804 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
806 #define EXTRACT_FMT_CMPZ_VARS \
807 /* Instruction fields. */ \
813 #define EXTRACT_FMT_CMPZ_CODE \
815 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
816 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
817 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
818 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
820 #define EXTRACT_FMT_DIV_VARS \
821 /* Instruction fields. */ \
828 #define EXTRACT_FMT_DIV_CODE \
830 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
831 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
832 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
833 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
834 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
836 #define EXTRACT_FMT_JC_VARS \
837 /* Instruction fields. */ \
843 #define EXTRACT_FMT_JC_CODE \
845 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
846 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
847 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
848 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
850 #define EXTRACT_FMT_JL_VARS \
851 /* Instruction fields. */ \
857 #define EXTRACT_FMT_JL_CODE \
859 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
860 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
861 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
862 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
864 #define EXTRACT_FMT_JMP_VARS \
865 /* Instruction fields. */ \
871 #define EXTRACT_FMT_JMP_CODE \
873 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
874 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
875 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
876 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
878 #define EXTRACT_FMT_LD_VARS \
879 /* Instruction fields. */ \
885 #define EXTRACT_FMT_LD_CODE \
887 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
888 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
889 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
890 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
892 #define EXTRACT_FMT_LD_D_VARS \
893 /* Instruction fields. */ \
900 #define EXTRACT_FMT_LD_D_CODE \
902 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
903 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
904 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
905 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
906 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
908 #define EXTRACT_FMT_LDB_VARS \
909 /* Instruction fields. */ \
915 #define EXTRACT_FMT_LDB_CODE \
917 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
918 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
919 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
920 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
922 #define EXTRACT_FMT_LDB_D_VARS \
923 /* Instruction fields. */ \
930 #define EXTRACT_FMT_LDB_D_CODE \
932 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
933 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
934 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
935 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
936 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
938 #define EXTRACT_FMT_LDH_VARS \
939 /* Instruction fields. */ \
945 #define EXTRACT_FMT_LDH_CODE \
947 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
948 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
949 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
950 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
952 #define EXTRACT_FMT_LDH_D_VARS \
953 /* Instruction fields. */ \
960 #define EXTRACT_FMT_LDH_D_CODE \
962 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
963 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
964 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
965 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
966 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
968 #define EXTRACT_FMT_LD_PLUS_VARS \
969 /* Instruction fields. */ \
975 #define EXTRACT_FMT_LD_PLUS_CODE \
977 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
978 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
979 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
980 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
982 #define EXTRACT_FMT_LD24_VARS \
983 /* Instruction fields. */ \
988 #define EXTRACT_FMT_LD24_CODE \
990 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
991 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
992 f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
994 #define EXTRACT_FMT_LDI8_VARS \
995 /* Instruction fields. */ \
1000 #define EXTRACT_FMT_LDI8_CODE \
1002 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1003 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1004 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
1006 #define EXTRACT_FMT_LDI16_VARS \
1007 /* Instruction fields. */ \
1013 unsigned int length;
1014 #define EXTRACT_FMT_LDI16_CODE \
1016 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1017 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1018 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1019 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1020 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1022 #define EXTRACT_FMT_LOCK_VARS \
1023 /* Instruction fields. */ \
1028 unsigned int length;
1029 #define EXTRACT_FMT_LOCK_CODE \
1031 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1032 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1033 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1034 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1036 #define EXTRACT_FMT_MACHI_A_VARS \
1037 /* Instruction fields. */ \
1043 unsigned int length;
1044 #define EXTRACT_FMT_MACHI_A_CODE \
1046 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1047 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1048 f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1049 f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1050 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1052 #define EXTRACT_FMT_MULHI_A_VARS \
1053 /* Instruction fields. */ \
1059 unsigned int length;
1060 #define EXTRACT_FMT_MULHI_A_CODE \
1062 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1063 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1064 f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1065 f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1066 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1068 #define EXTRACT_FMT_MV_VARS \
1069 /* Instruction fields. */ \
1074 unsigned int length;
1075 #define EXTRACT_FMT_MV_CODE \
1077 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1078 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1079 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1080 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1082 #define EXTRACT_FMT_MVFACHI_A_VARS \
1083 /* Instruction fields. */ \
1089 unsigned int length;
1090 #define EXTRACT_FMT_MVFACHI_A_CODE \
1092 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1093 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1094 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1095 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1096 f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1098 #define EXTRACT_FMT_MVFC_VARS \
1099 /* Instruction fields. */ \
1104 unsigned int length;
1105 #define EXTRACT_FMT_MVFC_CODE \
1107 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1108 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1109 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1110 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1112 #define EXTRACT_FMT_MVTACHI_A_VARS \
1113 /* Instruction fields. */ \
1119 unsigned int length;
1120 #define EXTRACT_FMT_MVTACHI_A_CODE \
1122 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1123 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1124 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1125 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1126 f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1128 #define EXTRACT_FMT_MVTC_VARS \
1129 /* Instruction fields. */ \
1134 unsigned int length;
1135 #define EXTRACT_FMT_MVTC_CODE \
1137 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1138 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1139 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1140 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1142 #define EXTRACT_FMT_NOP_VARS \
1143 /* Instruction fields. */ \
1148 unsigned int length;
1149 #define EXTRACT_FMT_NOP_CODE \
1151 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1152 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1153 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1154 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1156 #define EXTRACT_FMT_RAC_DSI_VARS \
1157 /* Instruction fields. */ \
1165 unsigned int length;
1166 #define EXTRACT_FMT_RAC_DSI_CODE \
1168 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1169 f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
1170 f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
1171 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1172 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1173 f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
1174 f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
1176 #define EXTRACT_FMT_RTE_VARS \
1177 /* Instruction fields. */ \
1182 unsigned int length;
1183 #define EXTRACT_FMT_RTE_CODE \
1185 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1186 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1187 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1188 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1190 #define EXTRACT_FMT_SETH_VARS \
1191 /* Instruction fields. */ \
1197 unsigned int length;
1198 #define EXTRACT_FMT_SETH_CODE \
1200 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1201 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1202 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1203 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1204 f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1206 #define EXTRACT_FMT_SLL3_VARS \
1207 /* Instruction fields. */ \
1213 unsigned int length;
1214 #define EXTRACT_FMT_SLL3_CODE \
1216 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1217 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1218 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1219 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1220 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1222 #define EXTRACT_FMT_SLLI_VARS \
1223 /* Instruction fields. */ \
1228 unsigned int length;
1229 #define EXTRACT_FMT_SLLI_CODE \
1231 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1232 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1233 f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1234 f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1236 #define EXTRACT_FMT_ST_VARS \
1237 /* Instruction fields. */ \
1242 unsigned int length;
1243 #define EXTRACT_FMT_ST_CODE \
1245 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1246 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1247 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1248 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1250 #define EXTRACT_FMT_ST_D_VARS \
1251 /* Instruction fields. */ \
1257 unsigned int length;
1258 #define EXTRACT_FMT_ST_D_CODE \
1260 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1261 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1262 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1263 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1264 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1266 #define EXTRACT_FMT_STB_VARS \
1267 /* Instruction fields. */ \
1272 unsigned int length;
1273 #define EXTRACT_FMT_STB_CODE \
1275 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1276 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1277 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1278 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1280 #define EXTRACT_FMT_STB_D_VARS \
1281 /* Instruction fields. */ \
1287 unsigned int length;
1288 #define EXTRACT_FMT_STB_D_CODE \
1290 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1291 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1292 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1293 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1294 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1296 #define EXTRACT_FMT_STH_VARS \
1297 /* Instruction fields. */ \
1302 unsigned int length;
1303 #define EXTRACT_FMT_STH_CODE \
1305 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1306 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1307 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1308 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1310 #define EXTRACT_FMT_STH_D_VARS \
1311 /* Instruction fields. */ \
1317 unsigned int length;
1318 #define EXTRACT_FMT_STH_D_CODE \
1320 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1321 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1322 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1323 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1324 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1326 #define EXTRACT_FMT_ST_PLUS_VARS \
1327 /* Instruction fields. */ \
1332 unsigned int length;
1333 #define EXTRACT_FMT_ST_PLUS_CODE \
1335 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1336 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1337 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1338 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1340 #define EXTRACT_FMT_TRAP_VARS \
1341 /* Instruction fields. */ \
1346 unsigned int length;
1347 #define EXTRACT_FMT_TRAP_CODE \
1349 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1350 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1351 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1352 f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1354 #define EXTRACT_FMT_UNLOCK_VARS \
1355 /* Instruction fields. */ \
1360 unsigned int length;
1361 #define EXTRACT_FMT_UNLOCK_CODE \
1363 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1364 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1365 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1366 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1368 #define EXTRACT_FMT_SATB_VARS \
1369 /* Instruction fields. */ \
1375 unsigned int length;
1376 #define EXTRACT_FMT_SATB_CODE \
1378 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1379 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1380 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1381 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1382 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1384 #define EXTRACT_FMT_SAT_VARS \
1385 /* Instruction fields. */ \
1391 unsigned int length;
1392 #define EXTRACT_FMT_SAT_CODE \
1394 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1395 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1396 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1397 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1398 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1400 #define EXTRACT_FMT_SADD_VARS \
1401 /* Instruction fields. */ \
1406 unsigned int length;
1407 #define EXTRACT_FMT_SADD_CODE \
1409 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1410 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1411 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1412 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1414 #define EXTRACT_FMT_MACWU1_VARS \
1415 /* Instruction fields. */ \
1420 unsigned int length;
1421 #define EXTRACT_FMT_MACWU1_CODE \
1423 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1424 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1425 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1426 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1428 #define EXTRACT_FMT_MSBLO_VARS \
1429 /* Instruction fields. */ \
1434 unsigned int length;
1435 #define EXTRACT_FMT_MSBLO_CODE \
1437 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1438 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1439 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1440 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1442 #define EXTRACT_FMT_MULWU1_VARS \
1443 /* Instruction fields. */ \
1448 unsigned int length;
1449 #define EXTRACT_FMT_MULWU1_CODE \
1451 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1452 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1453 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1454 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1456 #define EXTRACT_FMT_SC_VARS \
1457 /* Instruction fields. */ \
1462 unsigned int length;
1463 #define EXTRACT_FMT_SC_CODE \
1465 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1466 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1467 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1468 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1470 /* Queued output values of an instruction. */
1474 struct { /* e.g. add $dr,$sr */
1477 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
1480 struct { /* e.g. and3 $dr,$sr,$uimm16 */
1483 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
1486 struct { /* e.g. addi $dr,$simm8 */
1489 struct { /* e.g. addv $dr,$sr */
1493 struct { /* e.g. addv3 $dr,$sr,$simm16 */
1497 struct { /* e.g. addx $dr,$sr */
1501 struct { /* e.g. bc.s $disp8 */
1504 struct { /* e.g. bc.l $disp24 */
1507 struct { /* e.g. beq $src1,$src2,$disp16 */
1510 struct { /* e.g. beqz $src2,$disp16 */
1513 struct { /* e.g. bl.s $disp8 */
1517 struct { /* e.g. bl.l $disp24 */
1521 struct { /* e.g. bcl.s $disp8 */
1525 struct { /* e.g. bcl.l $disp24 */
1529 struct { /* e.g. bra.s $disp8 */
1532 struct { /* e.g. bra.l $disp24 */
1535 struct { /* e.g. cmp $src1,$src2 */
1538 struct { /* e.g. cmpi $src2,$simm16 */
1541 struct { /* e.g. cmpz $src2 */
1544 struct { /* e.g. div $dr,$sr */
1547 struct { /* e.g. jc $sr */
1550 struct { /* e.g. jl $sr */
1554 struct { /* e.g. jmp $sr */
1557 struct { /* e.g. ld $dr,@$sr */
1560 struct { /* e.g. ld $dr,@($slo16,$sr) */
1563 struct { /* e.g. ldb $dr,@$sr */
1566 struct { /* e.g. ldb $dr,@($slo16,$sr) */
1569 struct { /* e.g. ldh $dr,@$sr */
1572 struct { /* e.g. ldh $dr,@($slo16,$sr) */
1575 struct { /* e.g. ld $dr,@$sr+ */
1579 struct { /* e.g. ld24 $dr,$uimm24 */
1582 struct { /* e.g. ldi8 $dr,$simm8 */
1585 struct { /* e.g. ldi16 $dr,$hash$slo16 */
1588 struct { /* e.g. lock $dr,@$sr */
1592 struct { /* e.g. machi $src1,$src2,$acc */
1595 struct { /* e.g. mulhi $src1,$src2,$acc */
1598 struct { /* e.g. mv $dr,$sr */
1601 struct { /* e.g. mvfachi $dr,$accs */
1604 struct { /* e.g. mvfc $dr,$scr */
1607 struct { /* e.g. mvtachi $src1,$accs */
1610 struct { /* e.g. mvtc $sr,$dcr */
1613 struct { /* e.g. nop */
1616 struct { /* e.g. rac $accd,$accs,$imm1 */
1619 struct { /* e.g. rte */
1625 struct { /* e.g. seth $dr,$hash$hi16 */
1628 struct { /* e.g. sll3 $dr,$sr,$simm16 */
1631 struct { /* e.g. slli $dr,$uimm5 */
1634 struct { /* e.g. st $src1,@$src2 */
1636 USI h_memory_src2_idx;
1638 struct { /* e.g. st $src1,@($slo16,$src2) */
1639 SI h_memory_add__VM_src2_slo16;
1640 USI h_memory_add__VM_src2_slo16_idx;
1642 struct { /* e.g. stb $src1,@$src2 */
1644 USI h_memory_src2_idx;
1646 struct { /* e.g. stb $src1,@($slo16,$src2) */
1647 QI h_memory_add__VM_src2_slo16;
1648 USI h_memory_add__VM_src2_slo16_idx;
1650 struct { /* e.g. sth $src1,@$src2 */
1652 USI h_memory_src2_idx;
1654 struct { /* e.g. sth $src1,@($slo16,$src2) */
1655 HI h_memory_add__VM_src2_slo16;
1656 USI h_memory_add__VM_src2_slo16_idx;
1658 struct { /* e.g. st $src1,@+$src2 */
1659 SI h_memory_new_src2;
1660 USI h_memory_new_src2_idx;
1663 struct { /* e.g. trap $uimm4 */
1671 struct { /* e.g. unlock $src1,@$src2 */
1673 USI h_memory_src2_idx;
1676 struct { /* e.g. satb $dr,$sr */
1679 struct { /* e.g. sat $dr,$sr */
1682 struct { /* e.g. sadd */
1685 struct { /* e.g. macwu1 $src1,$src2 */
1688 struct { /* e.g. msblo $src1,$src2 */
1691 struct { /* e.g. mulwu1 $src1,$src2 */
1694 struct { /* e.g. sc */
1698 /* For conditionally written operands, bitmask of which ones were. */
1702 /* Collection of various things for the trace handler to use. */
1704 typedef struct trace_record {
1709 #endif /* CPU_M32RXF_H */