1 /* CPU family header for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 2
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
51 /* start-sanitize-m32rx */
54 /* end-sanitize-m32rx */
57 #define GET_H_COND() CPU (h_cond)
58 #define SET_H_COND(x) (CPU (h_cond) = (x))
63 #define GET_H_BPSW() CPU (h_bpsw)
64 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
67 #define GET_H_BBPSW() CPU (h_bbpsw)
68 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
71 #define GET_H_LOCK() CPU (h_lock)
72 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
74 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
77 /* Cover fns for register access. */
78 USI m32rxf_h_pc_get (SIM_CPU *);
79 void m32rxf_h_pc_set (SIM_CPU *, USI);
80 SI m32rxf_h_gr_get (SIM_CPU *, UINT);
81 void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
82 USI m32rxf_h_cr_get (SIM_CPU *, UINT);
83 void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
84 DI m32rxf_h_accum_get (SIM_CPU *);
85 void m32rxf_h_accum_set (SIM_CPU *, DI);
86 DI m32rxf_h_accums_get (SIM_CPU *, UINT);
87 void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
88 BI m32rxf_h_cond_get (SIM_CPU *);
89 void m32rxf_h_cond_set (SIM_CPU *, BI);
90 UQI m32rxf_h_psw_get (SIM_CPU *);
91 void m32rxf_h_psw_set (SIM_CPU *, UQI);
92 UQI m32rxf_h_bpsw_get (SIM_CPU *);
93 void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
94 UQI m32rxf_h_bbpsw_get (SIM_CPU *);
95 void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
96 BI m32rxf_h_lock_get (SIM_CPU *);
97 void m32rxf_h_lock_set (SIM_CPU *, BI);
99 /* These must be hand-written. */
100 extern CPUREG_FETCH_FN m32rxf_fetch_register;
101 extern CPUREG_STORE_FN m32rxf_store_register;
107 /* The ARGBUF struct. */
109 /* These are the baseclass definitions. */
114 /* cpu specific data follows */
118 struct { /* empty format for unspecified field list */
121 struct { /* e.g. add $dr,$sr */
126 unsigned char out_dr;
128 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
133 unsigned char out_dr;
135 struct { /* e.g. and3 $dr,$sr,$uimm16 */
140 unsigned char out_dr;
142 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
147 unsigned char out_dr;
149 struct { /* e.g. addi $dr,$simm8 */
153 unsigned char out_dr;
155 struct { /* e.g. addv $dr,$sr */
160 unsigned char out_dr;
162 struct { /* e.g. addv3 $dr,$sr,$simm16 */
167 unsigned char out_dr;
169 struct { /* e.g. addx $dr,$sr */
174 unsigned char out_dr;
176 struct { /* e.g. cmp $src1,$src2 */
179 unsigned char in_src1;
180 unsigned char in_src2;
182 struct { /* e.g. cmpi $src2,$simm16 */
185 unsigned char in_src2;
187 struct { /* e.g. cmpz $src2 */
189 unsigned char in_src2;
191 struct { /* e.g. div $dr,$sr */
196 unsigned char out_dr;
198 struct { /* e.g. ld $dr,@$sr */
202 unsigned char out_dr;
204 struct { /* e.g. ld $dr,@($slo16,$sr) */
209 unsigned char out_dr;
211 struct { /* e.g. ldb $dr,@$sr */
215 unsigned char out_dr;
217 struct { /* e.g. ldb $dr,@($slo16,$sr) */
222 unsigned char out_dr;
224 struct { /* e.g. ldh $dr,@$sr */
228 unsigned char out_dr;
230 struct { /* e.g. ldh $dr,@($slo16,$sr) */
235 unsigned char out_dr;
237 struct { /* e.g. ld $dr,@$sr+ */
241 unsigned char out_dr;
242 unsigned char out_sr;
244 struct { /* e.g. ld24 $dr,$uimm24 */
247 unsigned char out_dr;
249 struct { /* e.g. ldi8 $dr,$simm8 */
252 unsigned char out_dr;
254 struct { /* e.g. ldi16 $dr,$hash$slo16 */
257 unsigned char out_dr;
259 struct { /* e.g. lock $dr,@$sr */
263 unsigned char out_dr;
265 struct { /* e.g. machi $src1,$src2,$acc */
269 unsigned char in_src1;
270 unsigned char in_src2;
272 struct { /* e.g. mulhi $src1,$src2,$acc */
276 unsigned char in_src1;
277 unsigned char in_src2;
279 struct { /* e.g. mv $dr,$sr */
283 unsigned char out_dr;
285 struct { /* e.g. mvfachi $dr,$accs */
288 unsigned char out_dr;
290 struct { /* e.g. mvfc $dr,$scr */
293 unsigned char out_dr;
295 struct { /* e.g. mvtachi $src1,$accs */
298 unsigned char in_src1;
300 struct { /* e.g. mvtc $sr,$dcr */
305 struct { /* e.g. nop */
308 struct { /* e.g. rac $accd,$accs,$imm1 */
313 struct { /* e.g. seth $dr,$hash$hi16 */
316 unsigned char out_dr;
318 struct { /* e.g. sll3 $dr,$sr,$simm16 */
323 unsigned char out_dr;
325 struct { /* e.g. slli $dr,$uimm5 */
329 unsigned char out_dr;
331 struct { /* e.g. st $src1,@$src2 */
334 unsigned char in_src2;
335 unsigned char in_src1;
337 struct { /* e.g. st $src1,@($slo16,$src2) */
341 unsigned char in_src2;
342 unsigned char in_src1;
344 struct { /* e.g. stb $src1,@$src2 */
347 unsigned char in_src2;
348 unsigned char in_src1;
350 struct { /* e.g. stb $src1,@($slo16,$src2) */
354 unsigned char in_src2;
355 unsigned char in_src1;
357 struct { /* e.g. sth $src1,@$src2 */
360 unsigned char in_src2;
361 unsigned char in_src1;
363 struct { /* e.g. sth $src1,@($slo16,$src2) */
367 unsigned char in_src2;
368 unsigned char in_src1;
370 struct { /* e.g. st $src1,@+$src2 */
373 unsigned char in_src2;
374 unsigned char in_src1;
375 unsigned char out_src2;
377 struct { /* e.g. unlock $src1,@$src2 */
380 unsigned char in_src2;
381 unsigned char in_src1;
383 struct { /* e.g. satb $dr,$sr */
387 unsigned char out_dr;
389 struct { /* e.g. sat $dr,$sr */
393 unsigned char out_dr;
395 struct { /* e.g. sadd */
398 struct { /* e.g. macwu1 $src1,$src2 */
401 unsigned char in_src1;
402 unsigned char in_src2;
404 struct { /* e.g. msblo $src1,$src2 */
407 unsigned char in_src1;
408 unsigned char in_src2;
410 struct { /* e.g. mulwu1 $src1,$src2 */
413 unsigned char in_src1;
414 unsigned char in_src2;
416 /* cti insns, kept separately so addr_cache is in fixed place */
419 struct { /* e.g. bc.s $disp8 */
422 struct { /* e.g. bc.l $disp24 */
425 struct { /* e.g. beq $src1,$src2,$disp16 */
429 unsigned char in_src1;
430 unsigned char in_src2;
432 struct { /* e.g. beqz $src2,$disp16 */
435 unsigned char in_src2;
437 struct { /* e.g. bl.s $disp8 */
439 unsigned char out_h_gr_14;
441 struct { /* e.g. bl.l $disp24 */
443 unsigned char out_h_gr_14;
445 struct { /* e.g. bcl.s $disp8 */
447 unsigned char out_h_gr_14;
449 struct { /* e.g. bcl.l $disp24 */
451 unsigned char out_h_gr_14;
453 struct { /* e.g. bra.s $disp8 */
456 struct { /* e.g. bra.l $disp24 */
459 struct { /* e.g. jc $sr */
463 struct { /* e.g. jl $sr */
466 unsigned char out_h_gr_14;
468 struct { /* e.g. jmp $sr */
472 struct { /* e.g. rte */
475 struct { /* e.g. trap $uimm4 */
478 struct { /* e.g. sc */
487 /* Writeback handler. */
489 /* Pointer to argbuf entry for insn whose results need writing back. */
490 const struct argbuf *abuf;
492 /* x-before handler */
494 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
497 /* x-after handler */
501 /* This entry is used to terminate each pbb. */
503 /* Number of insns in pbb. */
505 /* Next pbb to execute. */
514 ??? SCACHE used to contain more than just argbuf. We could delete the
515 type entirely and always just use ARGBUF, but for future concerns and as
516 a level of abstraction it is left in. */
519 struct argbuf argbuf;
522 /* Macros to simplify extraction, reading and semantic code.
523 These define and assign the local vars that contain the insn's fields. */
525 #define EXTRACT_FMT_EMPTY_VARS \
526 /* Instruction fields. */ \
528 #define EXTRACT_FMT_EMPTY_CODE \
531 #define EXTRACT_FMT_ADD_VARS \
532 /* Instruction fields. */ \
538 #define EXTRACT_FMT_ADD_CODE \
540 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
541 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
542 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
543 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
545 #define EXTRACT_FMT_ADD3_VARS \
546 /* Instruction fields. */ \
553 #define EXTRACT_FMT_ADD3_CODE \
555 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
556 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
557 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
558 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
559 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
561 #define EXTRACT_FMT_AND3_VARS \
562 /* Instruction fields. */ \
569 #define EXTRACT_FMT_AND3_CODE \
571 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
572 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
573 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
574 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
575 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
577 #define EXTRACT_FMT_OR3_VARS \
578 /* Instruction fields. */ \
585 #define EXTRACT_FMT_OR3_CODE \
587 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
588 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
589 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
590 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
591 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
593 #define EXTRACT_FMT_ADDI_VARS \
594 /* Instruction fields. */ \
599 #define EXTRACT_FMT_ADDI_CODE \
601 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
602 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
603 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
605 #define EXTRACT_FMT_ADDV_VARS \
606 /* Instruction fields. */ \
612 #define EXTRACT_FMT_ADDV_CODE \
614 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
615 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
616 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
617 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
619 #define EXTRACT_FMT_ADDV3_VARS \
620 /* Instruction fields. */ \
627 #define EXTRACT_FMT_ADDV3_CODE \
629 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
630 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
631 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
632 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
633 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
635 #define EXTRACT_FMT_ADDX_VARS \
636 /* Instruction fields. */ \
642 #define EXTRACT_FMT_ADDX_CODE \
644 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
645 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
646 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
647 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
649 #define EXTRACT_FMT_BC8_VARS \
650 /* Instruction fields. */ \
655 #define EXTRACT_FMT_BC8_CODE \
657 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
658 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
659 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
661 #define EXTRACT_FMT_BC24_VARS \
662 /* Instruction fields. */ \
667 #define EXTRACT_FMT_BC24_CODE \
669 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
670 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
671 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
673 #define EXTRACT_FMT_BEQ_VARS \
674 /* Instruction fields. */ \
681 #define EXTRACT_FMT_BEQ_CODE \
683 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
684 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
685 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
686 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
687 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
689 #define EXTRACT_FMT_BEQZ_VARS \
690 /* Instruction fields. */ \
697 #define EXTRACT_FMT_BEQZ_CODE \
699 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
700 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
701 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
702 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
703 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
705 #define EXTRACT_FMT_BL8_VARS \
706 /* Instruction fields. */ \
711 #define EXTRACT_FMT_BL8_CODE \
713 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
714 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
715 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
717 #define EXTRACT_FMT_BL24_VARS \
718 /* Instruction fields. */ \
723 #define EXTRACT_FMT_BL24_CODE \
725 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
726 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
727 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
729 #define EXTRACT_FMT_BCL8_VARS \
730 /* Instruction fields. */ \
735 #define EXTRACT_FMT_BCL8_CODE \
737 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
738 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
739 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
741 #define EXTRACT_FMT_BCL24_VARS \
742 /* Instruction fields. */ \
747 #define EXTRACT_FMT_BCL24_CODE \
749 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
750 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
751 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
753 #define EXTRACT_FMT_BRA8_VARS \
754 /* Instruction fields. */ \
759 #define EXTRACT_FMT_BRA8_CODE \
761 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
762 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
763 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
765 #define EXTRACT_FMT_BRA24_VARS \
766 /* Instruction fields. */ \
771 #define EXTRACT_FMT_BRA24_CODE \
773 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
774 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
775 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
777 #define EXTRACT_FMT_CMP_VARS \
778 /* Instruction fields. */ \
784 #define EXTRACT_FMT_CMP_CODE \
786 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
787 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
788 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
789 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
791 #define EXTRACT_FMT_CMPI_VARS \
792 /* Instruction fields. */ \
799 #define EXTRACT_FMT_CMPI_CODE \
801 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
802 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
803 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
804 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
805 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
807 #define EXTRACT_FMT_CMPZ_VARS \
808 /* Instruction fields. */ \
814 #define EXTRACT_FMT_CMPZ_CODE \
816 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
817 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
818 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
819 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
821 #define EXTRACT_FMT_DIV_VARS \
822 /* Instruction fields. */ \
829 #define EXTRACT_FMT_DIV_CODE \
831 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
832 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
833 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
834 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
835 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
837 #define EXTRACT_FMT_JC_VARS \
838 /* Instruction fields. */ \
844 #define EXTRACT_FMT_JC_CODE \
846 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
847 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
848 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
849 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
851 #define EXTRACT_FMT_JL_VARS \
852 /* Instruction fields. */ \
858 #define EXTRACT_FMT_JL_CODE \
860 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
861 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
862 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
863 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
865 #define EXTRACT_FMT_JMP_VARS \
866 /* Instruction fields. */ \
872 #define EXTRACT_FMT_JMP_CODE \
874 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
875 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
876 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
877 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
879 #define EXTRACT_FMT_LD_VARS \
880 /* Instruction fields. */ \
886 #define EXTRACT_FMT_LD_CODE \
888 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
889 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
890 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
891 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
893 #define EXTRACT_FMT_LD_D_VARS \
894 /* Instruction fields. */ \
901 #define EXTRACT_FMT_LD_D_CODE \
903 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
904 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
905 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
906 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
907 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
909 #define EXTRACT_FMT_LDB_VARS \
910 /* Instruction fields. */ \
916 #define EXTRACT_FMT_LDB_CODE \
918 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
919 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
920 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
921 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
923 #define EXTRACT_FMT_LDB_D_VARS \
924 /* Instruction fields. */ \
931 #define EXTRACT_FMT_LDB_D_CODE \
933 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
934 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
935 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
936 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
937 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
939 #define EXTRACT_FMT_LDH_VARS \
940 /* Instruction fields. */ \
946 #define EXTRACT_FMT_LDH_CODE \
948 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
949 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
950 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
951 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
953 #define EXTRACT_FMT_LDH_D_VARS \
954 /* Instruction fields. */ \
961 #define EXTRACT_FMT_LDH_D_CODE \
963 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
964 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
965 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
966 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
967 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
969 #define EXTRACT_FMT_LD_PLUS_VARS \
970 /* Instruction fields. */ \
976 #define EXTRACT_FMT_LD_PLUS_CODE \
978 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
979 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
980 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
981 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
983 #define EXTRACT_FMT_LD24_VARS \
984 /* Instruction fields. */ \
989 #define EXTRACT_FMT_LD24_CODE \
991 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
992 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
993 f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
995 #define EXTRACT_FMT_LDI8_VARS \
996 /* Instruction fields. */ \
1000 unsigned int length;
1001 #define EXTRACT_FMT_LDI8_CODE \
1003 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1004 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1005 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
1007 #define EXTRACT_FMT_LDI16_VARS \
1008 /* Instruction fields. */ \
1014 unsigned int length;
1015 #define EXTRACT_FMT_LDI16_CODE \
1017 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1018 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1019 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1020 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1021 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1023 #define EXTRACT_FMT_LOCK_VARS \
1024 /* Instruction fields. */ \
1029 unsigned int length;
1030 #define EXTRACT_FMT_LOCK_CODE \
1032 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1033 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1034 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1035 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1037 #define EXTRACT_FMT_MACHI_A_VARS \
1038 /* Instruction fields. */ \
1044 unsigned int length;
1045 #define EXTRACT_FMT_MACHI_A_CODE \
1047 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1048 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1049 f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1050 f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1051 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1053 #define EXTRACT_FMT_MULHI_A_VARS \
1054 /* Instruction fields. */ \
1060 unsigned int length;
1061 #define EXTRACT_FMT_MULHI_A_CODE \
1063 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1064 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1065 f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1066 f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1067 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1069 #define EXTRACT_FMT_MV_VARS \
1070 /* Instruction fields. */ \
1075 unsigned int length;
1076 #define EXTRACT_FMT_MV_CODE \
1078 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1079 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1080 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1081 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1083 #define EXTRACT_FMT_MVFACHI_A_VARS \
1084 /* Instruction fields. */ \
1090 unsigned int length;
1091 #define EXTRACT_FMT_MVFACHI_A_CODE \
1093 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1094 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1095 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1096 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1097 f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1099 #define EXTRACT_FMT_MVFC_VARS \
1100 /* Instruction fields. */ \
1105 unsigned int length;
1106 #define EXTRACT_FMT_MVFC_CODE \
1108 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1109 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1110 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1111 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1113 #define EXTRACT_FMT_MVTACHI_A_VARS \
1114 /* Instruction fields. */ \
1120 unsigned int length;
1121 #define EXTRACT_FMT_MVTACHI_A_CODE \
1123 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1124 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1125 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1126 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1127 f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1129 #define EXTRACT_FMT_MVTC_VARS \
1130 /* Instruction fields. */ \
1135 unsigned int length;
1136 #define EXTRACT_FMT_MVTC_CODE \
1138 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1139 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1140 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1141 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1143 #define EXTRACT_FMT_NOP_VARS \
1144 /* Instruction fields. */ \
1149 unsigned int length;
1150 #define EXTRACT_FMT_NOP_CODE \
1152 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1153 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1154 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1155 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1157 #define EXTRACT_FMT_RAC_DSI_VARS \
1158 /* Instruction fields. */ \
1166 unsigned int length;
1167 #define EXTRACT_FMT_RAC_DSI_CODE \
1169 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1170 f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
1171 f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
1172 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1173 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1174 f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
1175 f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
1177 #define EXTRACT_FMT_RTE_VARS \
1178 /* Instruction fields. */ \
1183 unsigned int length;
1184 #define EXTRACT_FMT_RTE_CODE \
1186 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1187 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1188 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1189 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1191 #define EXTRACT_FMT_SETH_VARS \
1192 /* Instruction fields. */ \
1198 unsigned int length;
1199 #define EXTRACT_FMT_SETH_CODE \
1201 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1202 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1203 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1204 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1205 f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1207 #define EXTRACT_FMT_SLL3_VARS \
1208 /* Instruction fields. */ \
1214 unsigned int length;
1215 #define EXTRACT_FMT_SLL3_CODE \
1217 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1218 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1219 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1220 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1221 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1223 #define EXTRACT_FMT_SLLI_VARS \
1224 /* Instruction fields. */ \
1229 unsigned int length;
1230 #define EXTRACT_FMT_SLLI_CODE \
1232 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1233 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1234 f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1235 f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1237 #define EXTRACT_FMT_ST_VARS \
1238 /* Instruction fields. */ \
1243 unsigned int length;
1244 #define EXTRACT_FMT_ST_CODE \
1246 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1247 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1248 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1249 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1251 #define EXTRACT_FMT_ST_D_VARS \
1252 /* Instruction fields. */ \
1258 unsigned int length;
1259 #define EXTRACT_FMT_ST_D_CODE \
1261 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1262 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1263 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1264 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1265 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1267 #define EXTRACT_FMT_STB_VARS \
1268 /* Instruction fields. */ \
1273 unsigned int length;
1274 #define EXTRACT_FMT_STB_CODE \
1276 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1277 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1278 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1279 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1281 #define EXTRACT_FMT_STB_D_VARS \
1282 /* Instruction fields. */ \
1288 unsigned int length;
1289 #define EXTRACT_FMT_STB_D_CODE \
1291 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1292 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1293 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1294 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1295 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1297 #define EXTRACT_FMT_STH_VARS \
1298 /* Instruction fields. */ \
1303 unsigned int length;
1304 #define EXTRACT_FMT_STH_CODE \
1306 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1307 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1308 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1309 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1311 #define EXTRACT_FMT_STH_D_VARS \
1312 /* Instruction fields. */ \
1318 unsigned int length;
1319 #define EXTRACT_FMT_STH_D_CODE \
1321 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1322 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1323 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1324 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1325 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1327 #define EXTRACT_FMT_ST_PLUS_VARS \
1328 /* Instruction fields. */ \
1333 unsigned int length;
1334 #define EXTRACT_FMT_ST_PLUS_CODE \
1336 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1337 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1338 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1339 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1341 #define EXTRACT_FMT_TRAP_VARS \
1342 /* Instruction fields. */ \
1347 unsigned int length;
1348 #define EXTRACT_FMT_TRAP_CODE \
1350 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1351 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1352 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1353 f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1355 #define EXTRACT_FMT_UNLOCK_VARS \
1356 /* Instruction fields. */ \
1361 unsigned int length;
1362 #define EXTRACT_FMT_UNLOCK_CODE \
1364 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1365 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1366 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1367 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1369 #define EXTRACT_FMT_SATB_VARS \
1370 /* Instruction fields. */ \
1376 unsigned int length;
1377 #define EXTRACT_FMT_SATB_CODE \
1379 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1380 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1381 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1382 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1383 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1385 #define EXTRACT_FMT_SAT_VARS \
1386 /* Instruction fields. */ \
1392 unsigned int length;
1393 #define EXTRACT_FMT_SAT_CODE \
1395 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1396 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1397 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1398 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1399 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1401 #define EXTRACT_FMT_SADD_VARS \
1402 /* Instruction fields. */ \
1407 unsigned int length;
1408 #define EXTRACT_FMT_SADD_CODE \
1410 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1411 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1412 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1413 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1415 #define EXTRACT_FMT_MACWU1_VARS \
1416 /* Instruction fields. */ \
1421 unsigned int length;
1422 #define EXTRACT_FMT_MACWU1_CODE \
1424 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1425 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1426 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1427 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1429 #define EXTRACT_FMT_MSBLO_VARS \
1430 /* Instruction fields. */ \
1435 unsigned int length;
1436 #define EXTRACT_FMT_MSBLO_CODE \
1438 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1439 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1440 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1441 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1443 #define EXTRACT_FMT_MULWU1_VARS \
1444 /* Instruction fields. */ \
1449 unsigned int length;
1450 #define EXTRACT_FMT_MULWU1_CODE \
1452 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1453 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1454 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1455 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1457 #define EXTRACT_FMT_SC_VARS \
1458 /* Instruction fields. */ \
1463 unsigned int length;
1464 #define EXTRACT_FMT_SC_CODE \
1466 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1467 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1468 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1469 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1471 /* Queued output values of an instruction. */
1475 struct { /* empty format for unspecified field list */
1478 struct { /* e.g. add $dr,$sr */
1481 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
1484 struct { /* e.g. and3 $dr,$sr,$uimm16 */
1487 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
1490 struct { /* e.g. addi $dr,$simm8 */
1493 struct { /* e.g. addv $dr,$sr */
1497 struct { /* e.g. addv3 $dr,$sr,$simm16 */
1501 struct { /* e.g. addx $dr,$sr */
1505 struct { /* e.g. bc.s $disp8 */
1508 struct { /* e.g. bc.l $disp24 */
1511 struct { /* e.g. beq $src1,$src2,$disp16 */
1514 struct { /* e.g. beqz $src2,$disp16 */
1517 struct { /* e.g. bl.s $disp8 */
1521 struct { /* e.g. bl.l $disp24 */
1525 struct { /* e.g. bcl.s $disp8 */
1529 struct { /* e.g. bcl.l $disp24 */
1533 struct { /* e.g. bra.s $disp8 */
1536 struct { /* e.g. bra.l $disp24 */
1539 struct { /* e.g. cmp $src1,$src2 */
1542 struct { /* e.g. cmpi $src2,$simm16 */
1545 struct { /* e.g. cmpz $src2 */
1548 struct { /* e.g. div $dr,$sr */
1551 struct { /* e.g. jc $sr */
1554 struct { /* e.g. jl $sr */
1558 struct { /* e.g. jmp $sr */
1561 struct { /* e.g. ld $dr,@$sr */
1564 struct { /* e.g. ld $dr,@($slo16,$sr) */
1567 struct { /* e.g. ldb $dr,@$sr */
1570 struct { /* e.g. ldb $dr,@($slo16,$sr) */
1573 struct { /* e.g. ldh $dr,@$sr */
1576 struct { /* e.g. ldh $dr,@($slo16,$sr) */
1579 struct { /* e.g. ld $dr,@$sr+ */
1583 struct { /* e.g. ld24 $dr,$uimm24 */
1586 struct { /* e.g. ldi8 $dr,$simm8 */
1589 struct { /* e.g. ldi16 $dr,$hash$slo16 */
1592 struct { /* e.g. lock $dr,@$sr */
1596 struct { /* e.g. machi $src1,$src2,$acc */
1599 struct { /* e.g. mulhi $src1,$src2,$acc */
1602 struct { /* e.g. mv $dr,$sr */
1605 struct { /* e.g. mvfachi $dr,$accs */
1608 struct { /* e.g. mvfc $dr,$scr */
1611 struct { /* e.g. mvtachi $src1,$accs */
1614 struct { /* e.g. mvtc $sr,$dcr */
1617 struct { /* e.g. nop */
1620 struct { /* e.g. rac $accd,$accs,$imm1 */
1623 struct { /* e.g. rte */
1629 struct { /* e.g. seth $dr,$hash$hi16 */
1632 struct { /* e.g. sll3 $dr,$sr,$simm16 */
1635 struct { /* e.g. slli $dr,$uimm5 */
1638 struct { /* e.g. st $src1,@$src2 */
1640 USI h_memory_src2_idx;
1642 struct { /* e.g. st $src1,@($slo16,$src2) */
1643 SI h_memory_add__VM_src2_slo16;
1644 USI h_memory_add__VM_src2_slo16_idx;
1646 struct { /* e.g. stb $src1,@$src2 */
1648 USI h_memory_src2_idx;
1650 struct { /* e.g. stb $src1,@($slo16,$src2) */
1651 QI h_memory_add__VM_src2_slo16;
1652 USI h_memory_add__VM_src2_slo16_idx;
1654 struct { /* e.g. sth $src1,@$src2 */
1656 USI h_memory_src2_idx;
1658 struct { /* e.g. sth $src1,@($slo16,$src2) */
1659 HI h_memory_add__VM_src2_slo16;
1660 USI h_memory_add__VM_src2_slo16_idx;
1662 struct { /* e.g. st $src1,@+$src2 */
1663 SI h_memory_new_src2;
1664 USI h_memory_new_src2_idx;
1667 struct { /* e.g. trap $uimm4 */
1675 struct { /* e.g. unlock $src1,@$src2 */
1677 USI h_memory_src2_idx;
1680 struct { /* e.g. satb $dr,$sr */
1683 struct { /* e.g. sat $dr,$sr */
1686 struct { /* e.g. sadd */
1689 struct { /* e.g. macwu1 $src1,$src2 */
1692 struct { /* e.g. msblo $src1,$src2 */
1695 struct { /* e.g. mulwu1 $src1,$src2 */
1698 struct { /* e.g. sc */
1702 /* For conditionally written operands, bitmask of which ones were. */
1706 /* Collection of various things for the trace handler to use. */
1708 typedef struct trace_record {
1713 #endif /* CPU_M32RXF_H */