1 /* CPU family header for m32rbf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 1
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 #define GET_H_CR(a1) CPU (h_cr)[a1]
50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
53 #define GET_H_ACCUM() CPU (h_accum)
54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
55 /* start-sanitize-m32rx */
58 /* end-sanitize-m32rx */
59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
63 #define GET_H_COND() CPU (h_cond)
64 #define SET_H_COND(x) (CPU (h_cond) = (x))
67 #define GET_H_PSW() CPU (h_psw)
68 #define SET_H_PSW(x) (CPU (h_psw) = (x))
71 #define GET_H_BPSW() CPU (h_bpsw)
72 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
75 #define GET_H_BBPSW() CPU (h_bbpsw)
76 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
79 #define GET_H_LOCK() CPU (h_lock)
80 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
82 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
85 /* Cover fns for register access. */
86 USI m32rbf_h_pc_get (SIM_CPU *);
87 void m32rbf_h_pc_set (SIM_CPU *, USI);
88 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
89 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
90 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
91 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
92 DI m32rbf_h_accum_get (SIM_CPU *);
93 void m32rbf_h_accum_set (SIM_CPU *, DI);
94 DI m32rbf_h_accums_get (SIM_CPU *, UINT);
95 void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
96 BI m32rbf_h_cond_get (SIM_CPU *);
97 void m32rbf_h_cond_set (SIM_CPU *, BI);
98 UQI m32rbf_h_psw_get (SIM_CPU *);
99 void m32rbf_h_psw_set (SIM_CPU *, UQI);
100 UQI m32rbf_h_bpsw_get (SIM_CPU *);
101 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
102 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
103 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
104 BI m32rbf_h_lock_get (SIM_CPU *);
105 void m32rbf_h_lock_set (SIM_CPU *, BI);
107 /* These must be hand-written. */
108 extern CPUREG_FETCH_FN m32rbf_fetch_register;
109 extern CPUREG_STORE_FN m32rbf_store_register;
119 /* The ARGBUF struct. */
121 /* These are the baseclass definitions. */
124 /* cpu specific data follows */
128 struct { /* e.g. add $dr,$sr */
133 unsigned char out_dr;
135 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
140 unsigned char out_dr;
142 struct { /* e.g. and3 $dr,$sr,$uimm16 */
147 unsigned char out_dr;
149 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
154 unsigned char out_dr;
156 struct { /* e.g. addi $dr,$simm8 */
160 unsigned char out_dr;
162 struct { /* e.g. addv $dr,$sr */
167 unsigned char out_dr;
169 struct { /* e.g. addv3 $dr,$sr,$simm16 */
174 unsigned char out_dr;
176 struct { /* e.g. addx $dr,$sr */
181 unsigned char out_dr;
183 struct { /* e.g. cmp $src1,$src2 */
186 unsigned char in_src1;
187 unsigned char in_src2;
189 struct { /* e.g. cmpi $src2,$simm16 */
192 unsigned char in_src2;
194 struct { /* e.g. div $dr,$sr */
199 unsigned char out_dr;
201 struct { /* e.g. ld $dr,@$sr */
205 unsigned char out_dr;
207 struct { /* e.g. ld $dr,@($slo16,$sr) */
212 unsigned char out_dr;
214 struct { /* e.g. ldb $dr,@$sr */
218 unsigned char out_dr;
220 struct { /* e.g. ldb $dr,@($slo16,$sr) */
225 unsigned char out_dr;
227 struct { /* e.g. ldh $dr,@$sr */
231 unsigned char out_dr;
233 struct { /* e.g. ldh $dr,@($slo16,$sr) */
238 unsigned char out_dr;
240 struct { /* e.g. ld $dr,@$sr+ */
244 unsigned char out_dr;
245 unsigned char out_sr;
247 struct { /* e.g. ld24 $dr,$uimm24 */
250 unsigned char out_dr;
252 struct { /* e.g. ldi8 $dr,$simm8 */
255 unsigned char out_dr;
257 struct { /* e.g. ldi16 $dr,$hash$slo16 */
260 unsigned char out_dr;
262 struct { /* e.g. lock $dr,@$sr */
266 unsigned char out_dr;
268 struct { /* e.g. machi $src1,$src2 */
271 unsigned char in_src1;
272 unsigned char in_src2;
274 struct { /* e.g. mulhi $src1,$src2 */
277 unsigned char in_src1;
278 unsigned char in_src2;
280 struct { /* e.g. mv $dr,$sr */
284 unsigned char out_dr;
286 struct { /* e.g. mvfachi $dr */
288 unsigned char out_dr;
290 struct { /* e.g. mvfc $dr,$scr */
293 unsigned char out_dr;
295 struct { /* e.g. mvtachi $src1 */
297 unsigned char in_src1;
299 struct { /* e.g. mvtc $sr,$dcr */
304 struct { /* e.g. nop */
307 struct { /* e.g. rac */
310 struct { /* e.g. seth $dr,$hash$hi16 */
313 unsigned char out_dr;
315 struct { /* e.g. sll3 $dr,$sr,$simm16 */
320 unsigned char out_dr;
322 struct { /* e.g. slli $dr,$uimm5 */
326 unsigned char out_dr;
328 struct { /* e.g. st $src1,@$src2 */
331 unsigned char in_src2;
332 unsigned char in_src1;
334 struct { /* e.g. st $src1,@($slo16,$src2) */
338 unsigned char in_src2;
339 unsigned char in_src1;
341 struct { /* e.g. stb $src1,@$src2 */
344 unsigned char in_src2;
345 unsigned char in_src1;
347 struct { /* e.g. stb $src1,@($slo16,$src2) */
351 unsigned char in_src2;
352 unsigned char in_src1;
354 struct { /* e.g. sth $src1,@$src2 */
357 unsigned char in_src2;
358 unsigned char in_src1;
360 struct { /* e.g. sth $src1,@($slo16,$src2) */
364 unsigned char in_src2;
365 unsigned char in_src1;
367 struct { /* e.g. st $src1,@+$src2 */
370 unsigned char in_src2;
371 unsigned char in_src1;
372 unsigned char out_src2;
374 struct { /* e.g. unlock $src1,@$src2 */
377 unsigned char in_src2;
378 unsigned char in_src1;
380 /* cti insns, kept separately so addr_cache is in fixed place */
383 struct { /* e.g. bc.s $disp8 */
386 struct { /* e.g. bc.l $disp24 */
389 struct { /* e.g. beq $src1,$src2,$disp16 */
393 unsigned char in_src1;
394 unsigned char in_src2;
396 struct { /* e.g. beqz $src2,$disp16 */
399 unsigned char in_src2;
401 struct { /* e.g. bl.s $disp8 */
403 unsigned char out_h_gr_14;
405 struct { /* e.g. bl.l $disp24 */
407 unsigned char out_h_gr_14;
409 struct { /* e.g. bra.s $disp8 */
412 struct { /* e.g. bra.l $disp24 */
415 struct { /* e.g. jl $sr */
418 unsigned char out_h_gr_14;
420 struct { /* e.g. jmp $sr */
424 struct { /* e.g. rte */
427 struct { /* e.g. trap $uimm4 */
431 #if WITH_SCACHE_PBB_M32RBF
435 #if WITH_SCACHE_PBB_M32RBF
436 /* Writeback handler. */
438 /* Pointer to argbuf entry for insn whose results need writing back. */
439 const struct argbuf *abuf;
441 /* x-before handler */
443 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
446 /* x-after handler */
450 /* This entry is used to terminate each pbb. */
452 /* Number of insns in pbb. */
454 /* Next pbb to execute. */
463 ??? SCACHE used to contain more than just argbuf. We could delete the
464 type entirely and always just use ARGBUF, but for future concerns and as
465 a level of abstraction it is left in. */
468 struct argbuf argbuf;
471 /* Macros to simplify extraction, reading and semantic code.
472 These define and assign the local vars that contain the insn's fields. */
474 #define EXTRACT_FMT_ADD_VARS \
475 /* Instruction fields. */ \
481 #define EXTRACT_FMT_ADD_CODE \
483 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
484 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
485 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
486 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
488 #define EXTRACT_FMT_ADD3_VARS \
489 /* Instruction fields. */ \
496 #define EXTRACT_FMT_ADD3_CODE \
498 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
499 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
500 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
501 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
502 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
504 #define EXTRACT_FMT_AND3_VARS \
505 /* Instruction fields. */ \
512 #define EXTRACT_FMT_AND3_CODE \
514 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
515 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
516 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
517 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
518 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
520 #define EXTRACT_FMT_OR3_VARS \
521 /* Instruction fields. */ \
528 #define EXTRACT_FMT_OR3_CODE \
530 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
531 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
532 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
533 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
534 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
536 #define EXTRACT_FMT_ADDI_VARS \
537 /* Instruction fields. */ \
542 #define EXTRACT_FMT_ADDI_CODE \
544 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
545 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
546 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
548 #define EXTRACT_FMT_ADDV_VARS \
549 /* Instruction fields. */ \
555 #define EXTRACT_FMT_ADDV_CODE \
557 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
558 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
559 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
560 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
562 #define EXTRACT_FMT_ADDV3_VARS \
563 /* Instruction fields. */ \
570 #define EXTRACT_FMT_ADDV3_CODE \
572 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
573 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
574 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
575 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
576 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
578 #define EXTRACT_FMT_ADDX_VARS \
579 /* Instruction fields. */ \
585 #define EXTRACT_FMT_ADDX_CODE \
587 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
588 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
589 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
590 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
592 #define EXTRACT_FMT_BC8_VARS \
593 /* Instruction fields. */ \
598 #define EXTRACT_FMT_BC8_CODE \
600 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
601 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
602 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
604 #define EXTRACT_FMT_BC24_VARS \
605 /* Instruction fields. */ \
610 #define EXTRACT_FMT_BC24_CODE \
612 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
613 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
614 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
616 #define EXTRACT_FMT_BEQ_VARS \
617 /* Instruction fields. */ \
624 #define EXTRACT_FMT_BEQ_CODE \
626 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
627 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
628 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
629 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
630 f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
632 #define EXTRACT_FMT_BEQZ_VARS \
633 /* Instruction fields. */ \
640 #define EXTRACT_FMT_BEQZ_CODE \
642 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
643 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
644 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
645 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
646 f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
648 #define EXTRACT_FMT_BL8_VARS \
649 /* Instruction fields. */ \
654 #define EXTRACT_FMT_BL8_CODE \
656 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
657 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
658 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
660 #define EXTRACT_FMT_BL24_VARS \
661 /* Instruction fields. */ \
666 #define EXTRACT_FMT_BL24_CODE \
668 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
669 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
670 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
672 #define EXTRACT_FMT_BRA8_VARS \
673 /* Instruction fields. */ \
678 #define EXTRACT_FMT_BRA8_CODE \
680 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
681 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
682 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
684 #define EXTRACT_FMT_BRA24_VARS \
685 /* Instruction fields. */ \
690 #define EXTRACT_FMT_BRA24_CODE \
692 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
693 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
694 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
696 #define EXTRACT_FMT_CMP_VARS \
697 /* Instruction fields. */ \
703 #define EXTRACT_FMT_CMP_CODE \
705 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
706 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
707 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
708 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
710 #define EXTRACT_FMT_CMPI_VARS \
711 /* Instruction fields. */ \
718 #define EXTRACT_FMT_CMPI_CODE \
720 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
721 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
722 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
723 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
724 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
726 #define EXTRACT_FMT_DIV_VARS \
727 /* Instruction fields. */ \
734 #define EXTRACT_FMT_DIV_CODE \
736 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
737 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
738 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
739 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
740 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
742 #define EXTRACT_FMT_JL_VARS \
743 /* Instruction fields. */ \
749 #define EXTRACT_FMT_JL_CODE \
751 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
752 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
753 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
754 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
756 #define EXTRACT_FMT_JMP_VARS \
757 /* Instruction fields. */ \
763 #define EXTRACT_FMT_JMP_CODE \
765 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
766 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
767 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
768 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
770 #define EXTRACT_FMT_LD_VARS \
771 /* Instruction fields. */ \
777 #define EXTRACT_FMT_LD_CODE \
779 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
780 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
781 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
782 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
784 #define EXTRACT_FMT_LD_D_VARS \
785 /* Instruction fields. */ \
792 #define EXTRACT_FMT_LD_D_CODE \
794 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
795 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
796 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
797 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
798 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
800 #define EXTRACT_FMT_LDB_VARS \
801 /* Instruction fields. */ \
807 #define EXTRACT_FMT_LDB_CODE \
809 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
810 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
811 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
812 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
814 #define EXTRACT_FMT_LDB_D_VARS \
815 /* Instruction fields. */ \
822 #define EXTRACT_FMT_LDB_D_CODE \
824 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
825 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
826 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
827 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
828 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
830 #define EXTRACT_FMT_LDH_VARS \
831 /* Instruction fields. */ \
837 #define EXTRACT_FMT_LDH_CODE \
839 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
840 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
841 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
842 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
844 #define EXTRACT_FMT_LDH_D_VARS \
845 /* Instruction fields. */ \
852 #define EXTRACT_FMT_LDH_D_CODE \
854 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
855 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
856 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
857 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
858 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
860 #define EXTRACT_FMT_LD_PLUS_VARS \
861 /* Instruction fields. */ \
867 #define EXTRACT_FMT_LD_PLUS_CODE \
869 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
870 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
871 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
872 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
874 #define EXTRACT_FMT_LD24_VARS \
875 /* Instruction fields. */ \
880 #define EXTRACT_FMT_LD24_CODE \
882 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
883 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
884 f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
886 #define EXTRACT_FMT_LDI8_VARS \
887 /* Instruction fields. */ \
892 #define EXTRACT_FMT_LDI8_CODE \
894 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
895 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
896 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
898 #define EXTRACT_FMT_LDI16_VARS \
899 /* Instruction fields. */ \
906 #define EXTRACT_FMT_LDI16_CODE \
908 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
909 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
910 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
911 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
912 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
914 #define EXTRACT_FMT_LOCK_VARS \
915 /* Instruction fields. */ \
921 #define EXTRACT_FMT_LOCK_CODE \
923 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
924 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
925 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
926 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
928 #define EXTRACT_FMT_MACHI_VARS \
929 /* Instruction fields. */ \
935 #define EXTRACT_FMT_MACHI_CODE \
937 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
938 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
939 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
940 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
942 #define EXTRACT_FMT_MULHI_VARS \
943 /* Instruction fields. */ \
949 #define EXTRACT_FMT_MULHI_CODE \
951 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
952 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
953 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
954 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
956 #define EXTRACT_FMT_MV_VARS \
957 /* Instruction fields. */ \
963 #define EXTRACT_FMT_MV_CODE \
965 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
966 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
967 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
968 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
970 #define EXTRACT_FMT_MVFACHI_VARS \
971 /* Instruction fields. */ \
977 #define EXTRACT_FMT_MVFACHI_CODE \
979 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
980 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
981 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
982 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
984 #define EXTRACT_FMT_MVFC_VARS \
985 /* Instruction fields. */ \
991 #define EXTRACT_FMT_MVFC_CODE \
993 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
994 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
995 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
996 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
998 #define EXTRACT_FMT_MVTACHI_VARS \
999 /* Instruction fields. */ \
1004 unsigned int length;
1005 #define EXTRACT_FMT_MVTACHI_CODE \
1007 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1008 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1009 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1010 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1012 #define EXTRACT_FMT_MVTC_VARS \
1013 /* Instruction fields. */ \
1018 unsigned int length;
1019 #define EXTRACT_FMT_MVTC_CODE \
1021 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1022 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1023 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1024 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1026 #define EXTRACT_FMT_NOP_VARS \
1027 /* Instruction fields. */ \
1032 unsigned int length;
1033 #define EXTRACT_FMT_NOP_CODE \
1035 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1036 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1037 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1038 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1040 #define EXTRACT_FMT_RAC_VARS \
1041 /* Instruction fields. */ \
1046 unsigned int length;
1047 #define EXTRACT_FMT_RAC_CODE \
1049 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1050 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1051 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1052 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1054 #define EXTRACT_FMT_RTE_VARS \
1055 /* Instruction fields. */ \
1060 unsigned int length;
1061 #define EXTRACT_FMT_RTE_CODE \
1063 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1064 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1065 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1066 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1068 #define EXTRACT_FMT_SETH_VARS \
1069 /* Instruction fields. */ \
1075 unsigned int length;
1076 #define EXTRACT_FMT_SETH_CODE \
1078 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1079 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1080 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1081 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1082 f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1084 #define EXTRACT_FMT_SLL3_VARS \
1085 /* Instruction fields. */ \
1091 unsigned int length;
1092 #define EXTRACT_FMT_SLL3_CODE \
1094 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1095 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1096 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1097 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1098 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1100 #define EXTRACT_FMT_SLLI_VARS \
1101 /* Instruction fields. */ \
1106 unsigned int length;
1107 #define EXTRACT_FMT_SLLI_CODE \
1109 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1110 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1111 f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1112 f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1114 #define EXTRACT_FMT_ST_VARS \
1115 /* Instruction fields. */ \
1120 unsigned int length;
1121 #define EXTRACT_FMT_ST_CODE \
1123 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1124 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1125 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1126 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1128 #define EXTRACT_FMT_ST_D_VARS \
1129 /* Instruction fields. */ \
1135 unsigned int length;
1136 #define EXTRACT_FMT_ST_D_CODE \
1138 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1139 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1140 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1141 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1142 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1144 #define EXTRACT_FMT_STB_VARS \
1145 /* Instruction fields. */ \
1150 unsigned int length;
1151 #define EXTRACT_FMT_STB_CODE \
1153 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1154 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1155 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1156 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1158 #define EXTRACT_FMT_STB_D_VARS \
1159 /* Instruction fields. */ \
1165 unsigned int length;
1166 #define EXTRACT_FMT_STB_D_CODE \
1168 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1169 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1170 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1171 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1172 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1174 #define EXTRACT_FMT_STH_VARS \
1175 /* Instruction fields. */ \
1180 unsigned int length;
1181 #define EXTRACT_FMT_STH_CODE \
1183 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1184 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1185 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1186 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1188 #define EXTRACT_FMT_STH_D_VARS \
1189 /* Instruction fields. */ \
1195 unsigned int length;
1196 #define EXTRACT_FMT_STH_D_CODE \
1198 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1199 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1200 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1201 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1202 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1204 #define EXTRACT_FMT_ST_PLUS_VARS \
1205 /* Instruction fields. */ \
1210 unsigned int length;
1211 #define EXTRACT_FMT_ST_PLUS_CODE \
1213 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1214 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1215 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1216 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1218 #define EXTRACT_FMT_TRAP_VARS \
1219 /* Instruction fields. */ \
1224 unsigned int length;
1225 #define EXTRACT_FMT_TRAP_CODE \
1227 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1228 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1229 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1230 f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1232 #define EXTRACT_FMT_UNLOCK_VARS \
1233 /* Instruction fields. */ \
1238 unsigned int length;
1239 #define EXTRACT_FMT_UNLOCK_CODE \
1241 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1242 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1243 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1244 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1246 #endif /* CPU_M32RBF_H */