1 /* CPU family header for m32rbf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2014 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, see <http://www.gnu.org/licenses/>.
27 /* Maximum number of instructions that are fetched at a time.
28 This is for LIW type instructions sets (e.g. m32r). */
29 #define MAX_LIW_INSNS 2
31 /* Maximum number of instructions that can be executed in parallel. */
32 #define MAX_PARALLEL_INSNS 1
34 /* The size of an "int" needed to hold an instruction word.
35 This is usually 32 bits, but some architectures needs 64 bits. */
36 typedef CGEN_INSN_INT CGEN_INSN_WORD;
38 #include "cgen-engine.h"
40 /* CPU state information. */
42 /* Hardware elements. */
46 #define GET_H_PC() CPU (h_pc)
47 #define SET_H_PC(x) (CPU (h_pc) = (x))
48 /* general registers */
50 #define GET_H_GR(a1) CPU (h_gr)[a1]
51 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
52 /* control registers */
54 #define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
55 #define SET_H_CR(index, x) \
57 m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
61 #define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
62 #define SET_H_ACCUM(x) \
64 m32rbf_h_accum_set_handler (current_cpu, (x));\
68 #define GET_H_COND() CPU (h_cond)
69 #define SET_H_COND(x) (CPU (h_cond) = (x))
72 #define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
73 #define SET_H_PSW(x) \
75 m32rbf_h_psw_set_handler (current_cpu, (x));\
79 #define GET_H_BPSW() CPU (h_bpsw)
80 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
83 #define GET_H_BBPSW() CPU (h_bbpsw)
84 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
87 #define GET_H_LOCK() CPU (h_lock)
88 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
90 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
93 /* Cover fns for register access. */
94 USI m32rbf_h_pc_get (SIM_CPU *);
95 void m32rbf_h_pc_set (SIM_CPU *, USI);
96 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
97 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
98 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
99 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
100 DI m32rbf_h_accum_get (SIM_CPU *);
101 void m32rbf_h_accum_set (SIM_CPU *, DI);
102 BI m32rbf_h_cond_get (SIM_CPU *);
103 void m32rbf_h_cond_set (SIM_CPU *, BI);
104 UQI m32rbf_h_psw_get (SIM_CPU *);
105 void m32rbf_h_psw_set (SIM_CPU *, UQI);
106 UQI m32rbf_h_bpsw_get (SIM_CPU *);
107 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
108 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
109 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
110 BI m32rbf_h_lock_get (SIM_CPU *);
111 void m32rbf_h_lock_set (SIM_CPU *, BI);
113 /* These must be hand-written. */
114 extern CPUREG_FETCH_FN m32rbf_fetch_register;
115 extern CPUREG_STORE_FN m32rbf_store_register;
125 /* Instruction argument buffer. */
128 struct { /* no operands */
139 unsigned char out_h_gr_SI_14;
143 unsigned char out_h_gr_SI_14;
149 unsigned char out_dr;
155 unsigned char out_dr;
161 unsigned char out_h_gr_SI_14;
175 unsigned char out_dr;
182 unsigned char out_dr;
189 unsigned char in_src1;
190 unsigned char in_src2;
191 unsigned char out_src2;
199 unsigned char in_src1;
200 unsigned char in_src2;
208 unsigned char out_dr;
209 unsigned char out_sr;
217 unsigned char in_src1;
218 unsigned char in_src2;
227 unsigned char out_dr;
236 unsigned char out_dr;
245 unsigned char out_dr;
248 /* Writeback handler. */
250 /* Pointer to argbuf entry for insn whose results need writing back. */
251 const struct argbuf *abuf;
253 /* x-before handler */
255 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
258 /* x-after handler */
262 /* This entry is used to terminate each pbb. */
264 /* Number of insns in pbb. */
266 /* Next pbb to execute. */
268 SCACHE *branch_target;
273 /* The ARGBUF struct. */
275 /* These are the baseclass definitions. */
280 /* ??? Temporary hack for skip insns. */
283 /* cpu specific data follows */
286 union sem_fields fields;
291 ??? SCACHE used to contain more than just argbuf. We could delete the
292 type entirely and always just use ARGBUF, but for future concerns and as
293 a level of abstraction it is left in. */
296 struct argbuf argbuf;
299 /* Macros to simplify extraction, reading and semantic code.
300 These define and assign the local vars that contain the insn's fields. */
302 #define EXTRACT_IFMT_EMPTY_VARS \
304 #define EXTRACT_IFMT_EMPTY_CODE \
307 #define EXTRACT_IFMT_ADD_VARS \
313 #define EXTRACT_IFMT_ADD_CODE \
315 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
316 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
317 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
318 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
320 #define EXTRACT_IFMT_ADD3_VARS \
327 #define EXTRACT_IFMT_ADD3_CODE \
329 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
330 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
331 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
332 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
333 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
335 #define EXTRACT_IFMT_AND3_VARS \
342 #define EXTRACT_IFMT_AND3_CODE \
344 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
345 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
346 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
347 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
348 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
350 #define EXTRACT_IFMT_OR3_VARS \
357 #define EXTRACT_IFMT_OR3_CODE \
359 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
360 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
361 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
362 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
363 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
365 #define EXTRACT_IFMT_ADDI_VARS \
370 #define EXTRACT_IFMT_ADDI_CODE \
372 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
373 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
374 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
376 #define EXTRACT_IFMT_ADDV3_VARS \
383 #define EXTRACT_IFMT_ADDV3_CODE \
385 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
386 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
387 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
388 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
389 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
391 #define EXTRACT_IFMT_BC8_VARS \
396 #define EXTRACT_IFMT_BC8_CODE \
398 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
399 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
400 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
402 #define EXTRACT_IFMT_BC24_VARS \
407 #define EXTRACT_IFMT_BC24_CODE \
409 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
410 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
411 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
413 #define EXTRACT_IFMT_BEQ_VARS \
420 #define EXTRACT_IFMT_BEQ_CODE \
422 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
423 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
424 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
425 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
426 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
428 #define EXTRACT_IFMT_BEQZ_VARS \
435 #define EXTRACT_IFMT_BEQZ_CODE \
437 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
438 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
439 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
440 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
441 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
443 #define EXTRACT_IFMT_CMP_VARS \
449 #define EXTRACT_IFMT_CMP_CODE \
451 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
452 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
453 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
454 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
456 #define EXTRACT_IFMT_CMPI_VARS \
463 #define EXTRACT_IFMT_CMPI_CODE \
465 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
466 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
467 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
468 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
469 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
471 #define EXTRACT_IFMT_DIV_VARS \
478 #define EXTRACT_IFMT_DIV_CODE \
480 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
481 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
482 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
483 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
484 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
486 #define EXTRACT_IFMT_JL_VARS \
492 #define EXTRACT_IFMT_JL_CODE \
494 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
495 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
496 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
497 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
499 #define EXTRACT_IFMT_LD24_VARS \
504 #define EXTRACT_IFMT_LD24_CODE \
506 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
507 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
508 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
510 #define EXTRACT_IFMT_LDI16_VARS \
517 #define EXTRACT_IFMT_LDI16_CODE \
519 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
520 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
521 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
522 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
523 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
525 #define EXTRACT_IFMT_MVFACHI_VARS \
531 #define EXTRACT_IFMT_MVFACHI_CODE \
533 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
534 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
535 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
536 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
538 #define EXTRACT_IFMT_MVFC_VARS \
544 #define EXTRACT_IFMT_MVFC_CODE \
546 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
547 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
548 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
549 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
551 #define EXTRACT_IFMT_MVTACHI_VARS \
557 #define EXTRACT_IFMT_MVTACHI_CODE \
559 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
560 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
561 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
562 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
564 #define EXTRACT_IFMT_MVTC_VARS \
570 #define EXTRACT_IFMT_MVTC_CODE \
572 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
573 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
574 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
575 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
577 #define EXTRACT_IFMT_NOP_VARS \
583 #define EXTRACT_IFMT_NOP_CODE \
585 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
586 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
587 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
588 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
590 #define EXTRACT_IFMT_SETH_VARS \
597 #define EXTRACT_IFMT_SETH_CODE \
599 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
600 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
601 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
602 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
603 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
605 #define EXTRACT_IFMT_SLLI_VARS \
611 #define EXTRACT_IFMT_SLLI_CODE \
613 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
614 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
615 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
616 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
618 #define EXTRACT_IFMT_ST_D_VARS \
625 #define EXTRACT_IFMT_ST_D_CODE \
627 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
628 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
629 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
630 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
631 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
633 #define EXTRACT_IFMT_TRAP_VARS \
639 #define EXTRACT_IFMT_TRAP_CODE \
641 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
642 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
643 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
644 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
646 #define EXTRACT_IFMT_CLRPSW_VARS \
651 #define EXTRACT_IFMT_CLRPSW_CODE \
653 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
654 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
655 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
657 #define EXTRACT_IFMT_BSET_VARS \
665 #define EXTRACT_IFMT_BSET_CODE \
667 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
668 f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
669 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
670 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
671 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
672 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
674 #define EXTRACT_IFMT_BTST_VARS \
681 #define EXTRACT_IFMT_BTST_CODE \
683 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
684 f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
685 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
686 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
687 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
689 /* Collection of various things for the trace handler to use. */
691 typedef struct trace_record {
696 #endif /* CPU_M32RBF_H */