1 /* Simulator instruction semantics for lm32bf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2005 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
27 /* The labels have the case they have because the enum of insn types
28 is all uppercase and in the non-stdc case the insn symbol is built
29 into the enum name. */
35 { LM32BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
36 { LM32BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
37 { LM32BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
38 { LM32BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
39 { LM32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
40 { LM32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
41 { LM32BF_INSN_ADD, && case_sem_INSN_ADD },
42 { LM32BF_INSN_ADDI, && case_sem_INSN_ADDI },
43 { LM32BF_INSN_AND, && case_sem_INSN_AND },
44 { LM32BF_INSN_ANDI, && case_sem_INSN_ANDI },
45 { LM32BF_INSN_ANDHII, && case_sem_INSN_ANDHII },
46 { LM32BF_INSN_B, && case_sem_INSN_B },
47 { LM32BF_INSN_BI, && case_sem_INSN_BI },
48 { LM32BF_INSN_BE, && case_sem_INSN_BE },
49 { LM32BF_INSN_BG, && case_sem_INSN_BG },
50 { LM32BF_INSN_BGE, && case_sem_INSN_BGE },
51 { LM32BF_INSN_BGEU, && case_sem_INSN_BGEU },
52 { LM32BF_INSN_BGU, && case_sem_INSN_BGU },
53 { LM32BF_INSN_BNE, && case_sem_INSN_BNE },
54 { LM32BF_INSN_CALL, && case_sem_INSN_CALL },
55 { LM32BF_INSN_CALLI, && case_sem_INSN_CALLI },
56 { LM32BF_INSN_CMPE, && case_sem_INSN_CMPE },
57 { LM32BF_INSN_CMPEI, && case_sem_INSN_CMPEI },
58 { LM32BF_INSN_CMPG, && case_sem_INSN_CMPG },
59 { LM32BF_INSN_CMPGI, && case_sem_INSN_CMPGI },
60 { LM32BF_INSN_CMPGE, && case_sem_INSN_CMPGE },
61 { LM32BF_INSN_CMPGEI, && case_sem_INSN_CMPGEI },
62 { LM32BF_INSN_CMPGEU, && case_sem_INSN_CMPGEU },
63 { LM32BF_INSN_CMPGEUI, && case_sem_INSN_CMPGEUI },
64 { LM32BF_INSN_CMPGU, && case_sem_INSN_CMPGU },
65 { LM32BF_INSN_CMPGUI, && case_sem_INSN_CMPGUI },
66 { LM32BF_INSN_CMPNE, && case_sem_INSN_CMPNE },
67 { LM32BF_INSN_CMPNEI, && case_sem_INSN_CMPNEI },
68 { LM32BF_INSN_DIVU, && case_sem_INSN_DIVU },
69 { LM32BF_INSN_LB, && case_sem_INSN_LB },
70 { LM32BF_INSN_LBU, && case_sem_INSN_LBU },
71 { LM32BF_INSN_LH, && case_sem_INSN_LH },
72 { LM32BF_INSN_LHU, && case_sem_INSN_LHU },
73 { LM32BF_INSN_LW, && case_sem_INSN_LW },
74 { LM32BF_INSN_MODU, && case_sem_INSN_MODU },
75 { LM32BF_INSN_MUL, && case_sem_INSN_MUL },
76 { LM32BF_INSN_MULI, && case_sem_INSN_MULI },
77 { LM32BF_INSN_NOR, && case_sem_INSN_NOR },
78 { LM32BF_INSN_NORI, && case_sem_INSN_NORI },
79 { LM32BF_INSN_OR, && case_sem_INSN_OR },
80 { LM32BF_INSN_ORI, && case_sem_INSN_ORI },
81 { LM32BF_INSN_ORHII, && case_sem_INSN_ORHII },
82 { LM32BF_INSN_RCSR, && case_sem_INSN_RCSR },
83 { LM32BF_INSN_SB, && case_sem_INSN_SB },
84 { LM32BF_INSN_SEXTB, && case_sem_INSN_SEXTB },
85 { LM32BF_INSN_SEXTH, && case_sem_INSN_SEXTH },
86 { LM32BF_INSN_SH, && case_sem_INSN_SH },
87 { LM32BF_INSN_SL, && case_sem_INSN_SL },
88 { LM32BF_INSN_SLI, && case_sem_INSN_SLI },
89 { LM32BF_INSN_SR, && case_sem_INSN_SR },
90 { LM32BF_INSN_SRI, && case_sem_INSN_SRI },
91 { LM32BF_INSN_SRU, && case_sem_INSN_SRU },
92 { LM32BF_INSN_SRUI, && case_sem_INSN_SRUI },
93 { LM32BF_INSN_SUB, && case_sem_INSN_SUB },
94 { LM32BF_INSN_SW, && case_sem_INSN_SW },
95 { LM32BF_INSN_USER, && case_sem_INSN_USER },
96 { LM32BF_INSN_WCSR, && case_sem_INSN_WCSR },
97 { LM32BF_INSN_XOR, && case_sem_INSN_XOR },
98 { LM32BF_INSN_XORI, && case_sem_INSN_XORI },
99 { LM32BF_INSN_XNOR, && case_sem_INSN_XNOR },
100 { LM32BF_INSN_XNORI, && case_sem_INSN_XNORI },
101 { LM32BF_INSN_BREAK, && case_sem_INSN_BREAK },
102 { LM32BF_INSN_SCALL, && case_sem_INSN_SCALL },
107 for (i = 0; labels[i].label != 0; ++i)
110 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
112 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
117 #endif /* DEFINE_LABELS */
121 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
122 off frills like tracing and profiling. */
123 /* FIXME: A better way would be to have TRACE_RESULT check for something
124 that can cause it to be optimized out. Another way would be to emit
125 special handlers into the instruction "stream". */
129 #define TRACE_RESULT(cpu, abuf, name, type, val)
133 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
134 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
136 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
143 /* Branch to next handler without going around main loop. */
144 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
145 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
147 #else /* ! WITH_SCACHE_PBB */
149 #define NEXT(vpc) BREAK (sem)
152 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
154 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
157 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
160 #endif /* ! WITH_SCACHE_PBB */
164 CASE (sem, INSN_X_INVALID) : /* --invalid-- */
166 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
167 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
168 #define FLD(f) abuf->fields.fmt_empty.f
169 int UNUSED written = 0;
170 IADDR UNUSED pc = abuf->addr;
171 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
174 /* Update the recorded pc in the cpu state struct.
175 Only necessary for WITH_SCACHE case, but to avoid the
176 conditional compilation .... */
178 /* Virtual insns have zero size. Overwrite vpc with address of next insn
179 using the default-insn-bitsize spec. When executing insns in parallel
180 we may want to queue the fault and continue execution. */
181 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
182 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
189 CASE (sem, INSN_X_AFTER) : /* --after-- */
191 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
192 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
193 #define FLD(f) abuf->fields.fmt_empty.f
194 int UNUSED written = 0;
195 IADDR UNUSED pc = abuf->addr;
196 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
199 #if WITH_SCACHE_PBB_LM32BF
200 lm32bf_pbb_after (current_cpu, sem_arg);
208 CASE (sem, INSN_X_BEFORE) : /* --before-- */
210 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
211 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
212 #define FLD(f) abuf->fields.fmt_empty.f
213 int UNUSED written = 0;
214 IADDR UNUSED pc = abuf->addr;
215 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
218 #if WITH_SCACHE_PBB_LM32BF
219 lm32bf_pbb_before (current_cpu, sem_arg);
227 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
229 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
230 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
231 #define FLD(f) abuf->fields.fmt_empty.f
232 int UNUSED written = 0;
233 IADDR UNUSED pc = abuf->addr;
234 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
237 #if WITH_SCACHE_PBB_LM32BF
239 vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg,
240 pbb_br_type, pbb_br_npc);
243 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
244 vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg,
245 CPU_PBB_BR_TYPE (current_cpu),
246 CPU_PBB_BR_NPC (current_cpu));
255 CASE (sem, INSN_X_CHAIN) : /* --chain-- */
257 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
258 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
259 #define FLD(f) abuf->fields.fmt_empty.f
260 int UNUSED written = 0;
261 IADDR UNUSED pc = abuf->addr;
262 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
265 #if WITH_SCACHE_PBB_LM32BF
266 vpc = lm32bf_pbb_chain (current_cpu, sem_arg);
277 CASE (sem, INSN_X_BEGIN) : /* --begin-- */
279 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
280 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
281 #define FLD(f) abuf->fields.fmt_empty.f
282 int UNUSED written = 0;
283 IADDR UNUSED pc = abuf->addr;
284 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
287 #if WITH_SCACHE_PBB_LM32BF
288 #if defined DEFINE_SWITCH || defined FAST_P
289 /* In the switch case FAST_P is a constant, allowing several optimizations
290 in any called inline functions. */
291 vpc = lm32bf_pbb_begin (current_cpu, FAST_P);
293 #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
294 vpc = lm32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
296 vpc = lm32bf_pbb_begin (current_cpu, 0);
306 CASE (sem, INSN_ADD) : /* add $r2,$r0,$r1 */
308 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
309 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
310 #define FLD(f) abuf->fields.sfmt_user.f
311 int UNUSED written = 0;
312 IADDR UNUSED pc = abuf->addr;
313 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
316 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
317 CPU (h_gr[FLD (f_r2)]) = opval;
318 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
325 CASE (sem, INSN_ADDI) : /* addi $r1,$r0,$imm */
327 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
328 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
329 #define FLD(f) abuf->fields.sfmt_addi.f
330 int UNUSED written = 0;
331 IADDR UNUSED pc = abuf->addr;
332 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
335 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
336 CPU (h_gr[FLD (f_r1)]) = opval;
337 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
344 CASE (sem, INSN_AND) : /* and $r2,$r0,$r1 */
346 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
347 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
348 #define FLD(f) abuf->fields.sfmt_user.f
349 int UNUSED written = 0;
350 IADDR UNUSED pc = abuf->addr;
351 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
354 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
355 CPU (h_gr[FLD (f_r2)]) = opval;
356 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
363 CASE (sem, INSN_ANDI) : /* andi $r1,$r0,$uimm */
365 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
366 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
367 #define FLD(f) abuf->fields.sfmt_andi.f
368 int UNUSED written = 0;
369 IADDR UNUSED pc = abuf->addr;
370 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
373 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
374 CPU (h_gr[FLD (f_r1)]) = opval;
375 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
382 CASE (sem, INSN_ANDHII) : /* andhi $r1,$r0,$hi16 */
384 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
385 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
386 #define FLD(f) abuf->fields.sfmt_andi.f
387 int UNUSED written = 0;
388 IADDR UNUSED pc = abuf->addr;
389 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
392 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16));
393 CPU (h_gr[FLD (f_r1)]) = opval;
394 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
401 CASE (sem, INSN_B) : /* b $r0 */
403 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
404 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
405 #define FLD(f) abuf->fields.sfmt_be.f
406 int UNUSED written = 0;
407 IADDR UNUSED pc = abuf->addr;
409 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
412 USI opval = lm32bf_b_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), FLD (f_r0));
413 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
414 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
417 SEM_BRANCH_FINI (vpc);
422 CASE (sem, INSN_BI) : /* bi $call */
424 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
425 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
426 #define FLD(f) abuf->fields.sfmt_bi.f
427 int UNUSED written = 0;
428 IADDR UNUSED pc = abuf->addr;
430 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
433 USI opval = EXTSISI (FLD (i_call));
434 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
435 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
438 SEM_BRANCH_FINI (vpc);
443 CASE (sem, INSN_BE) : /* be $r0,$r1,$branch */
445 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
446 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
447 #define FLD(f) abuf->fields.sfmt_be.f
448 int UNUSED written = 0;
449 IADDR UNUSED pc = abuf->addr;
451 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
453 if (EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
455 USI opval = FLD (i_branch);
456 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
458 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
462 abuf->written = written;
463 SEM_BRANCH_FINI (vpc);
468 CASE (sem, INSN_BG) : /* bg $r0,$r1,$branch */
470 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
471 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
472 #define FLD(f) abuf->fields.sfmt_be.f
473 int UNUSED written = 0;
474 IADDR UNUSED pc = abuf->addr;
476 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
478 if (GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
480 USI opval = FLD (i_branch);
481 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
483 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
487 abuf->written = written;
488 SEM_BRANCH_FINI (vpc);
493 CASE (sem, INSN_BGE) : /* bge $r0,$r1,$branch */
495 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
496 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
497 #define FLD(f) abuf->fields.sfmt_be.f
498 int UNUSED written = 0;
499 IADDR UNUSED pc = abuf->addr;
501 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
503 if (GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
505 USI opval = FLD (i_branch);
506 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
508 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
512 abuf->written = written;
513 SEM_BRANCH_FINI (vpc);
518 CASE (sem, INSN_BGEU) : /* bgeu $r0,$r1,$branch */
520 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
521 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
522 #define FLD(f) abuf->fields.sfmt_be.f
523 int UNUSED written = 0;
524 IADDR UNUSED pc = abuf->addr;
526 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
528 if (GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
530 USI opval = FLD (i_branch);
531 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
533 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
537 abuf->written = written;
538 SEM_BRANCH_FINI (vpc);
543 CASE (sem, INSN_BGU) : /* bgu $r0,$r1,$branch */
545 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
546 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
547 #define FLD(f) abuf->fields.sfmt_be.f
548 int UNUSED written = 0;
549 IADDR UNUSED pc = abuf->addr;
551 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
553 if (GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
555 USI opval = FLD (i_branch);
556 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
558 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
562 abuf->written = written;
563 SEM_BRANCH_FINI (vpc);
568 CASE (sem, INSN_BNE) : /* bne $r0,$r1,$branch */
570 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
571 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
572 #define FLD(f) abuf->fields.sfmt_be.f
573 int UNUSED written = 0;
574 IADDR UNUSED pc = abuf->addr;
576 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
578 if (NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
580 USI opval = FLD (i_branch);
581 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
583 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
587 abuf->written = written;
588 SEM_BRANCH_FINI (vpc);
593 CASE (sem, INSN_CALL) : /* call $r0 */
595 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
596 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
597 #define FLD(f) abuf->fields.sfmt_be.f
598 int UNUSED written = 0;
599 IADDR UNUSED pc = abuf->addr;
601 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
605 SI opval = ADDSI (pc, 4);
606 CPU (h_gr[((UINT) 29)]) = opval;
607 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
610 USI opval = CPU (h_gr[FLD (f_r0)]);
611 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
612 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
616 SEM_BRANCH_FINI (vpc);
621 CASE (sem, INSN_CALLI) : /* calli $call */
623 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
624 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
625 #define FLD(f) abuf->fields.sfmt_bi.f
626 int UNUSED written = 0;
627 IADDR UNUSED pc = abuf->addr;
629 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
633 SI opval = ADDSI (pc, 4);
634 CPU (h_gr[((UINT) 29)]) = opval;
635 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
638 USI opval = EXTSISI (FLD (i_call));
639 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
640 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
644 SEM_BRANCH_FINI (vpc);
649 CASE (sem, INSN_CMPE) : /* cmpe $r2,$r0,$r1 */
651 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
652 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
653 #define FLD(f) abuf->fields.sfmt_user.f
654 int UNUSED written = 0;
655 IADDR UNUSED pc = abuf->addr;
656 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
659 SI opval = EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
660 CPU (h_gr[FLD (f_r2)]) = opval;
661 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
668 CASE (sem, INSN_CMPEI) : /* cmpei $r1,$r0,$imm */
670 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
671 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
672 #define FLD(f) abuf->fields.sfmt_addi.f
673 int UNUSED written = 0;
674 IADDR UNUSED pc = abuf->addr;
675 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
678 SI opval = EQSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
679 CPU (h_gr[FLD (f_r1)]) = opval;
680 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
687 CASE (sem, INSN_CMPG) : /* cmpg $r2,$r0,$r1 */
689 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
690 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
691 #define FLD(f) abuf->fields.sfmt_user.f
692 int UNUSED written = 0;
693 IADDR UNUSED pc = abuf->addr;
694 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
697 SI opval = GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
698 CPU (h_gr[FLD (f_r2)]) = opval;
699 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
706 CASE (sem, INSN_CMPGI) : /* cmpgi $r1,$r0,$imm */
708 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
709 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
710 #define FLD(f) abuf->fields.sfmt_addi.f
711 int UNUSED written = 0;
712 IADDR UNUSED pc = abuf->addr;
713 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
716 SI opval = GTSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
717 CPU (h_gr[FLD (f_r1)]) = opval;
718 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
725 CASE (sem, INSN_CMPGE) : /* cmpge $r2,$r0,$r1 */
727 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
728 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
729 #define FLD(f) abuf->fields.sfmt_user.f
730 int UNUSED written = 0;
731 IADDR UNUSED pc = abuf->addr;
732 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
735 SI opval = GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
736 CPU (h_gr[FLD (f_r2)]) = opval;
737 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
744 CASE (sem, INSN_CMPGEI) : /* cmpgei $r1,$r0,$imm */
746 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
747 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
748 #define FLD(f) abuf->fields.sfmt_addi.f
749 int UNUSED written = 0;
750 IADDR UNUSED pc = abuf->addr;
751 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
754 SI opval = GESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
755 CPU (h_gr[FLD (f_r1)]) = opval;
756 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
763 CASE (sem, INSN_CMPGEU) : /* cmpgeu $r2,$r0,$r1 */
765 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
766 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
767 #define FLD(f) abuf->fields.sfmt_user.f
768 int UNUSED written = 0;
769 IADDR UNUSED pc = abuf->addr;
770 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
773 SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
774 CPU (h_gr[FLD (f_r2)]) = opval;
775 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
782 CASE (sem, INSN_CMPGEUI) : /* cmpgeui $r1,$r0,$uimm */
784 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
785 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
786 #define FLD(f) abuf->fields.sfmt_andi.f
787 int UNUSED written = 0;
788 IADDR UNUSED pc = abuf->addr;
789 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
792 SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
793 CPU (h_gr[FLD (f_r1)]) = opval;
794 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
801 CASE (sem, INSN_CMPGU) : /* cmpgu $r2,$r0,$r1 */
803 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
804 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
805 #define FLD(f) abuf->fields.sfmt_user.f
806 int UNUSED written = 0;
807 IADDR UNUSED pc = abuf->addr;
808 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
811 SI opval = GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
812 CPU (h_gr[FLD (f_r2)]) = opval;
813 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
820 CASE (sem, INSN_CMPGUI) : /* cmpgui $r1,$r0,$uimm */
822 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
823 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
824 #define FLD(f) abuf->fields.sfmt_andi.f
825 int UNUSED written = 0;
826 IADDR UNUSED pc = abuf->addr;
827 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
830 SI opval = GTUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
831 CPU (h_gr[FLD (f_r1)]) = opval;
832 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
839 CASE (sem, INSN_CMPNE) : /* cmpne $r2,$r0,$r1 */
841 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
842 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
843 #define FLD(f) abuf->fields.sfmt_user.f
844 int UNUSED written = 0;
845 IADDR UNUSED pc = abuf->addr;
846 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
849 SI opval = NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
850 CPU (h_gr[FLD (f_r2)]) = opval;
851 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
858 CASE (sem, INSN_CMPNEI) : /* cmpnei $r1,$r0,$imm */
860 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
861 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
862 #define FLD(f) abuf->fields.sfmt_addi.f
863 int UNUSED written = 0;
864 IADDR UNUSED pc = abuf->addr;
865 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
868 SI opval = NESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
869 CPU (h_gr[FLD (f_r1)]) = opval;
870 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
877 CASE (sem, INSN_DIVU) : /* divu $r2,$r0,$r1 */
879 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
880 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
881 #define FLD(f) abuf->fields.sfmt_user.f
882 int UNUSED written = 0;
883 IADDR UNUSED pc = abuf->addr;
885 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
888 USI opval = lm32bf_divu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2));
889 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
890 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
893 SEM_BRANCH_FINI (vpc);
898 CASE (sem, INSN_LB) : /* lb $r1,($r0+$imm) */
900 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
901 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
902 #define FLD(f) abuf->fields.sfmt_addi.f
903 int UNUSED written = 0;
904 IADDR UNUSED pc = abuf->addr;
905 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
908 SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
909 CPU (h_gr[FLD (f_r1)]) = opval;
910 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
917 CASE (sem, INSN_LBU) : /* lbu $r1,($r0+$imm) */
919 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
920 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
921 #define FLD(f) abuf->fields.sfmt_addi.f
922 int UNUSED written = 0;
923 IADDR UNUSED pc = abuf->addr;
924 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
927 SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
928 CPU (h_gr[FLD (f_r1)]) = opval;
929 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
936 CASE (sem, INSN_LH) : /* lh $r1,($r0+$imm) */
938 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
939 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
940 #define FLD(f) abuf->fields.sfmt_addi.f
941 int UNUSED written = 0;
942 IADDR UNUSED pc = abuf->addr;
943 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
946 SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
947 CPU (h_gr[FLD (f_r1)]) = opval;
948 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
955 CASE (sem, INSN_LHU) : /* lhu $r1,($r0+$imm) */
957 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
958 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
959 #define FLD(f) abuf->fields.sfmt_addi.f
960 int UNUSED written = 0;
961 IADDR UNUSED pc = abuf->addr;
962 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
965 SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
966 CPU (h_gr[FLD (f_r1)]) = opval;
967 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
974 CASE (sem, INSN_LW) : /* lw $r1,($r0+$imm) */
976 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
977 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
978 #define FLD(f) abuf->fields.sfmt_addi.f
979 int UNUSED written = 0;
980 IADDR UNUSED pc = abuf->addr;
981 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
984 SI opval = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))));
985 CPU (h_gr[FLD (f_r1)]) = opval;
986 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
993 CASE (sem, INSN_MODU) : /* modu $r2,$r0,$r1 */
995 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
996 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
997 #define FLD(f) abuf->fields.sfmt_user.f
998 int UNUSED written = 0;
999 IADDR UNUSED pc = abuf->addr;
1001 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1004 USI opval = lm32bf_modu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2));
1005 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1006 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1009 SEM_BRANCH_FINI (vpc);
1014 CASE (sem, INSN_MUL) : /* mul $r2,$r0,$r1 */
1016 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1017 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1018 #define FLD(f) abuf->fields.sfmt_user.f
1019 int UNUSED written = 0;
1020 IADDR UNUSED pc = abuf->addr;
1021 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1024 SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1025 CPU (h_gr[FLD (f_r2)]) = opval;
1026 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1033 CASE (sem, INSN_MULI) : /* muli $r1,$r0,$imm */
1035 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1036 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1037 #define FLD(f) abuf->fields.sfmt_addi.f
1038 int UNUSED written = 0;
1039 IADDR UNUSED pc = abuf->addr;
1040 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1043 SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
1044 CPU (h_gr[FLD (f_r1)]) = opval;
1045 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1052 CASE (sem, INSN_NOR) : /* nor $r2,$r0,$r1 */
1054 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1055 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1056 #define FLD(f) abuf->fields.sfmt_user.f
1057 int UNUSED written = 0;
1058 IADDR UNUSED pc = abuf->addr;
1059 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1062 SI opval = INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])));
1063 CPU (h_gr[FLD (f_r2)]) = opval;
1064 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1071 CASE (sem, INSN_NORI) : /* nori $r1,$r0,$uimm */
1073 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1074 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1075 #define FLD(f) abuf->fields.sfmt_andi.f
1076 int UNUSED written = 0;
1077 IADDR UNUSED pc = abuf->addr;
1078 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1081 SI opval = INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))));
1082 CPU (h_gr[FLD (f_r1)]) = opval;
1083 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1090 CASE (sem, INSN_OR) : /* or $r2,$r0,$r1 */
1092 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1093 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1094 #define FLD(f) abuf->fields.sfmt_user.f
1095 int UNUSED written = 0;
1096 IADDR UNUSED pc = abuf->addr;
1097 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1100 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1101 CPU (h_gr[FLD (f_r2)]) = opval;
1102 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1109 CASE (sem, INSN_ORI) : /* ori $r1,$r0,$lo16 */
1111 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1112 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1113 #define FLD(f) abuf->fields.sfmt_andi.f
1114 int UNUSED written = 0;
1115 IADDR UNUSED pc = abuf->addr;
1116 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1119 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
1120 CPU (h_gr[FLD (f_r1)]) = opval;
1121 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1128 CASE (sem, INSN_ORHII) : /* orhi $r1,$r0,$hi16 */
1130 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1131 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1132 #define FLD(f) abuf->fields.sfmt_andi.f
1133 int UNUSED written = 0;
1134 IADDR UNUSED pc = abuf->addr;
1135 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1138 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16));
1139 CPU (h_gr[FLD (f_r1)]) = opval;
1140 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1147 CASE (sem, INSN_RCSR) : /* rcsr $r2,$csr */
1149 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1150 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1151 #define FLD(f) abuf->fields.sfmt_rcsr.f
1152 int UNUSED written = 0;
1153 IADDR UNUSED pc = abuf->addr;
1154 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1157 SI opval = CPU (h_csr[FLD (f_csr)]);
1158 CPU (h_gr[FLD (f_r2)]) = opval;
1159 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1166 CASE (sem, INSN_SB) : /* sb ($r0+$imm),$r1 */
1168 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1169 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1170 #define FLD(f) abuf->fields.sfmt_addi.f
1171 int UNUSED written = 0;
1172 IADDR UNUSED pc = abuf->addr;
1173 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1176 QI opval = CPU (h_gr[FLD (f_r1)]);
1177 SETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1178 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1185 CASE (sem, INSN_SEXTB) : /* sextb $r2,$r0 */
1187 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1188 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1189 #define FLD(f) abuf->fields.sfmt_user.f
1190 int UNUSED written = 0;
1191 IADDR UNUSED pc = abuf->addr;
1192 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1195 SI opval = EXTQISI (TRUNCSIQI (CPU (h_gr[FLD (f_r0)])));
1196 CPU (h_gr[FLD (f_r2)]) = opval;
1197 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1204 CASE (sem, INSN_SEXTH) : /* sexth $r2,$r0 */
1206 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1207 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1208 #define FLD(f) abuf->fields.sfmt_user.f
1209 int UNUSED written = 0;
1210 IADDR UNUSED pc = abuf->addr;
1211 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1214 SI opval = EXTHISI (TRUNCSIHI (CPU (h_gr[FLD (f_r0)])));
1215 CPU (h_gr[FLD (f_r2)]) = opval;
1216 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1223 CASE (sem, INSN_SH) : /* sh ($r0+$imm),$r1 */
1225 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1226 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1227 #define FLD(f) abuf->fields.sfmt_addi.f
1228 int UNUSED written = 0;
1229 IADDR UNUSED pc = abuf->addr;
1230 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1233 HI opval = CPU (h_gr[FLD (f_r1)]);
1234 SETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1235 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1242 CASE (sem, INSN_SL) : /* sl $r2,$r0,$r1 */
1244 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1245 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1246 #define FLD(f) abuf->fields.sfmt_user.f
1247 int UNUSED written = 0;
1248 IADDR UNUSED pc = abuf->addr;
1249 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1252 SI opval = SLLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1253 CPU (h_gr[FLD (f_r2)]) = opval;
1254 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1261 CASE (sem, INSN_SLI) : /* sli $r1,$r0,$imm */
1263 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1264 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1265 #define FLD(f) abuf->fields.sfmt_addi.f
1266 int UNUSED written = 0;
1267 IADDR UNUSED pc = abuf->addr;
1268 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1271 SI opval = SLLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1272 CPU (h_gr[FLD (f_r1)]) = opval;
1273 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1280 CASE (sem, INSN_SR) : /* sr $r2,$r0,$r1 */
1282 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1283 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1284 #define FLD(f) abuf->fields.sfmt_user.f
1285 int UNUSED written = 0;
1286 IADDR UNUSED pc = abuf->addr;
1287 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1290 SI opval = SRASI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1291 CPU (h_gr[FLD (f_r2)]) = opval;
1292 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1299 CASE (sem, INSN_SRI) : /* sri $r1,$r0,$imm */
1301 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1302 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1303 #define FLD(f) abuf->fields.sfmt_addi.f
1304 int UNUSED written = 0;
1305 IADDR UNUSED pc = abuf->addr;
1306 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1309 SI opval = SRASI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1310 CPU (h_gr[FLD (f_r1)]) = opval;
1311 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1318 CASE (sem, INSN_SRU) : /* sru $r2,$r0,$r1 */
1320 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1321 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1322 #define FLD(f) abuf->fields.sfmt_user.f
1323 int UNUSED written = 0;
1324 IADDR UNUSED pc = abuf->addr;
1325 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1328 SI opval = SRLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1329 CPU (h_gr[FLD (f_r2)]) = opval;
1330 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1337 CASE (sem, INSN_SRUI) : /* srui $r1,$r0,$imm */
1339 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1340 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1341 #define FLD(f) abuf->fields.sfmt_addi.f
1342 int UNUSED written = 0;
1343 IADDR UNUSED pc = abuf->addr;
1344 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1347 SI opval = SRLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1348 CPU (h_gr[FLD (f_r1)]) = opval;
1349 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1356 CASE (sem, INSN_SUB) : /* sub $r2,$r0,$r1 */
1358 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1359 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1360 #define FLD(f) abuf->fields.sfmt_user.f
1361 int UNUSED written = 0;
1362 IADDR UNUSED pc = abuf->addr;
1363 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1366 SI opval = SUBSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1367 CPU (h_gr[FLD (f_r2)]) = opval;
1368 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1375 CASE (sem, INSN_SW) : /* sw ($r0+$imm),$r1 */
1377 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1378 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1379 #define FLD(f) abuf->fields.sfmt_addi.f
1380 int UNUSED written = 0;
1381 IADDR UNUSED pc = abuf->addr;
1382 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1385 SI opval = CPU (h_gr[FLD (f_r1)]);
1386 SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1387 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1394 CASE (sem, INSN_USER) : /* user $r2,$r0,$r1,$user */
1396 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1397 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1398 #define FLD(f) abuf->fields.sfmt_user.f
1399 int UNUSED written = 0;
1400 IADDR UNUSED pc = abuf->addr;
1401 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1404 SI opval = lm32bf_user_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]), FLD (f_user));
1405 CPU (h_gr[FLD (f_r2)]) = opval;
1406 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1413 CASE (sem, INSN_WCSR) : /* wcsr $csr,$r1 */
1415 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1416 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1417 #define FLD(f) abuf->fields.sfmt_wcsr.f
1418 int UNUSED written = 0;
1419 IADDR UNUSED pc = abuf->addr;
1420 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1422 lm32bf_wcsr_insn (current_cpu, FLD (f_csr), CPU (h_gr[FLD (f_r1)]));
1428 CASE (sem, INSN_XOR) : /* xor $r2,$r0,$r1 */
1430 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1431 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1432 #define FLD(f) abuf->fields.sfmt_user.f
1433 int UNUSED written = 0;
1434 IADDR UNUSED pc = abuf->addr;
1435 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1438 SI opval = XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1439 CPU (h_gr[FLD (f_r2)]) = opval;
1440 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1447 CASE (sem, INSN_XORI) : /* xori $r1,$r0,$uimm */
1449 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1450 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1451 #define FLD(f) abuf->fields.sfmt_andi.f
1452 int UNUSED written = 0;
1453 IADDR UNUSED pc = abuf->addr;
1454 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1457 SI opval = XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
1458 CPU (h_gr[FLD (f_r1)]) = opval;
1459 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1466 CASE (sem, INSN_XNOR) : /* xnor $r2,$r0,$r1 */
1468 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1469 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1470 #define FLD(f) abuf->fields.sfmt_user.f
1471 int UNUSED written = 0;
1472 IADDR UNUSED pc = abuf->addr;
1473 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1476 SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])));
1477 CPU (h_gr[FLD (f_r2)]) = opval;
1478 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1485 CASE (sem, INSN_XNORI) : /* xnori $r1,$r0,$uimm */
1487 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1488 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1489 #define FLD(f) abuf->fields.sfmt_andi.f
1490 int UNUSED written = 0;
1491 IADDR UNUSED pc = abuf->addr;
1492 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1495 SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))));
1496 CPU (h_gr[FLD (f_r1)]) = opval;
1497 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1504 CASE (sem, INSN_BREAK) : /* break */
1506 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1507 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1508 #define FLD(f) abuf->fields.fmt_empty.f
1509 int UNUSED written = 0;
1510 IADDR UNUSED pc = abuf->addr;
1512 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1515 USI opval = lm32bf_break_insn (current_cpu, pc);
1516 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1517 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1520 SEM_BRANCH_FINI (vpc);
1525 CASE (sem, INSN_SCALL) : /* scall */
1527 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1528 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1529 #define FLD(f) abuf->fields.fmt_empty.f
1530 int UNUSED written = 0;
1531 IADDR UNUSED pc = abuf->addr;
1533 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1536 USI opval = lm32bf_scall_insn (current_cpu, pc);
1537 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1538 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1541 SEM_BRANCH_FINI (vpc);
1548 ENDSWITCH (sem) /* End of semantic switch. */
1550 /* At this point `vpc' contains the next insn to execute. */
1553 #undef DEFINE_SWITCH
1554 #endif /* DEFINE_SWITCH */