1 /* Lattice Mico32 UART model.
2 Contributed by Jon Beniston <jon@beniston.com>
4 Copyright (C) 2009-2017 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "sim-assert.h"
30 unsigned base; /* Base address of this UART. */
31 unsigned limit; /* Limit address of this UART. */
41 struct hw_event *event;
46 #define LM32_UART_RBR 0x0
47 #define LM32_UART_THR 0x0
48 #define LM32_UART_IER 0x4
49 #define LM32_UART_IIR 0x8
50 #define LM32_UART_LCR 0xc
51 #define LM32_UART_MCR 0x10
52 #define LM32_UART_LSR 0x14
53 #define LM32_UART_MSR 0x18
54 #define LM32_UART_DIV 0x1c
56 #define LM32_UART_IER_RX_INT 0x1
57 #define LM32_UART_IER_TX_INT 0x2
59 #define MICOUART_IIR_TXRDY 0x2
60 #define MICOUART_IIR_RXRDY 0x4
62 #define LM32_UART_LSR_RX_RDY 0x01
63 #define LM32_UART_LSR_TX_RDY 0x20
65 #define LM32_UART_LCR_WLS_MASK 0x3
66 #define LM32_UART_LCR_WLS_5 0x0
67 #define LM32_UART_LCR_WLS_6 0x1
68 #define LM32_UART_LCR_WLS_7 0x2
69 #define LM32_UART_LCR_WLS_8 0x3
78 static const struct hw_port_descriptor lm32uart_ports[] = {
79 {"int", INT_PORT, 0, output_port},
84 do_uart_tx_event (struct hw *me, void *data)
86 struct lm32uart *uart = hw_data (me);
89 /* Generate interrupt when transmission is complete. */
90 if (uart->ier & LM32_UART_IER_TX_INT)
92 /* Generate interrupt */
93 hw_port_event (me, INT_PORT, 1);
96 /* Indicate which interrupt has occured. */
97 uart->iir = MICOUART_IIR_TXRDY;
99 /* Indicate THR is empty. */
100 uart->lsr |= LM32_UART_LSR_TX_RDY;
102 /* Output the character in the THR. */
103 c = (char) uart->thr;
105 /* WLS field in LCR register specifies the number of bits to output. */
106 switch (uart->lcr & LM32_UART_LCR_WLS_MASK)
108 case LM32_UART_LCR_WLS_5:
111 case LM32_UART_LCR_WLS_6:
114 case LM32_UART_LCR_WLS_7:
122 lm32uart_io_write_buffer (struct hw *me,
124 int space, unsigned_word base, unsigned nr_bytes)
126 struct lm32uart *uart = hw_data (me);
128 const unsigned char *source_bytes = source;
131 HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,
132 (int) nr_bytes, value));
135 value = (source_bytes[0] << 24)
136 | (source_bytes[1] << 16) | (source_bytes[2] << 8) | (source_bytes[3]);
138 hw_abort (me, "write of unsupported number of bytes: %d.", nr_bytes);
140 uart_reg = base - uart->base;
145 /* Buffer the character to output. */
148 /* Indicate the THR is full. */
149 uart->lsr &= ~LM32_UART_LSR_TX_RDY;
151 /* deassert interrupt when IER is loaded. */
152 uart->iir &= ~MICOUART_IIR_TXRDY;
154 /* schedule an event to output the character. */
155 hw_event_queue_schedule (me, 1, do_uart_tx_event, 0);
160 if ((value & LM32_UART_IER_TX_INT)
161 && (uart->lsr & LM32_UART_LSR_TX_RDY))
163 /* hw_event_queue_schedule (me, 1, do_uart_tx_event, 0); */
164 uart->lsr |= LM32_UART_LSR_TX_RDY;
165 uart->iir |= MICOUART_IIR_TXRDY;
166 hw_port_event (me, INT_PORT, 1);
168 else if ((value & LM32_UART_IER_TX_INT) == 0)
170 hw_port_event (me, INT_PORT, 0);
192 hw_abort (me, "write to invalid register address: 0x%x.", uart_reg);
199 lm32uart_io_read_buffer (struct hw *me,
201 int space, unsigned_word base, unsigned nr_bytes)
203 struct lm32uart *uart = hw_data (me);
206 unsigned char *dest_bytes = dest;
210 HW_TRACE ((me, "read 0x%08lx length %d", (long) base, (int) nr_bytes));
212 uart_reg = base - uart->base;
218 uart->lsr &= ~LM32_UART_LSR_RX_RDY;
233 /* Check to see if any data waiting in stdin. */
235 FD_SET (fileno (stdin), &fd);
238 if (select (fileno (stdin) + 1, &fd, NULL, NULL, &tv))
239 uart->lsr |= LM32_UART_LSR_RX_RDY;
249 hw_abort (me, "read from invalid register address: 0x%x.", uart_reg);
254 dest_bytes[0] = value >> 24;
255 dest_bytes[1] = value >> 16;
256 dest_bytes[2] = value >> 8;
257 dest_bytes[3] = value;
260 hw_abort (me, "read of unsupported number of bytes: %d", nr_bytes);
266 attach_lm32uart_regs (struct hw *me, struct lm32uart *uart)
268 unsigned_word attach_address;
270 unsigned attach_size;
271 reg_property_spec reg;
273 if (hw_find_property (me, "reg") == NULL)
274 hw_abort (me, "Missing \"reg\" property");
275 if (!hw_find_reg_array_property (me, "reg", 0, ®))
276 hw_abort (me, "\"reg\" property must contain three addr/size entries");
277 hw_unit_address_to_attach_address (hw_parent (me),
279 &attach_space, &attach_address, me);
280 uart->base = attach_address;
281 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
282 uart->limit = attach_address + (attach_size - 1);
283 hw_attach_address (hw_parent (me),
284 0, attach_space, attach_address, attach_size, me);
288 lm32uart_finish (struct hw *me)
290 struct lm32uart *uart;
293 uart = HW_ZALLOC (me, struct lm32uart);
294 set_hw_data (me, uart);
295 set_hw_io_read_buffer (me, lm32uart_io_read_buffer);
296 set_hw_io_write_buffer (me, lm32uart_io_write_buffer);
297 set_hw_ports (me, lm32uart_ports);
299 /* Attach ourself to our parent bus. */
300 attach_lm32uart_regs (me, uart);
302 /* Initialize the UART. */
309 uart->lsr = LM32_UART_LSR_TX_RDY;
311 uart->div = 0; /* By setting to zero, characters are output immediately. */
314 const struct hw_descriptor dv_lm32uart_descriptor[] = {
315 {"lm32uart", lm32uart_finish,},