2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
36 #include "remote-sim.h"
44 host_callback *sim_callback;
46 static SIM_OPEN_KIND sim_kind;
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
53 void sim_set_simcache_size PARAMS ((int));
55 #define X(op, size) op * 4 + size
57 #define SP (h8300hmode ? SL : SW)
70 #define h8_opcodes ops
72 #include "opcode/h8300.h"
76 /* The rate at which to call the host's poll_quit callback. */
78 #define POLL_QUIT_INTERVAL 0x80000
80 #define LOW_BYTE(x) ((x) & 0xff)
81 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
82 #define P(X,Y) ((X << 8) | Y)
84 #define BUILDSR() cpu.ccr = (I << 7) | (UI << 6)| (H<<5) | (U<<4) | \
85 (N << 3) | (Z << 2) | (V<<1) | C;
88 c = (cpu.ccr >> 0) & 1;\
89 v = (cpu.ccr >> 1) & 1;\
90 nz = !((cpu.ccr >> 2) & 1);\
91 n = (cpu.ccr >> 3) & 1;\
92 u = (cpu.ccr >> 4) & 1;\
93 h = (cpu.ccr >> 5) & 1;\
94 ui = ((cpu.ccr >> 6) & 1);\
95 intMaskBit = (cpu.ccr >> 7) & 1;
97 #ifdef __CHAR_IS_SIGNED__
98 #define SEXTCHAR(x) ((char) (x))
102 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
105 #define UEXTCHAR(x) ((x) & 0xff)
106 #define UEXTSHORT(x) ((x) & 0xffff)
107 #define SEXTSHORT(x) ((short) (x))
109 static cpu_state_type cpu;
114 static int memory_size;
119 return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */
140 return h8300hmode ? SL : SW;
152 return X (OP_IMM, SP);
154 return X (OP_REG, SP);
157 return X (OP_MEM, SP);
160 abort (); /* ?? May be something more usefull? */
165 decode (addr, data, dst)
183 /* Find the exact opcode/arg combo. */
184 for (q = h8_opcodes; q->name; q++)
186 op_type *nib = q->data.nib;
187 unsigned int len = 0;
191 op_type looking_for = *nib;
192 int thisnib = data[len >> 1];
194 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
196 if (looking_for < 16 && looking_for >= 0)
198 if (looking_for != thisnib)
203 if ((int) looking_for & (int) B31)
205 if (!(((int) thisnib & 0x8) != 0))
208 looking_for = (op_type) ((int) looking_for & ~(int) B31);
212 if ((int) looking_for & (int) B30)
214 if (!(((int) thisnib & 0x8) == 0))
217 looking_for = (op_type) ((int) looking_for & ~(int) B30);
220 if (looking_for & DBIT)
222 /* Exclude adds/subs by looking at bit 0 and 2, and
223 make sure the operand size, either w or l,
224 matches by looking at bit 1. */
225 if ((looking_for & 7) != (thisnib & 7))
228 abs = (thisnib & 0x8) ? 2 : 1;
230 else if (looking_for & (REG | IND | INC | DEC))
232 if (looking_for & REG)
234 /* Can work out size from the register. */
235 size = bitfrom (looking_for);
237 if (looking_for & SRC)
242 else if (looking_for & L_16)
244 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
246 if (looking_for & (PCREL | DISP))
251 else if (looking_for & ABSJMP)
253 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
255 else if (looking_for & MEMIND)
259 else if (looking_for & L_32)
263 abs = (data[i] << 24)
264 | (data[i + 1] << 16)
270 else if (looking_for & L_24)
274 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
277 else if (looking_for & IGNORE)
281 else if (looking_for & DISPREG)
283 rdisp = thisnib & 0x7;
285 else if (looking_for & KBIT)
302 else if (looking_for & L_8)
306 if (looking_for & PCREL)
308 abs = SEXTCHAR (data[len >> 1]);
310 else if (looking_for & ABS8MEM)
313 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
314 abs |= data[len >> 1] & 0xff;
318 abs = data[len >> 1] & 0xff;
321 else if (looking_for & L_3)
327 else if (looking_for == E)
331 /* Fill in the args. */
333 op_type *args = q->args.nib;
339 int rn = (x & DST) ? rd : rs;
349 p->type = X (OP_IMM, size);
352 else if (x & (IMM | KBIT | DBIT))
354 p->type = X (OP_IMM, size);
360 Some ops (like mul) have two sizes. */
363 p->type = X (OP_REG, size);
368 p->type = X (OP_INC, size);
373 p->type = X (OP_DEC, size);
378 p->type = X (OP_DISP, size);
382 else if (x & (ABS | ABSJMP | ABS8MEM))
384 p->type = X (OP_DISP, size);
390 p->type = X (OP_MEM, size);
395 p->type = X (OP_PCREL, size);
396 p->literal = abs + addr + 2;
402 p->type = X (OP_IMM, SP);
407 p->type = X (OP_DISP, size);
409 p->reg = rdisp & 0x7;
416 printf ("Hmmmm %x", x);
422 /* But a jmp or a jsr gets automagically lvalued,
423 since we branch to their address not their
425 if (q->how == O (O_JSR, SB)
426 || q->how == O (O_JMP, SB))
428 dst->src.type = lvalue (dst->src.type, dst->src.reg);
431 if (dst->dst.type == -1)
434 dst->opcode = q->how;
435 dst->cycles = q->time;
437 /* And a jsr to 0xc4 is turned into a magic trap. */
439 if (dst->opcode == O (O_JSR, SB))
441 if (dst->src.literal == 0xc4)
443 dst->opcode = O (O_SYSCALL, SB);
447 dst->next_pc = addr + len / 2;
451 printf ("Don't understand %x \n", looking_for);
462 /* Fell off the end. */
463 dst->opcode = O (O_ILL, SB);
471 /* Find the next cache entry to use. */
472 idx = cpu.cache_top + 1;
474 if (idx >= cpu.csize)
480 /* Throw away its old meaning. */
481 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
483 /* Set to new address. */
484 cpu.cache[idx].oldpc = pc;
486 /* Fill in instruction info. */
487 decode (pc, cpu.memory + pc, cpu.cache + idx);
489 /* Point to new cache entry. */
490 cpu.cache_idx[pc] = idx;
494 static unsigned char *breg[18];
495 static unsigned short *wreg[18];
496 static unsigned int *lreg[18];
498 #define GET_B_REG(x) *(breg[x])
499 #define SET_B_REG(x,y) (*(breg[x])) = (y)
500 #define GET_W_REG(x) *(wreg[x])
501 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
503 #define GET_L_REG(x) *(lreg[x])
504 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
506 #define GET_MEMORY_L(x) \
508 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
509 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
510 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
511 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
513 #define GET_MEMORY_W(x) \
515 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
516 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
519 #define GET_MEMORY_B(x) \
520 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
522 #define SET_MEMORY_L(x,y) \
523 { register unsigned char *_p; register int __y = y; \
524 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
525 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
526 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
528 #define SET_MEMORY_W(x,y) \
529 { register unsigned char *_p; register int __y = y; \
530 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
531 _p[0] = (__y)>>8; _p[1] =(__y);}
533 #define SET_MEMORY_B(x,y) \
534 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
541 int abs = arg->literal;
548 return GET_B_REG (rn);
550 return GET_W_REG (rn);
552 return GET_L_REG (rn);
563 r = GET_MEMORY_B (t);
572 r = GET_MEMORY_W (t);
580 r = GET_MEMORY_L (t);
587 case X (OP_DISP, SB):
588 t = GET_L_REG (rn) + abs;
590 return GET_MEMORY_B (t);
592 case X (OP_DISP, SW):
593 t = GET_L_REG (rn) + abs;
595 return GET_MEMORY_W (t);
597 case X (OP_DISP, SL):
598 t = GET_L_REG (rn) + abs;
600 return GET_MEMORY_L (t);
603 t = GET_MEMORY_L (abs);
608 t = GET_MEMORY_W (abs);
613 abort (); /* ?? May be something more usefull? */
625 int abs = arg->literal;
641 t = GET_L_REG (rn) - 1;
648 t = (GET_L_REG (rn) - 2) & cpu.mask;
654 t = (GET_L_REG (rn) - 4) & cpu.mask;
659 case X (OP_DISP, SB):
660 t = GET_L_REG (rn) + abs;
665 case X (OP_DISP, SW):
666 t = GET_L_REG (rn) + abs;
671 case X (OP_DISP, SL):
672 t = GET_L_REG (rn) + abs;
708 memory_size = H8300H_MSIZE;
710 memory_size = H8300_MSIZE;
711 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
712 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
713 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
715 /* `msize' must be a power of two. */
716 if ((memory_size & (memory_size - 1)) != 0)
718 cpu.mask = memory_size - 1;
720 for (i = 0; i < 9; i++)
725 for (i = 0; i < 8; i++)
727 unsigned char *p = (unsigned char *) (cpu.regs + i);
728 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
729 unsigned short *q = (unsigned short *) (cpu.regs + i);
730 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
731 cpu.regs[i] = 0x00112233;
757 lreg[i] = &cpu.regs[i];
760 lreg[8] = &cpu.regs[8];
762 /* Initialize the seg registers. */
764 sim_set_simcache_size (CSIZE);
769 control_c (sig, code, scp, addr)
775 cpu.state = SIM_STATE_STOPPED;
776 cpu.exception = SIGINT;
786 #define I (intMaskBit != 0)
789 mop (code, bsize, sign)
802 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
803 SEXTSHORT (GET_W_REG (code->dst.reg));
805 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
806 SEXTSHORT (GET_W_REG (code->src.reg));
810 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
811 UEXTSHORT (GET_W_REG (code->dst.reg));
813 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
814 UEXTSHORT (GET_W_REG (code->src.reg));
817 result = multiplier * multiplicand;
821 n = result & (bsize ? 0x8000 : 0x80000000);
822 nz = result & (bsize ? 0xffff : 0xffffffff);
826 SET_W_REG (code->dst.reg, result);
830 SET_L_REG (code->dst.reg, result);
833 return ((n == 1) << 1) | (nz == 1);
837 #define ONOT(name, how) \
842 rd = GET_B_REG (code->src.reg); \
850 rd = GET_W_REG (code->src.reg); \
857 int hm = 0x80000000; \
858 rd = GET_L_REG (code->src.reg); \
863 #define OSHIFTS(name, how1, how2) \
868 rd = GET_B_REG (code->src.reg); \
869 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
883 rd = GET_W_REG (code->src.reg); \
884 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
897 int hm = 0x80000000; \
898 rd = GET_L_REG (code->src.reg); \
899 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
910 #define OBITOP(name,f, s, op) \
915 if (f) ea = fetch (&code->dst); \
916 m=1<< fetch(&code->src); \
918 if(s) store (&code->dst,ea); goto next; \
925 cpu.state = SIM_STATE_STOPPED;
926 cpu.exception = SIGINT;
931 sim_resume (sd, step, siggnal)
937 int tick_start = get_now ();
946 int c, nz, v, n, u, h, ui, intMaskBit;
950 prev = signal (SIGINT, control_c);
954 cpu.state = SIM_STATE_STOPPED;
955 cpu.exception = SIGTRAP;
959 cpu.state = SIM_STATE_RUNNING;
965 /* The PC should never be odd. */
979 cidx = cpu.cache_idx[pc];
980 code = cpu.cache + cidx;
983 #define ALUOP(STORE, NAME, HOW) \
984 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
985 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
986 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
989 #define LOGOP(NAME, HOW) \
990 case O(NAME,SB): HOW; goto log8;\
991 case O(NAME, SW): HOW; goto log16;\
992 case O(NAME,SL): HOW; goto log32;
999 printf ("%x %d %s\n", pc, code->opcode,
1000 code->op ? code->op->name : "**");
1002 cpu.stats[code->opcode]++;
1008 cycles += code->cycles;
1012 switch (code->opcode)
1016 * This opcode is a fake for when we get to an
1017 * instruction which hasnt been compiled
1024 case O (O_SUBX, SB):
1025 rd = fetch (&code->dst);
1026 ea = fetch (&code->src);
1031 case O (O_ADDX, SB):
1032 rd = fetch (&code->dst);
1033 ea = fetch (&code->src);
1038 #define EA ea = fetch(&code->src);
1039 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1041 ALUOP (1, O_SUB, RD_EA;
1044 ALUOP (1, O_NEG, EA;
1050 rd = GET_B_REG (code->dst.reg);
1051 ea = fetch (&code->src);
1055 rd = GET_W_REG (code->dst.reg);
1056 ea = fetch (&code->src);
1060 rd = GET_L_REG (code->dst.reg);
1061 ea = fetch (&code->src);
1066 LOGOP (O_AND, RD_EA;
1072 LOGOP (O_XOR, RD_EA;
1076 case O (O_MOV_TO_MEM, SB):
1077 res = GET_B_REG (code->src.reg);
1079 case O (O_MOV_TO_MEM, SW):
1080 res = GET_W_REG (code->src.reg);
1082 case O (O_MOV_TO_MEM, SL):
1083 res = GET_L_REG (code->src.reg);
1087 case O (O_MOV_TO_REG, SB):
1088 res = fetch (&code->src);
1089 SET_B_REG (code->dst.reg, res);
1090 goto just_flags_log8;
1091 case O (O_MOV_TO_REG, SW):
1092 res = fetch (&code->src);
1093 SET_W_REG (code->dst.reg, res);
1094 goto just_flags_log16;
1095 case O (O_MOV_TO_REG, SL):
1096 res = fetch (&code->src);
1097 SET_L_REG (code->dst.reg, res);
1098 goto just_flags_log32;
1101 case O (O_ADDS, SL):
1102 SET_L_REG (code->dst.reg,
1103 GET_L_REG (code->dst.reg)
1104 + code->src.literal);
1108 case O (O_SUBS, SL):
1109 SET_L_REG (code->dst.reg,
1110 GET_L_REG (code->dst.reg)
1111 - code->src.literal);
1115 rd = fetch (&code->dst);
1116 ea = fetch (&code->src);
1119 goto just_flags_alu8;
1122 rd = fetch (&code->dst);
1123 ea = fetch (&code->src);
1126 goto just_flags_alu16;
1129 rd = fetch (&code->dst);
1130 ea = fetch (&code->src);
1133 goto just_flags_alu32;
1137 rd = GET_B_REG (code->src.reg);
1140 SET_B_REG (code->src.reg, res);
1141 goto just_flags_inc8;
1144 rd = GET_W_REG (code->dst.reg);
1145 ea = -code->src.literal;
1147 SET_W_REG (code->dst.reg, res);
1148 goto just_flags_inc16;
1151 rd = GET_L_REG (code->dst.reg);
1152 ea = -code->src.literal;
1154 SET_L_REG (code->dst.reg, res);
1155 goto just_flags_inc32;
1159 rd = GET_B_REG (code->src.reg);
1162 SET_B_REG (code->src.reg, res);
1163 goto just_flags_inc8;
1166 rd = GET_W_REG (code->dst.reg);
1167 ea = code->src.literal;
1169 SET_W_REG (code->dst.reg, res);
1170 goto just_flags_inc16;
1173 rd = GET_L_REG (code->dst.reg);
1174 ea = code->src.literal;
1176 SET_L_REG (code->dst.reg, res);
1177 goto just_flags_inc32;
1180 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1182 case O (O_ANDC, SB):
1184 ea = code->src.literal;
1190 ea = code->src.literal;
1194 case O (O_XORC, SB):
1196 ea = code->src.literal;
1237 if (((Z || (N ^ V)) == 0))
1243 if (((Z || (N ^ V)) == 1))
1277 case O (O_SYSCALL, SB):
1279 char c = cpu.regs[2];
1280 sim_callback->write_stdout (sim_callback, &c, 1);
1284 ONOT (O_NOT, rd = ~rd; v = 0;);
1286 c = rd & hm; v = 0; rd <<= 1,
1287 c = rd & (hm >> 1); v = 0; rd <<= 2);
1289 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1290 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1292 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1293 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1295 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1296 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1298 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1299 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1301 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1302 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1304 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1305 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1307 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1308 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1312 pc = fetch (&code->src);
1320 pc = fetch (&code->src);
1327 SET_MEMORY_L (tmp, code->next_pc);
1332 SET_MEMORY_W (tmp, code->next_pc);
1339 pc = code->src.literal;
1350 pc = GET_MEMORY_L (tmp);
1355 pc = GET_MEMORY_W (tmp);
1364 cpu.state = SIM_STATE_STOPPED;
1365 cpu.exception = SIGILL;
1367 case O (O_SLEEP, SN):
1368 /* FIXME: Doesn't this break for breakpoints when r0
1369 contains just the right (er, wrong) value? */
1370 cpu.state = SIM_STATE_STOPPED;
1371 /* The format of r0 is defined by target newlib. Expand
1372 the macros here instead of looking for .../sys/wait.h. */
1373 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1374 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1375 if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0]))
1376 cpu.exception = SIGILL;
1378 cpu.exception = SIGTRAP;
1381 cpu.state = SIM_STATE_STOPPED;
1382 cpu.exception = SIGTRAP;
1385 OBITOP (O_BNOT, 1, 1, ea ^= m);
1386 OBITOP (O_BTST, 1, 0, nz = ea & m);
1387 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1388 OBITOP (O_BSET, 1, 1, ea |= m);
1389 OBITOP (O_BLD, 1, 0, c = ea & m);
1390 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1391 OBITOP (O_BST, 1, 1, ea &= ~m;
1393 OBITOP (O_BIST, 1, 1, ea &= ~m;
1395 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1396 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1397 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1398 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1399 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1400 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1402 #define MOP(bsize, signed) \
1403 mop (code, bsize, signed); \
1406 case O (O_MULS, SB):
1409 case O (O_MULS, SW):
1412 case O (O_MULU, SB):
1415 case O (O_MULU, SW):
1420 case O (O_DIVU, SB):
1422 rd = GET_W_REG (code->dst.reg);
1423 ea = GET_B_REG (code->src.reg);
1426 tmp = (unsigned) rd % ea;
1427 rd = (unsigned) rd / ea;
1429 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1435 case O (O_DIVU, SW):
1437 rd = GET_L_REG (code->dst.reg);
1438 ea = GET_W_REG (code->src.reg);
1443 tmp = (unsigned) rd % ea;
1444 rd = (unsigned) rd / ea;
1446 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1450 case O (O_DIVS, SB):
1453 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1454 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1457 tmp = (int) rd % (int) ea;
1458 rd = (int) rd / (int) ea;
1464 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1467 case O (O_DIVS, SW):
1469 rd = GET_L_REG (code->dst.reg);
1470 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1473 tmp = (int) rd % (int) ea;
1474 rd = (int) rd / (int) ea;
1475 n = rd & 0x80000000;
1480 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1483 case O (O_EXTS, SW):
1484 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1485 ea = rd & 0x80 ? -256 : 0;
1488 case O (O_EXTS, SL):
1489 rd = GET_W_REG (code->src.reg) & 0xffff;
1490 ea = rd & 0x8000 ? -65536 : 0;
1493 case O (O_EXTU, SW):
1494 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1498 case O (O_EXTU, SL):
1499 rd = GET_W_REG (code->src.reg) & 0xffff;
1509 int nregs, firstreg, i;
1511 nregs = GET_MEMORY_B (pc + 1);
1514 firstreg = GET_MEMORY_B (pc + 3);
1516 for (i = firstreg; i <= firstreg + nregs; i++)
1519 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1526 int nregs, firstreg, i;
1528 nregs = GET_MEMORY_B (pc + 1);
1531 firstreg = GET_MEMORY_B (pc + 3);
1533 for (i = firstreg; i >= firstreg - nregs; i--)
1535 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1542 cpu.state = SIM_STATE_STOPPED;
1543 cpu.exception = SIGILL;
1555 /* When a branch works */
1556 pc = code->src.literal;
1559 /* Set the cond codes from res */
1562 /* Set the flags after an 8 bit inc/dec operation */
1566 v = (rd & 0x7f) == 0x7f;
1570 /* Set the flags after an 16 bit inc/dec operation */
1574 v = (rd & 0x7fff) == 0x7fff;
1578 /* Set the flags after an 32 bit inc/dec operation */
1580 n = res & 0x80000000;
1581 nz = res & 0xffffffff;
1582 v = (rd & 0x7fffffff) == 0x7fffffff;
1587 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1590 SET_B_REG (code->src.reg, rd);
1594 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1597 SET_W_REG (code->src.reg, rd);
1601 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1602 n = (rd & 0x80000000);
1603 nz = rd & 0xffffffff;
1604 SET_L_REG (code->src.reg, rd);
1608 store (&code->dst, res);
1610 /* flags after a 32bit logical operation */
1611 n = res & 0x80000000;
1612 nz = res & 0xffffffff;
1617 store (&code->dst, res);
1619 /* flags after a 16bit logical operation */
1627 store (&code->dst, res);
1635 SET_B_REG (code->dst.reg, res);
1640 switch (code->opcode / 4)
1643 v = ((rd & 0x80) == (ea & 0x80)
1644 && (rd & 0x80) != (res & 0x80));
1648 v = ((rd & 0x80) != (-ea & 0x80)
1649 && (rd & 0x80) != (res & 0x80));
1658 SET_W_REG (code->dst.reg, res);
1662 c = (res & 0x10000);
1663 switch (code->opcode / 4)
1666 v = ((rd & 0x8000) == (ea & 0x8000)
1667 && (rd & 0x8000) != (res & 0x8000));
1671 v = ((rd & 0x8000) != (-ea & 0x8000)
1672 && (rd & 0x8000) != (res & 0x8000));
1681 SET_L_REG (code->dst.reg, res);
1683 n = res & 0x80000000;
1684 nz = res & 0xffffffff;
1685 switch (code->opcode / 4)
1688 v = ((rd & 0x80000000) == (ea & 0x80000000)
1689 && (rd & 0x80000000) != (res & 0x80000000));
1690 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1694 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1695 && (rd & 0x80000000) != (res & 0x80000000));
1696 c = (unsigned) rd < (unsigned) -ea;
1699 v = (rd == 0x80000000);
1715 if (--poll_count < 0)
1717 poll_count = POLL_QUIT_INTERVAL;
1718 if ((*sim_callback->poll_quit) != NULL
1719 && (*sim_callback->poll_quit) (sim_callback))
1724 while (cpu.state == SIM_STATE_RUNNING);
1725 cpu.ticks += get_now () - tick_start;
1726 cpu.cycles += cycles;
1732 signal (SIGINT, prev);
1739 /* FIXME: Unfinished. */
1744 sim_write (sd, addr, buffer, size)
1747 unsigned char *buffer;
1755 for (i = 0; i < size; i++)
1757 if (addr < memory_size)
1759 cpu.memory[addr + i] = buffer[i];
1760 cpu.cache_idx[addr + i] = 0;
1763 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1769 sim_read (sd, addr, buffer, size)
1772 unsigned char *buffer;
1778 if (addr < memory_size)
1779 memcpy (buffer, cpu.memory + addr, size);
1781 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1795 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1796 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1799 #define CCR_REGNUM 8 /* Contains processor status */
1800 #define PC_REGNUM 9 /* Contains program counter */
1802 #define CYCLE_REGNUM 10
1803 #define INST_REGNUM 11
1804 #define TICK_REGNUM 12
1808 sim_store_register (sd, rn, value, length)
1811 unsigned char *value;
1817 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1818 shortval = (value[0] << 8) | (value[1]);
1819 intval = h8300hmode ? longval : shortval;
1837 cpu.regs[rn] = intval;
1843 cpu.cycles = longval;
1847 cpu.insts = longval;
1851 cpu.ticks = longval;
1858 sim_fetch_register (sd, rn, buf, length)
1902 if (h8300hmode || longreg)
1918 sim_stop_reason (sd, reason, sigrc)
1920 enum sim_stop *reason;
1923 #if 0 /* FIXME: This should work but we can't use it.
1924 grep for SLEEP above. */
1927 case SIM_STATE_EXITED : *reason = sim_exited; break;
1928 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1929 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1933 *reason = sim_stopped;
1935 *sigrc = cpu.exception;
1938 /* FIXME: Rename to sim_set_mem_size. */
1944 /* Memory size is fixed. */
1948 sim_set_simcache_size (n)
1954 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1955 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1961 sim_info (sd, verbose)
1965 double timetaken = (double) cpu.ticks / (double) now_persec ();
1966 double virttime = cpu.cycles / 10.0e6;
1968 (*sim_callback->printf_filtered) (sim_callback,
1969 "\n\n#instructions executed %10d\n",
1971 (*sim_callback->printf_filtered) (sim_callback,
1972 "#cycles (v approximate) %10d\n",
1974 (*sim_callback->printf_filtered) (sim_callback,
1975 "#real time taken %10.4f\n",
1977 (*sim_callback->printf_filtered) (sim_callback,
1978 "#virtual time taked %10.4f\n",
1980 if (timetaken != 0.0)
1981 (*sim_callback->printf_filtered) (sim_callback,
1982 "#simulation ratio %10.4f\n",
1983 virttime / timetaken);
1984 (*sim_callback->printf_filtered) (sim_callback,
1987 (*sim_callback->printf_filtered) (sim_callback,
1988 "#cache size %10d\n",
1992 /* This to be conditional on `what' (aka `verbose'),
1993 however it was never passed as non-zero. */
1997 for (i = 0; i < O_LAST; i++)
2000 (*sim_callback->printf_filtered) (sim_callback,
2001 "%d: %d\n", i, cpu.stats[i]);
2007 /* Indicate whether the cpu is an H8/300 or H8/300H.
2008 FLAG is non-zero for the H8/300H. */
2014 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2015 This function being replaced by a sim_open:ARGV configuration
2021 sim_open (kind, ptr, abfd, argv)
2023 struct host_callback_struct *ptr;
2027 /* FIXME: Much of the code in sim_load can be moved here. */
2032 /* Fudge our descriptor. */
2033 return (SIM_DESC) 1;
2037 sim_close (sd, quitting)
2041 /* Nothing to do. */
2044 /* Called by gdb to load a program into memory. */
2047 sim_load (sd, prog, abfd, from_tty)
2055 /* FIXME: The code below that sets a specific variant of the H8/300
2056 being simulated should be moved to sim_open(). */
2058 /* See if the file is for the H8/300 or H8/300H. */
2059 /* ??? This may not be the most efficient way. The z8k simulator
2060 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2064 prog_bfd = bfd_openr (prog, "coff-h8300");
2065 if (prog_bfd != NULL)
2067 /* Set the cpu type. We ignore failure from bfd_check_format
2068 and bfd_openr as sim_load_file checks too. */
2069 if (bfd_check_format (prog_bfd, bfd_object))
2071 unsigned long mach = bfd_get_mach (prog_bfd);
2072 set_h8300h (mach == bfd_mach_h8300h
2073 || mach == bfd_mach_h8300s);
2077 /* If we're using gdb attached to the simulator, then we have to
2078 reallocate memory for the simulator.
2080 When gdb first starts, it calls fetch_registers (among other
2081 functions), which in turn calls init_pointers, which allocates
2084 The problem is when we do that, we don't know whether we're
2085 debugging an H8/300 or H8/300H program.
2087 This is the first point at which we can make that determination,
2088 so we just reallocate memory now; this will also allow us to handle
2089 switching between H8/300 and H8/300H programs without exiting
2092 memory_size = H8300H_MSIZE;
2094 memory_size = H8300_MSIZE;
2099 free (cpu.cache_idx);
2101 free (cpu.eightbit);
2103 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2104 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2105 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2107 /* `msize' must be a power of two. */
2108 if ((memory_size & (memory_size - 1)) != 0)
2110 cpu.mask = memory_size - 1;
2112 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2113 sim_kind == SIM_OPEN_DEBUG,
2117 /* Close the bfd if we opened it. */
2118 if (abfd == NULL && prog_bfd != NULL)
2119 bfd_close (prog_bfd);
2123 /* Close the bfd if we opened it. */
2124 if (abfd == NULL && prog_bfd != NULL)
2125 bfd_close (prog_bfd);
2130 sim_create_inferior (sd, abfd, argv, env)
2137 cpu.pc = bfd_get_start_address (abfd);
2144 sim_do_command (sd, cmd)
2148 (*sim_callback->printf_filtered) (sim_callback,
2149 "This simulator does not accept any commands.\n");
2153 sim_set_callbacks (ptr)
2154 struct host_callback_struct *ptr;