2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
29 #include <sys/param.h>
32 #include "remote-sim.h"
38 #define X(op, size) op*4+size
40 #define SP (h8300hmode ? SL:SW)
53 #define h8_opcodes ops
55 #include "opcode/h8300.h"
59 #define LOW_BYTE(x) ((x) & 0xff)
60 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
61 #define P(X,Y) ((X<<8) | Y)
63 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
66 c = (cpu.ccr >> 0) & 1;\
67 v = (cpu.ccr >> 1) & 1;\
68 nz = !((cpu.ccr >> 2) & 1);\
69 n = (cpu.ccr >> 3) & 1;
71 #ifdef __CHAR_IS_SIGNED__
72 #define SEXTCHAR(x) ((char)(x))
76 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
79 #define UEXTCHAR(x) ((x) & 0xff)
80 #define UEXTSHORT(x) ((x) & 0xffff)
81 #define SEXTSHORT(x) ((short)(x))
83 static cpu_state_type cpu;
87 static int memory_size;
118 return h8300hmode ? SL : SW;
131 return X (OP_IMM, SP);
133 return X (OP_REG, SP);
137 return X (OP_MEM, SP);
144 decode (addr, data, dst)
156 struct h8_opcode *q = h8_opcodes;
160 /* Find the exact opcode/arg combo */
164 unsigned int len = 0;
170 op_type looking_for = *nib;
171 int thisnib = data[len >> 1];
173 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
175 if (looking_for < 16 && looking_for >= 0)
177 if (looking_for != thisnib)
182 if ((int) looking_for & (int) B31)
184 if (!(((int) thisnib & 0x8) != 0))
186 looking_for = (op_type) ((int) looking_for & ~(int)
190 if ((int) looking_for & (int) B30)
192 if (!(((int) thisnib & 0x8) == 0))
194 looking_for = (op_type) ((int) looking_for & ~(int) B30);
196 if (looking_for & DBIT)
198 if ((looking_for & 5) != (thisnib & 5))
200 abs = (thisnib & 0x8) ? 2 : 1;
202 else if (looking_for & (REG | IND | INC | DEC))
204 if (looking_for & REG)
207 * Can work out size from the
210 size = bitfrom (looking_for);
212 if (looking_for & SRC)
221 else if (looking_for & L_16)
223 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
225 if (looking_for & (PCREL | DISP))
230 else if (looking_for & ABSJMP)
237 else if (looking_for & MEMIND)
241 else if (looking_for & L_32)
244 abs = (data[i] << 24)
245 | (data[i + 1] << 16)
251 else if (looking_for & L_24)
254 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
257 else if (looking_for & IGNORE)
261 else if (looking_for & DISPREG)
263 rdisp = thisnib & 0x7;
265 else if (looking_for & KBIT)
280 else if (looking_for & L_8)
284 if (looking_for & PCREL)
286 abs = SEXTCHAR (data[len >> 1]);
290 abs = data[len >> 1] & 0xff;
293 else if (looking_for & L_3)
299 else if (looking_for == E)
303 /* Fill in the args */
305 op_type *args = q->args.nib;
311 int rn = (x & DST) ? rd : rs;
323 if (x & (IMM | KBIT | DBIT))
325 p->type = X (OP_IMM, size);
330 /* Reset the size, some
331 ops (like mul) have two sizes */
334 p->type = X (OP_REG, size);
339 p->type = X (OP_INC, size);
344 p->type = X (OP_DEC, size);
349 p->type = X (OP_DISP, size);
353 else if (x & (ABS | ABSJMP | ABSMOV))
355 p->type = X (OP_DISP, size);
361 p->type = X (OP_MEM, size);
366 p->type = X (OP_PCREL, size);
367 p->literal = abs + addr + 2;
373 p->type = X (OP_IMM, SP);
378 p->type = X (OP_DISP, size);
380 p->reg = rdisp & 0x7;
387 printf ("Hmmmm %x", x);
394 * But a jmp or a jsr gets
395 * automagically lvalued, since we
396 * branch to their address not their
399 if (q->how == O (O_JSR, SB)
400 || q->how == O (O_JMP, SB))
402 dst->src.type = lvalue (dst->src.type, dst->src.reg);
405 if (dst->dst.type == -1)
408 dst->opcode = q->how;
409 dst->cycles = q->time;
411 /* And a jsr to 0xc4 is turned into a magic trap */
413 if (dst->opcode == O (O_JSR, SB))
415 if (dst->src.literal == 0xc4)
417 dst->opcode = O (O_SYSCALL, SB);
421 dst->next_pc = addr + len / 2;
426 printf ("Dont understand %x \n", looking_for);
438 dst->opcode = O (O_ILL, SB);
447 /* find the next cache entry to use */
449 idx = cpu.cache_top + 1;
451 if (idx >= cpu.csize)
457 /* Throw away its old meaning */
458 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
460 /* set to new address */
461 cpu.cache[idx].oldpc = pc;
463 /* fill in instruction info */
464 decode (pc, cpu.memory + pc, cpu.cache + idx);
466 /* point to new cache entry */
467 cpu.cache_idx[pc] = idx;
471 static unsigned char *breg[18];
472 static unsigned short *wreg[18];
473 static unsigned int *lreg[18];
475 #define GET_B_REG(x) *(breg[x])
476 #define SET_B_REG(x,y) (*(breg[x])) = (y)
477 #define GET_W_REG(x) *(wreg[x])
478 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
480 #define GET_L_REG(x) *(lreg[x])
481 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
483 #define GET_MEMORY_L(x) \
484 ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3])
486 #define GET_MEMORY_W(x) \
487 ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0))
490 #define SET_MEMORY_B(x,y) \
491 (cpu.memory[(x)] = y)
493 #define SET_MEMORY_W(x,y) \
494 {register unsigned char *_p = cpu.memory+x;\
495 register int __y = y;\
499 #define SET_MEMORY_L(x,y) \
500 {register unsigned char *_p = cpu.memory+x;register int __y = y;\
501 _p[0] = (__y)>>24; _p[1] = (__y)>>16; _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
503 #define GET_MEMORY_B(x) (cpu.memory[x])
510 int abs = arg->literal;
517 return GET_B_REG (rn);
519 return GET_W_REG (rn);
521 return GET_L_REG (rn);
532 r = GET_MEMORY_B (t);
541 r = GET_MEMORY_W (t);
549 r = GET_MEMORY_L (t);
556 case X (OP_DISP, SB):
557 t = GET_L_REG (rn) + abs;
559 return GET_MEMORY_B (t);
561 case X (OP_DISP, SW):
562 t = GET_L_REG (rn) + abs;
564 return GET_MEMORY_W (t);
566 case X (OP_DISP, SL):
567 t = GET_L_REG (rn) + abs;
569 return GET_MEMORY_L (t);
572 t = GET_MEMORY_L (abs);
590 int abs = arg->literal;
606 t = GET_L_REG (rn) - 1;
613 t = (GET_L_REG (rn) - 2) & cpu.mask;
619 t = (GET_L_REG (rn) - 4) & cpu.mask;
624 case X (OP_DISP, SB):
625 t = GET_L_REG (rn) + abs;
630 case X (OP_DISP, SW):
631 t = GET_L_REG (rn) + abs;
636 case X (OP_DISP, SL):
637 t = GET_L_REG (rn) + abs;
674 memory_size = H8300H_MSIZE;
676 memory_size = H8300_MSIZE;
677 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
678 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
680 /* `msize' must be a power of two */
681 if ((memory_size & (memory_size - 1)) != 0)
683 cpu.mask = memory_size - 1;
685 for (i = 0; i < 9; i++)
690 for (i = 0; i < 8; i++)
692 unsigned char *p = (unsigned char *) (cpu.regs + i);
693 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
694 unsigned short *q = (unsigned short *) (cpu.regs + i);
695 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
696 cpu.regs[i] = 0x00112233;
722 lreg[i] = &cpu.regs[i];
725 lreg[8] = &cpu.regs[8];
727 /* initialize the seg registers */
734 control_c (sig, code, scp, addr)
740 cpu.exception = SIGINT;
749 mop (code, bsize, sign)
762 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
763 SEXTSHORT (GET_W_REG (code->dst.reg));
765 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
766 SEXTSHORT (GET_W_REG (code->src.reg));
770 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
771 UEXTSHORT (GET_W_REG (code->dst.reg));
773 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
774 UEXTSHORT (GET_W_REG (code->src.reg));
777 result = multiplier * multiplicand;
781 n = result & (bsize ? 0x8000 : 0x80000000);
782 nz = result & (bsize ? 0xffff : 0xffffffff);
786 SET_W_REG (code->dst.reg, result);
790 SET_L_REG (code->dst.reg, result);
792 /* return ((n==1) << 1) | (nz==1); */
796 #define OSHIFTS(name, how) \
801 rd = GET_B_REG (code->src.reg); \
809 rd = GET_W_REG (code->src.reg); \
816 int hm = 0x80000000; \
817 rd = GET_L_REG (code->src.reg); \
822 #define OBITOP(name,f, s, op) \
827 if (f) ea = fetch (&code->dst); \
828 m=1<< fetch(&code->src); \
830 if(s) store (&code->dst,ea); goto next; \
834 sim_resume (step, siggnal)
839 int tick_start = get_now ();
852 prev = signal (SIGINT, control_c);
856 cpu.exception = SIGTRAP;
875 cidx = cpu.cache_idx[pc];
876 code = cpu.cache + cidx;
879 #define ALUOP(STORE, NAME, HOW) \
880 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
881 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
882 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
885 #define LOGOP(NAME, HOW) \
886 case O(NAME,SB): HOW; goto log8;\
887 case O(NAME, SW): HOW; goto log16;\
888 case O(NAME,SL): HOW; goto log32;
895 printf ("%x %d %s\n", pc, code->opcode,
896 code->op ? code->op->name : "**");
898 cpu.stats[code->opcode]++;
902 cycles += code->cycles;
904 switch (code->opcode)
908 * This opcode is a fake for when we get to an
909 * instruction which hasnt been compiled
917 rd = fetch (&code->dst);
918 ea = fetch (&code->src);
924 rd = fetch (&code->dst);
925 ea = fetch (&code->src);
930 #define EA ea = fetch(&code->src);
931 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
933 ALUOP (1, O_SUB, RD_EA;
942 rd = GET_B_REG (code->dst.reg);
943 ea = fetch (&code->src);
947 rd = GET_W_REG (code->dst.reg);
948 ea = fetch (&code->src);
952 rd = GET_L_REG (code->dst.reg);
953 ea = fetch (&code->src);
968 case O (O_MOV_TO_MEM, SB):
969 res = GET_B_REG (code->src.reg);
971 case O (O_MOV_TO_MEM, SW):
972 res = GET_W_REG (code->src.reg);
974 case O (O_MOV_TO_MEM, SL):
975 res = GET_L_REG (code->src.reg);
979 case O (O_MOV_TO_REG, SB):
980 res = fetch (&code->src);
981 SET_B_REG (code->dst.reg, res);
982 goto just_flags_log8;
983 case O (O_MOV_TO_REG, SW):
984 res = fetch (&code->src);
985 SET_W_REG (code->dst.reg, res);
986 goto just_flags_log16;
987 case O (O_MOV_TO_REG, SL):
988 res = fetch (&code->src);
989 SET_L_REG (code->dst.reg, res);
990 goto just_flags_log32;
994 SET_L_REG (code->dst.reg,
995 GET_L_REG (code->dst.reg)
996 + code->src.literal);
1000 case O (O_SUBS, SL):
1001 SET_L_REG (code->dst.reg,
1002 GET_L_REG (code->dst.reg)
1003 - code->src.literal);
1007 rd = fetch (&code->dst);
1008 ea = fetch (&code->src);
1011 goto just_flags_alu8;
1014 rd = fetch (&code->dst);
1015 ea = fetch (&code->src);
1018 goto just_flags_alu16;
1021 rd = fetch (&code->dst);
1022 ea = fetch (&code->src);
1025 goto just_flags_alu32;
1029 rd = GET_B_REG (code->src.reg);
1032 SET_B_REG (code->src.reg, res);
1033 goto just_flags_inc8;
1036 rd = GET_W_REG (code->dst.reg);
1037 ea = -code->src.literal;
1039 SET_W_REG (code->dst.reg, res);
1040 goto just_flags_inc16;
1043 rd = GET_L_REG (code->dst.reg);
1044 ea = -code->src.literal;
1046 SET_L_REG (code->dst.reg, res);
1047 goto just_flags_inc32;
1051 rd = GET_B_REG (code->src.reg);
1054 SET_B_REG (code->src.reg, res);
1055 goto just_flags_inc8;
1058 rd = GET_W_REG (code->dst.reg);
1059 ea = code->src.literal;
1061 SET_W_REG (code->dst.reg, res);
1062 goto just_flags_inc16;
1065 rd = GET_L_REG (code->dst.reg);
1066 ea = code->src.literal;
1068 SET_L_REG (code->dst.reg, res);
1069 goto just_flags_inc32;
1072 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1074 case O (O_ANDC, SB):
1076 ea = code->src.literal;
1082 ea = code->src.literal;
1086 case O (O_XORC, SB):
1088 ea = code->src.literal;
1129 if (((Z || (N ^ V)) == 0))
1135 if (((Z || (N ^ V)) == 1))
1169 case O (O_SYSCALL, SB):
1170 printf ("%c", cpu.regs[2]);
1173 OSHIFTS (O_NOT, rd = ~rd);
1174 OSHIFTS (O_SHLL, c = rd & hm;
1176 OSHIFTS (O_SHLR, c = rd & 1;
1177 rd = (unsigned int) rd >> 1);
1178 OSHIFTS (O_SHAL, c = rd & hm;
1180 OSHIFTS (O_SHAR, t = rd & hm;
1185 OSHIFTS (O_ROTL, c = rd & hm;
1188 OSHIFTS (O_ROTR, c = rd & 1;
1189 rd = (unsigned int) rd >> 1;
1191 OSHIFTS (O_ROTXL, t = rd & hm;
1196 OSHIFTS (O_ROTXR, t = rd & 1;
1197 rd = (unsigned int) rd >> 1;
1198 if (C) rd |= hm; c = t;);
1202 pc = fetch (&code->src);
1210 pc = fetch (&code->src);
1217 SET_MEMORY_L (tmp, code->next_pc);
1222 SET_MEMORY_W (tmp, code->next_pc);
1229 pc = code->src.literal;
1240 pc = GET_MEMORY_L (tmp);
1245 pc = GET_MEMORY_W (tmp);
1254 cpu.exception = SIGILL;
1256 case O (O_SLEEP, SB):
1257 if ((short) cpu.regs[0] == -255)
1258 cpu.exception = SIGILL;
1260 cpu.exception = SIGTRAP;
1263 cpu.exception = SIGTRAP;
1266 OBITOP (O_BNOT, 1, 1, ea ^= m);
1267 OBITOP (O_BTST, 1, 0, nz = ea & m);
1268 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1269 OBITOP (O_BSET, 1, 1, ea |= m);
1270 OBITOP (O_BLD, 1, 0, c = ea & m);
1271 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1272 OBITOP (O_BST, 1, 1, ea &= ~m;
1274 OBITOP (O_BIST, 1, 1, ea &= ~m;
1276 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1277 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1278 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1279 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1280 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1281 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1284 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1286 case O (O_MULS, SB):
1289 case O (O_MULS, SW):
1292 case O (O_MULU, SB):
1295 case O (O_MULU, SW):
1300 case O (O_DIVU, SB):
1302 rd = GET_W_REG (code->dst.reg);
1303 ea = GET_B_REG (code->src.reg);
1309 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1315 case O (O_DIVU, SW):
1317 rd = GET_L_REG (code->dst.reg);
1318 ea = GET_W_REG (code->src.reg);
1326 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1330 case O (O_DIVS, SB):
1333 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1334 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1337 tmp = (int) rd % (int) ea;
1338 rd = (int) rd / (int) ea;
1344 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1347 case O (O_DIVS, SW):
1349 rd = GET_L_REG (code->dst.reg);
1350 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1353 tmp = (int) rd % (int) ea;
1354 rd = (int) rd / (int) ea;
1355 n = rd & 0x80000000;
1360 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1363 case O (O_EXTS, SW):
1364 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1365 ea = rd & 0x80 ? -256 : 0;
1368 case O (O_EXTS, SL):
1369 rd = GET_W_REG (code->src.reg) & 0xffff;
1370 ea = rd & 0x8000 ? -65536 : 0;
1373 case O (O_EXTU, SW):
1374 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1378 case O (O_EXTU, SL):
1379 rd = GET_W_REG (code->src.reg) & 0xffff;
1388 cpu.exception = SIGILL;
1400 /* When a branch works */
1401 pc = code->src.literal;
1404 /* Set the cond codes from res */
1407 /* Set the flags after an 8 bit inc/dec operation */
1411 v = (rd & 0x7f) == 0x7f;
1415 /* Set the flags after an 16 bit inc/dec operation */
1419 v = (rd & 0x7fff) == 0x7fff;
1423 /* Set the flags after an 32 bit inc/dec operation */
1425 n = res & 0x80000000;
1426 nz = res & 0xffffffff;
1427 v = (rd & 0x7fffffff) == 0x7fffffff;
1432 /* Set flags after an 8 bit shift op, carry set in insn */
1436 SET_B_REG (code->src.reg, rd);
1441 /* Set flags after an 16 bit shift op, carry set in insn */
1446 SET_W_REG (code->src.reg, rd);
1450 /* Set flags after an 32 bit shift op, carry set in insn */
1451 n = (rd & 0x80000000);
1453 nz = rd & 0xffffffff;
1454 SET_L_REG (code->src.reg, rd);
1458 store (&code->dst, res);
1460 /* flags after a 32bit logical operation */
1461 n = res & 0x80000000;
1462 nz = res & 0xffffffff;
1467 store (&code->dst, res);
1469 /* flags after a 16bit logical operation */
1477 store (&code->dst, res);
1485 SET_B_REG (code->dst.reg, res);
1489 v = ((ea & 0x80) == (rd & 0x80)) && ((ea & 0x80) != (res & 0x80));
1494 SET_W_REG (code->dst.reg, res);
1498 v = ((ea & 0x8000) == (rd & 0x8000)) && ((ea & 0x8000) != (res & 0x8000));
1499 c = (res & 0x10000);
1503 SET_L_REG (code->dst.reg, res);
1505 n = res & 0x80000000;
1506 nz = res & 0xffffffff;
1507 v = ((ea & 0x80000000) == (rd & 0x80000000))
1508 && ((ea & 0x80000000) != (res & 0x80000000));
1509 switch (code->opcode / 4)
1512 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1516 c = (unsigned) rd < (unsigned) -ea;
1529 /* if (cpu.regs[8] ) abort(); */
1532 /* Poll after every 100th insn, */
1533 if (poll_count++ > 100)
1536 if (win32pollquit())
1542 #if defined(__GO32__)
1543 /* Poll after every 100th insn, */
1544 if (poll_count++ > 100)
1556 while (!cpu.exception);
1557 cpu.ticks += get_now () - tick_start;
1558 cpu.cycles += cycles;
1564 signal (SIGINT, prev);
1569 sim_write (addr, buffer, size)
1571 unsigned char *buffer;
1577 if (addr < 0 || addr + size > memory_size)
1579 for (i = 0; i < size; i++)
1581 cpu.memory[addr + i] = buffer[i];
1582 cpu.cache_idx[addr + i] = 0;
1588 sim_read (addr, buffer, size)
1590 unsigned char *buffer;
1594 if (addr < 0 || addr + size > memory_size)
1596 memcpy (buffer, cpu.memory + addr, size);
1610 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1611 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1614 #define CCR_REGNUM 8 /* Contains processor status */
1615 #define PC_REGNUM 9 /* Contains program counter */
1617 #define CYCLE_REGNUM 10
1618 #define INST_REGNUM 11
1619 #define TICK_REGNUM 12
1623 sim_store_register (rn, value)
1625 unsigned char *value;
1630 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1631 shortval = (value[0] << 8) | (value[1]);
1632 intval = h8300hmode ? longval : shortval;
1650 cpu.regs[rn] = intval;
1656 cpu.cycles = longval;
1660 cpu.insts = longval;
1664 cpu.ticks = longval;
1670 sim_fetch_register (rn, buf)
1712 if (h8300hmode || longreg)
1727 sim_stop_reason (reason, sigrc)
1728 enum sim_stop *reason;
1731 *reason = sim_stopped;
1732 *sigrc = cpu.exception;
1741 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1742 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1751 double timetaken = (double) cpu.ticks / (double) now_persec ();
1752 double virttime = cpu.cycles / 10.0e6;
1754 printf_filtered ("\n\n#instructions executed %10d\n", cpu.insts);
1755 printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles);
1756 printf_filtered ("#real time taken %10.4f\n", timetaken);
1757 printf_filtered ("#virtual time taked %10.4f\n", virttime);
1758 if (timetaken != 0.0)
1759 printf_filtered ("#simulation ratio %10.4f\n", virttime / timetaken);
1760 printf_filtered ("#compiles %10d\n", cpu.compiles);
1761 printf_filtered ("#cache size %10d\n", cpu.csize);
1767 for (i = 0; i < O_LAST; i++)
1770 printf_filtered ("%d: %d\n", i, cpu.stats[i]);
1776 /* Indicate whether the cpu is an h8/300 or h8/300h.
1777 FLAG is non-zero for the h8/300h. */
1800 sim_close (quitting)
1806 /* Called by gdb to load a program into memory. */
1809 sim_load (prog, from_tty)
1815 /* See if the file is for the h8/300 or h8/300h. */
1816 /* ??? This may not be the most efficient way. The z8k simulator
1817 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
1818 if ((abfd = bfd_openr (prog, "coff-h8300")) != 0)
1820 if (bfd_check_format (abfd, bfd_object))
1821 set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h);
1825 /* Return non-zero so gdb will handle it. */
1830 sim_create_inferior (start_address, argv, env)
1831 SIM_ADDR start_address;
1835 cpu.pc = start_address;
1839 sim_do_command (cmd)
1842 printf_filtered ("This simulator does not accept any commands.\n");
1848 sim_set_callbacks (ptr)
1849 struct host_callback_struct *ptr;