2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
35 #include "gdb/callback.h"
36 #include "gdb/remote-sim.h"
37 #include "gdb/sim-h8300.h"
45 host_callback *sim_callback;
47 static SIM_OPEN_KIND sim_kind;
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
54 void sim_set_simcache_size PARAMS ((int));
56 #define X(op, size) op * 4 + size
58 #define SP (h8300hmode ? SL : SW)
72 #define h8_opcodes ops
74 #include "opcode/h8300.h"
78 /* The rate at which to call the host's poll_quit callback. */
80 #define POLL_QUIT_INTERVAL 0x80000
82 #define LOW_BYTE(x) ((x) & 0xff)
83 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
84 #define P(X,Y) ((X << 8) | Y)
87 cpu.ccr = ((I << 7) | (UI << 6) | (H << 5) | (U << 4) \
88 | (N << 3) | (Z << 2) | (V << 1) | C);
91 if (h8300smode) cpu.exr = (trace<<7) | intMask;
94 c = (cpu.ccr >> 0) & 1;\
95 v = (cpu.ccr >> 1) & 1;\
96 nz = !((cpu.ccr >> 2) & 1);\
97 n = (cpu.ccr >> 3) & 1;\
98 u = (cpu.ccr >> 4) & 1;\
99 h = (cpu.ccr >> 5) & 1;\
100 ui = ((cpu.ccr >> 6) & 1);\
101 intMaskBit = (cpu.ccr >> 7) & 1;
106 trace = (cpu.exr >> 7) & 1; \
107 intMask = cpu.exr & 7; \
110 #ifdef __CHAR_IS_SIGNED__
111 #define SEXTCHAR(x) ((char) (x))
115 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
118 #define UEXTCHAR(x) ((x) & 0xff)
119 #define UEXTSHORT(x) ((x) & 0xffff)
120 #define SEXTSHORT(x) ((short) (x))
122 static cpu_state_type cpu;
127 static int memory_size;
132 return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */
153 return h8300hmode ? SL : SW;
165 return X (OP_IMM, SP);
167 return X (OP_REG, SP);
170 return X (OP_MEM, SP);
173 abort (); /* ?? May be something more usefull? */
178 decode (addr, data, dst)
196 /* Find the exact opcode/arg combo. */
197 for (q = h8_opcodes; q->name; q++)
199 op_type *nib = q->data.nib;
200 unsigned int len = 0;
204 op_type looking_for = *nib;
205 int thisnib = data[len >> 1];
207 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
209 if (looking_for < 16 && looking_for >= 0)
211 if (looking_for != thisnib)
216 if ((int) looking_for & (int) B31)
218 if (!(((int) thisnib & 0x8) != 0))
221 looking_for = (op_type) ((int) looking_for & ~(int) B31);
225 if ((int) looking_for & (int) B30)
227 if (!(((int) thisnib & 0x8) == 0))
230 looking_for = (op_type) ((int) looking_for & ~(int) B30);
233 if (looking_for & DBIT)
235 /* Exclude adds/subs by looking at bit 0 and 2, and
236 make sure the operand size, either w or l,
237 matches by looking at bit 1. */
238 if ((looking_for & 7) != (thisnib & 7))
241 abs = (thisnib & 0x8) ? 2 : 1;
243 else if (looking_for & (REG | IND | INC | DEC))
245 if (looking_for & REG)
247 /* Can work out size from the register. */
248 size = bitfrom (looking_for);
250 if (looking_for & SRC)
255 else if (looking_for & L_16)
257 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
259 if (looking_for & (PCREL | DISP))
264 else if (looking_for & ABSJMP)
266 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
268 else if (looking_for & MEMIND)
272 else if (looking_for & L_32)
276 abs = (data[i] << 24)
277 | (data[i + 1] << 16)
283 else if (looking_for & L_24)
287 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
290 else if (looking_for & IGNORE)
294 else if (looking_for & DISPREG)
296 rdisp = thisnib & 0x7;
298 else if (looking_for & KBIT)
315 else if (looking_for & L_8)
319 if (looking_for & PCREL)
321 abs = SEXTCHAR (data[len >> 1]);
323 else if (looking_for & ABS8MEM)
326 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
327 abs |= data[len >> 1] & 0xff;
331 abs = data[len >> 1] & 0xff;
334 else if (looking_for & L_3)
340 else if (looking_for == E)
344 /* Fill in the args. */
346 op_type *args = q->args.nib;
352 int rn = (x & DST) ? rd : rs;
362 p->type = X (OP_IMM, size);
365 else if (x & (IMM | KBIT | DBIT))
367 p->type = X (OP_IMM, size);
373 Some ops (like mul) have two sizes. */
376 p->type = X (OP_REG, size);
381 p->type = X (OP_INC, size);
386 p->type = X (OP_DEC, size);
391 p->type = X (OP_DISP, size);
395 else if (x & (ABS | ABSJMP | ABS8MEM))
397 p->type = X (OP_DISP, size);
403 p->type = X (OP_MEM, size);
408 p->type = X (OP_PCREL, size);
409 p->literal = abs + addr + 2;
415 p->type = X (OP_IMM, SP);
420 p->type = X (OP_DISP, size);
422 p->reg = rdisp & 0x7;
433 printf ("Hmmmm %x", x);
439 /* But a jmp or a jsr gets automagically lvalued,
440 since we branch to their address not their
442 if (q->how == O (O_JSR, SB)
443 || q->how == O (O_JMP, SB))
445 dst->src.type = lvalue (dst->src.type, dst->src.reg);
448 if (dst->dst.type == -1)
451 dst->opcode = q->how;
452 dst->cycles = q->time;
454 /* And a jsr to 0xc4 is turned into a magic trap. */
456 if (dst->opcode == O (O_JSR, SB))
458 if (dst->src.literal == 0xc4)
460 dst->opcode = O (O_SYSCALL, SB);
464 dst->next_pc = addr + len / 2;
468 printf ("Don't understand %x \n", looking_for);
479 /* Fell off the end. */
480 dst->opcode = O (O_ILL, SB);
488 /* Find the next cache entry to use. */
489 idx = cpu.cache_top + 1;
491 if (idx >= cpu.csize)
497 /* Throw away its old meaning. */
498 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
500 /* Set to new address. */
501 cpu.cache[idx].oldpc = pc;
503 /* Fill in instruction info. */
504 decode (pc, cpu.memory + pc, cpu.cache + idx);
506 /* Point to new cache entry. */
507 cpu.cache_idx[pc] = idx;
511 static unsigned char *breg[18];
512 static unsigned short *wreg[18];
513 static unsigned int *lreg[18];
515 #define GET_B_REG(x) *(breg[x])
516 #define SET_B_REG(x,y) (*(breg[x])) = (y)
517 #define GET_W_REG(x) *(wreg[x])
518 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
520 #define GET_L_REG(x) *(lreg[x])
521 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
523 #define GET_MEMORY_L(x) \
525 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
526 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
527 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
528 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
530 #define GET_MEMORY_W(x) \
532 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
533 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
536 #define GET_MEMORY_B(x) \
537 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
539 #define SET_MEMORY_L(x,y) \
540 { register unsigned char *_p; register int __y = y; \
541 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
542 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
543 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
545 #define SET_MEMORY_W(x,y) \
546 { register unsigned char *_p; register int __y = y; \
547 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
548 _p[0] = (__y)>>8; _p[1] =(__y);}
550 #define SET_MEMORY_B(x,y) \
551 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
558 int abs = arg->literal;
565 return GET_B_REG (rn);
567 return GET_W_REG (rn);
569 return GET_L_REG (rn);
580 r = GET_MEMORY_B (t);
589 r = GET_MEMORY_W (t);
597 r = GET_MEMORY_L (t);
604 case X (OP_DISP, SB):
605 t = GET_L_REG (rn) + abs;
607 return GET_MEMORY_B (t);
609 case X (OP_DISP, SW):
610 t = GET_L_REG (rn) + abs;
612 return GET_MEMORY_W (t);
614 case X (OP_DISP, SL):
615 t = GET_L_REG (rn) + abs;
617 return GET_MEMORY_L (t);
620 t = GET_MEMORY_L (abs);
625 t = GET_MEMORY_W (abs);
630 abort (); /* ?? May be something more usefull? */
642 int abs = arg->literal;
658 t = GET_L_REG (rn) - 1;
665 t = (GET_L_REG (rn) - 2) & cpu.mask;
671 t = (GET_L_REG (rn) - 4) & cpu.mask;
676 case X (OP_DISP, SB):
677 t = GET_L_REG (rn) + abs;
682 case X (OP_DISP, SW):
683 t = GET_L_REG (rn) + abs;
688 case X (OP_DISP, SL):
689 t = GET_L_REG (rn) + abs;
725 memory_size = H8300S_MSIZE;
727 memory_size = H8300H_MSIZE;
729 memory_size = H8300_MSIZE;
730 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
731 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
732 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
734 /* `msize' must be a power of two. */
735 if ((memory_size & (memory_size - 1)) != 0)
737 cpu.mask = memory_size - 1;
739 for (i = 0; i < 9; i++)
744 for (i = 0; i < 8; i++)
746 unsigned char *p = (unsigned char *) (cpu.regs + i);
747 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
748 unsigned short *q = (unsigned short *) (cpu.regs + i);
749 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
750 cpu.regs[i] = 0x00112233;
776 lreg[i] = &cpu.regs[i];
779 lreg[8] = &cpu.regs[8];
781 /* Initialize the seg registers. */
783 sim_set_simcache_size (CSIZE);
788 control_c (sig, code, scp, addr)
794 cpu.state = SIM_STATE_STOPPED;
795 cpu.exception = SIGINT;
805 #define I (intMaskBit != 0)
808 mop (code, bsize, sign)
821 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
822 SEXTSHORT (GET_W_REG (code->dst.reg));
824 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
825 SEXTSHORT (GET_W_REG (code->src.reg));
829 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
830 UEXTSHORT (GET_W_REG (code->dst.reg));
832 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
833 UEXTSHORT (GET_W_REG (code->src.reg));
836 result = multiplier * multiplicand;
840 n = result & (bsize ? 0x8000 : 0x80000000);
841 nz = result & (bsize ? 0xffff : 0xffffffff);
845 SET_W_REG (code->dst.reg, result);
849 SET_L_REG (code->dst.reg, result);
852 return ((n == 1) << 1) | (nz == 1);
856 #define ONOT(name, how) \
861 rd = GET_B_REG (code->src.reg); \
869 rd = GET_W_REG (code->src.reg); \
876 int hm = 0x80000000; \
877 rd = GET_L_REG (code->src.reg); \
882 #define OSHIFTS(name, how1, how2) \
887 rd = GET_B_REG (code->src.reg); \
888 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
902 rd = GET_W_REG (code->src.reg); \
903 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
916 int hm = 0x80000000; \
917 rd = GET_L_REG (code->src.reg); \
918 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
929 #define OBITOP(name,f, s, op) \
934 if (f) ea = fetch (&code->dst); \
935 m=1<< fetch (&code->src); \
937 if (s) store (&code->dst,ea); goto next; \
944 cpu.state = SIM_STATE_STOPPED;
945 cpu.exception = SIGINT;
958 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
959 #define FP_REGNUM R6_REGNUM /* Contains address of executing
962 #define CCR_REGNUM 8 /* Contains processor status */
963 #define PC_REGNUM 9 /* Contains program counter */
965 #define CYCLE_REGNUM 10
967 #define EXR_REGNUM 11
968 #define INST_REGNUM 12
969 #define TICK_REGNUM 13
972 sim_resume (sd, step, siggnal)
978 int tick_start = get_now ();
987 int c, nz, v, n, u, h, ui, intMaskBit;
992 prev = signal (SIGINT, control_c);
996 cpu.state = SIM_STATE_STOPPED;
997 cpu.exception = SIGTRAP;
1001 cpu.state = SIM_STATE_RUNNING;
1007 /* The PC should never be odd. */
1023 cidx = cpu.cache_idx[pc];
1024 code = cpu.cache + cidx;
1027 #define ALUOP(STORE, NAME, HOW) \
1028 case O (NAME, SB): HOW; if (STORE) goto alu8; else goto just_flags_alu8; \
1029 case O (NAME, SW): HOW; if (STORE) goto alu16; else goto just_flags_alu16; \
1030 case O (NAME, SL): HOW; if (STORE) goto alu32; else goto just_flags_alu32;
1033 #define LOGOP(NAME, HOW) \
1034 case O (NAME, SB): HOW; goto log8; \
1035 case O (NAME, SW): HOW; goto log16; \
1036 case O (NAME, SL): HOW; goto log32;
1043 printf ("%x %d %s\n", pc, code->opcode,
1044 code->op ? code->op->name : "**");
1046 cpu.stats[code->opcode]++;
1052 cycles += code->cycles;
1056 switch (code->opcode)
1060 * This opcode is a fake for when we get to an
1061 * instruction which hasnt been compiled
1068 case O (O_SUBX, SB):
1069 rd = fetch (&code->dst);
1070 ea = fetch (&code->src);
1075 case O (O_ADDX, SB):
1076 rd = fetch (&code->dst);
1077 ea = fetch (&code->src);
1082 #define EA ea = fetch (&code->src);
1083 #define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst);
1085 ALUOP (1, O_SUB, RD_EA;
1088 ALUOP (1, O_NEG, EA;
1094 rd = GET_B_REG (code->dst.reg);
1095 ea = fetch (&code->src);
1099 rd = GET_W_REG (code->dst.reg);
1100 ea = fetch (&code->src);
1104 rd = GET_L_REG (code->dst.reg);
1105 ea = fetch (&code->src);
1110 LOGOP (O_AND, RD_EA;
1116 LOGOP (O_XOR, RD_EA;
1120 case O (O_MOV_TO_MEM, SB):
1121 res = GET_B_REG (code->src.reg);
1123 case O (O_MOV_TO_MEM, SW):
1124 res = GET_W_REG (code->src.reg);
1126 case O (O_MOV_TO_MEM, SL):
1127 res = GET_L_REG (code->src.reg);
1131 case O (O_MOV_TO_REG, SB):
1132 res = fetch (&code->src);
1133 SET_B_REG (code->dst.reg, res);
1134 goto just_flags_log8;
1135 case O (O_MOV_TO_REG, SW):
1136 res = fetch (&code->src);
1137 SET_W_REG (code->dst.reg, res);
1138 goto just_flags_log16;
1139 case O (O_MOV_TO_REG, SL):
1140 res = fetch (&code->src);
1141 SET_L_REG (code->dst.reg, res);
1142 goto just_flags_log32;
1144 case O (O_EEPMOV, SB):
1145 case O (O_EEPMOV, SW):
1146 if (h8300hmode || h8300smode)
1148 register unsigned char *_src, *_dst;
1149 unsigned int count = ((code->opcode == O (O_EEPMOV, SW))
1150 ? cpu.regs[R4_REGNUM] & 0xffff
1151 : cpu.regs[R4_REGNUM] & 0xff);
1153 _src = (cpu.regs[R5_REGNUM] < memory_size
1154 ? cpu.memory + cpu.regs[R5_REGNUM]
1155 : cpu.eightbit + (cpu.regs[R5_REGNUM] & 0xff));
1156 if ((_src + count) >= (cpu.memory + memory_size))
1158 if ((_src + count) >= (cpu.eightbit + 0x100))
1161 _dst = (cpu.regs[R6_REGNUM] < memory_size
1162 ? cpu.memory + cpu.regs[R6_REGNUM]
1163 : cpu.eightbit + (cpu.regs[R6_REGNUM] & 0xff));
1164 if ((_dst + count) >= (cpu.memory + memory_size))
1166 if ((_dst + count) >= (cpu.eightbit + 0x100))
1169 memcpy (_dst, _src, count);
1171 cpu.regs[R5_REGNUM] += count;
1172 cpu.regs[R6_REGNUM] += count;
1173 cpu.regs[R4_REGNUM] &= ((code->opcode == O (O_EEPMOV, SW))
1174 ? (~0xffff) : (~0xff));
1175 cycles += 2 * count;
1180 case O (O_ADDS, SL):
1181 SET_L_REG (code->dst.reg,
1182 GET_L_REG (code->dst.reg)
1183 + code->src.literal);
1187 case O (O_SUBS, SL):
1188 SET_L_REG (code->dst.reg,
1189 GET_L_REG (code->dst.reg)
1190 - code->src.literal);
1194 rd = fetch (&code->dst);
1195 ea = fetch (&code->src);
1198 goto just_flags_alu8;
1201 rd = fetch (&code->dst);
1202 ea = fetch (&code->src);
1205 goto just_flags_alu16;
1208 rd = fetch (&code->dst);
1209 ea = fetch (&code->src);
1212 goto just_flags_alu32;
1216 rd = GET_B_REG (code->src.reg);
1219 SET_B_REG (code->src.reg, res);
1220 goto just_flags_inc8;
1223 rd = GET_W_REG (code->dst.reg);
1224 ea = -code->src.literal;
1226 SET_W_REG (code->dst.reg, res);
1227 goto just_flags_inc16;
1230 rd = GET_L_REG (code->dst.reg);
1231 ea = -code->src.literal;
1233 SET_L_REG (code->dst.reg, res);
1234 goto just_flags_inc32;
1238 rd = GET_B_REG (code->src.reg);
1241 SET_B_REG (code->src.reg, res);
1242 goto just_flags_inc8;
1245 rd = GET_W_REG (code->dst.reg);
1246 ea = code->src.literal;
1248 SET_W_REG (code->dst.reg, res);
1249 goto just_flags_inc16;
1252 rd = GET_L_REG (code->dst.reg);
1253 ea = code->src.literal;
1255 SET_L_REG (code->dst.reg, res);
1256 goto just_flags_inc32;
1258 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1259 #define GET_EXR(x) BUILDEXR ();x = cpu.exr
1263 res = fetch (&code->src);
1267 if (code->src.type == OP_CCR)
1271 else if (code->src.type == OP_EXR && h8300smode)
1277 store (&code->dst, res);
1280 case O (O_ANDC, SB):
1281 if (code->dst.type == OP_CCR)
1285 else if (code->dst.type == OP_EXR && h8300smode)
1291 ea = code->src.literal;
1296 if (code->dst.type == OP_CCR)
1300 else if (code->dst.type == OP_EXR && h8300smode)
1306 ea = code->src.literal;
1310 case O (O_XORC, SB):
1311 if (code->dst.type == OP_CCR)
1315 else if (code->dst.type == OP_EXR && h8300smode)
1321 ea = code->src.literal;
1362 if (((Z || (N ^ V)) == 0))
1368 if (((Z || (N ^ V)) == 1))
1402 case O (O_SYSCALL, SB):
1404 char c = cpu.regs[2];
1405 sim_callback->write_stdout (sim_callback, &c, 1);
1409 ONOT (O_NOT, rd = ~rd; v = 0;);
1411 c = rd & hm; v = 0; rd <<= 1,
1412 c = rd & (hm >> 1); v = 0; rd <<= 2);
1414 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1415 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1417 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1418 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1420 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1421 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1);
1423 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1424 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1426 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1427 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1429 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1430 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1432 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1433 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1437 pc = fetch (&code->src);
1445 pc = fetch (&code->src);
1452 SET_MEMORY_L (tmp, code->next_pc);
1457 SET_MEMORY_W (tmp, code->next_pc);
1464 pc = code->src.literal;
1475 pc = GET_MEMORY_L (tmp);
1480 pc = GET_MEMORY_W (tmp);
1489 cpu.state = SIM_STATE_STOPPED;
1490 cpu.exception = SIGILL;
1492 case O (O_SLEEP, SN):
1493 /* FIXME: Doesn't this break for breakpoints when r0
1494 contains just the right (er, wrong) value? */
1495 cpu.state = SIM_STATE_STOPPED;
1496 /* The format of r0 is defined by target newlib. Expand
1497 the macros here instead of looking for .../sys/wait.h. */
1498 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1499 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1500 if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0]))
1501 cpu.exception = SIGILL;
1503 cpu.exception = SIGTRAP;
1506 cpu.state = SIM_STATE_STOPPED;
1507 cpu.exception = SIGTRAP;
1510 OBITOP (O_BNOT, 1, 1, ea ^= m);
1511 OBITOP (O_BTST, 1, 0, nz = ea & m);
1512 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1513 OBITOP (O_BSET, 1, 1, ea |= m);
1514 OBITOP (O_BLD, 1, 0, c = ea & m);
1515 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1516 OBITOP (O_BST, 1, 1, ea &= ~m;
1518 OBITOP (O_BIST, 1, 1, ea &= ~m;
1520 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1521 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1522 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1523 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1524 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1525 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1527 #define MOP(bsize, signed) \
1528 mop (code, bsize, signed); \
1531 case O (O_MULS, SB):
1534 case O (O_MULS, SW):
1537 case O (O_MULU, SB):
1540 case O (O_MULU, SW):
1545 if (!h8300smode || code->src.type != X (OP_REG, SL))
1547 switch (code->src.reg)
1557 res = fetch (&code->src);
1558 store (&code->src, res | 0x80);
1559 goto just_flags_log8;
1561 case O (O_DIVU, SB):
1563 rd = GET_W_REG (code->dst.reg);
1564 ea = GET_B_REG (code->src.reg);
1567 tmp = (unsigned) rd % ea;
1568 rd = (unsigned) rd / ea;
1570 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1576 case O (O_DIVU, SW):
1578 rd = GET_L_REG (code->dst.reg);
1579 ea = GET_W_REG (code->src.reg);
1584 tmp = (unsigned) rd % ea;
1585 rd = (unsigned) rd / ea;
1587 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1591 case O (O_DIVS, SB):
1594 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1595 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1598 tmp = (int) rd % (int) ea;
1599 rd = (int) rd / (int) ea;
1605 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1608 case O (O_DIVS, SW):
1610 rd = GET_L_REG (code->dst.reg);
1611 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1614 tmp = (int) rd % (int) ea;
1615 rd = (int) rd / (int) ea;
1616 n = rd & 0x80000000;
1621 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1624 case O (O_EXTS, SW):
1625 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1626 ea = rd & 0x80 ? -256 : 0;
1629 case O (O_EXTS, SL):
1630 rd = GET_W_REG (code->src.reg) & 0xffff;
1631 ea = rd & 0x8000 ? -65536 : 0;
1634 case O (O_EXTU, SW):
1635 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1639 case O (O_EXTU, SL):
1640 rd = GET_W_REG (code->src.reg) & 0xffff;
1650 int nregs, firstreg, i;
1652 nregs = GET_MEMORY_B (pc + 1);
1655 firstreg = GET_MEMORY_B (pc + 3);
1657 for (i = firstreg; i <= firstreg + nregs; i++)
1660 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1667 int nregs, firstreg, i;
1669 nregs = GET_MEMORY_B (pc + 1);
1672 firstreg = GET_MEMORY_B (pc + 3);
1674 for (i = firstreg; i >= firstreg - nregs; i--)
1676 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1684 cpu.state = SIM_STATE_STOPPED;
1685 cpu.exception = SIGILL;
1692 if (code->dst.type == OP_CCR)
1697 else if (code->dst.type == OP_EXR && h8300smode)
1708 /* When a branch works */
1709 pc = code->src.literal;
1712 /* Set the cond codes from res */
1715 /* Set the flags after an 8 bit inc/dec operation */
1719 v = (rd & 0x7f) == 0x7f;
1723 /* Set the flags after an 16 bit inc/dec operation */
1727 v = (rd & 0x7fff) == 0x7fff;
1731 /* Set the flags after an 32 bit inc/dec operation */
1733 n = res & 0x80000000;
1734 nz = res & 0xffffffff;
1735 v = (rd & 0x7fffffff) == 0x7fffffff;
1740 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1743 SET_B_REG (code->src.reg, rd);
1747 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1750 SET_W_REG (code->src.reg, rd);
1754 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1755 n = (rd & 0x80000000);
1756 nz = rd & 0xffffffff;
1757 SET_L_REG (code->src.reg, rd);
1761 store (&code->dst, res);
1763 /* flags after a 32bit logical operation */
1764 n = res & 0x80000000;
1765 nz = res & 0xffffffff;
1770 store (&code->dst, res);
1772 /* flags after a 16bit logical operation */
1780 store (&code->dst, res);
1788 SET_B_REG (code->dst.reg, res);
1793 switch (code->opcode / 4)
1796 v = ((rd & 0x80) == (ea & 0x80)
1797 && (rd & 0x80) != (res & 0x80));
1801 v = ((rd & 0x80) != (-ea & 0x80)
1802 && (rd & 0x80) != (res & 0x80));
1811 SET_W_REG (code->dst.reg, res);
1815 c = (res & 0x10000);
1816 switch (code->opcode / 4)
1819 v = ((rd & 0x8000) == (ea & 0x8000)
1820 && (rd & 0x8000) != (res & 0x8000));
1824 v = ((rd & 0x8000) != (-ea & 0x8000)
1825 && (rd & 0x8000) != (res & 0x8000));
1834 SET_L_REG (code->dst.reg, res);
1836 n = res & 0x80000000;
1837 nz = res & 0xffffffff;
1838 switch (code->opcode / 4)
1841 v = ((rd & 0x80000000) == (ea & 0x80000000)
1842 && (rd & 0x80000000) != (res & 0x80000000));
1843 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1847 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1848 && (rd & 0x80000000) != (res & 0x80000000));
1849 c = (unsigned) rd < (unsigned) -ea;
1852 v = (rd == 0x80000000);
1868 if (--poll_count < 0)
1870 poll_count = POLL_QUIT_INTERVAL;
1871 if ((*sim_callback->poll_quit) != NULL
1872 && (*sim_callback->poll_quit) (sim_callback))
1877 while (cpu.state == SIM_STATE_RUNNING);
1878 cpu.ticks += get_now () - tick_start;
1879 cpu.cycles += cycles;
1886 signal (SIGINT, prev);
1893 /* FIXME: Unfinished. */
1898 sim_write (sd, addr, buffer, size)
1901 unsigned char *buffer;
1909 for (i = 0; i < size; i++)
1911 if (addr < memory_size)
1913 cpu.memory[addr + i] = buffer[i];
1914 cpu.cache_idx[addr + i] = 0;
1917 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1923 sim_read (sd, addr, buffer, size)
1926 unsigned char *buffer;
1932 if (addr < memory_size)
1933 memcpy (buffer, cpu.memory + addr, size);
1935 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1941 sim_store_register (sd, rn, value, length)
1944 unsigned char *value;
1950 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1951 shortval = (value[0] << 8) | (value[1]);
1952 intval = h8300hmode ? longval : shortval;
1970 cpu.regs[rn] = intval;
1979 cpu.cycles = longval;
1983 cpu.insts = longval;
1987 cpu.ticks = longval;
1994 sim_fetch_register (sd, rn, buf, length)
2005 if (!h8300smode && rn >= EXR_REGNUM)
2043 if (h8300hmode || longreg)
2059 sim_stop_reason (sd, reason, sigrc)
2061 enum sim_stop *reason;
2064 #if 0 /* FIXME: This should work but we can't use it.
2065 grep for SLEEP above. */
2068 case SIM_STATE_EXITED : *reason = sim_exited; break;
2069 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
2070 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
2074 *reason = sim_stopped;
2076 *sigrc = cpu.exception;
2079 /* FIXME: Rename to sim_set_mem_size. */
2085 /* Memory size is fixed. */
2089 sim_set_simcache_size (n)
2095 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
2096 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
2102 sim_info (sd, verbose)
2106 double timetaken = (double) cpu.ticks / (double) now_persec ();
2107 double virttime = cpu.cycles / 10.0e6;
2109 (*sim_callback->printf_filtered) (sim_callback,
2110 "\n\n#instructions executed %10d\n",
2112 (*sim_callback->printf_filtered) (sim_callback,
2113 "#cycles (v approximate) %10d\n",
2115 (*sim_callback->printf_filtered) (sim_callback,
2116 "#real time taken %10.4f\n",
2118 (*sim_callback->printf_filtered) (sim_callback,
2119 "#virtual time taked %10.4f\n",
2121 if (timetaken != 0.0)
2122 (*sim_callback->printf_filtered) (sim_callback,
2123 "#simulation ratio %10.4f\n",
2124 virttime / timetaken);
2125 (*sim_callback->printf_filtered) (sim_callback,
2128 (*sim_callback->printf_filtered) (sim_callback,
2129 "#cache size %10d\n",
2133 /* This to be conditional on `what' (aka `verbose'),
2134 however it was never passed as non-zero. */
2138 for (i = 0; i < O_LAST; i++)
2141 (*sim_callback->printf_filtered) (sim_callback,
2142 "%d: %d\n", i, cpu.stats[i]);
2148 /* Indicate whether the cpu is an H8/300 or H8/300H.
2149 FLAG is non-zero for the H8/300H. */
2152 set_h8300h (h_flag, s_flag)
2155 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2156 This function being replaced by a sim_open:ARGV configuration
2158 h8300hmode = h_flag;
2159 h8300smode = s_flag;
2163 sim_open (kind, ptr, abfd, argv)
2165 struct host_callback_struct *ptr;
2169 /* FIXME: Much of the code in sim_load can be moved here. */
2174 /* Fudge our descriptor. */
2175 return (SIM_DESC) 1;
2179 sim_close (sd, quitting)
2183 /* Nothing to do. */
2186 /* Called by gdb to load a program into memory. */
2189 sim_load (sd, prog, abfd, from_tty)
2197 /* FIXME: The code below that sets a specific variant of the H8/300
2198 being simulated should be moved to sim_open(). */
2200 /* See if the file is for the H8/300 or H8/300H. */
2201 /* ??? This may not be the most efficient way. The z8k simulator
2202 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2206 prog_bfd = bfd_openr (prog, "coff-h8300");
2207 if (prog_bfd != NULL)
2209 /* Set the cpu type. We ignore failure from bfd_check_format
2210 and bfd_openr as sim_load_file checks too. */
2211 if (bfd_check_format (prog_bfd, bfd_object))
2213 unsigned long mach = bfd_get_mach (prog_bfd);
2214 set_h8300h (mach == bfd_mach_h8300h || mach == bfd_mach_h8300s,
2215 mach == bfd_mach_h8300s);
2219 /* If we're using gdb attached to the simulator, then we have to
2220 reallocate memory for the simulator.
2222 When gdb first starts, it calls fetch_registers (among other
2223 functions), which in turn calls init_pointers, which allocates
2226 The problem is when we do that, we don't know whether we're
2227 debugging an H8/300 or H8/300H program.
2229 This is the first point at which we can make that determination,
2230 so we just reallocate memory now; this will also allow us to handle
2231 switching between H8/300 and H8/300H programs without exiting
2235 memory_size = H8300S_MSIZE;
2236 else if (h8300hmode)
2237 memory_size = H8300H_MSIZE;
2239 memory_size = H8300_MSIZE;
2244 free (cpu.cache_idx);
2246 free (cpu.eightbit);
2248 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2249 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2250 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2252 /* `msize' must be a power of two. */
2253 if ((memory_size & (memory_size - 1)) != 0)
2255 cpu.mask = memory_size - 1;
2257 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2258 sim_kind == SIM_OPEN_DEBUG,
2262 /* Close the bfd if we opened it. */
2263 if (abfd == NULL && prog_bfd != NULL)
2264 bfd_close (prog_bfd);
2268 /* Close the bfd if we opened it. */
2269 if (abfd == NULL && prog_bfd != NULL)
2270 bfd_close (prog_bfd);
2275 sim_create_inferior (sd, abfd, argv, env)
2282 cpu.pc = bfd_get_start_address (abfd);
2289 sim_do_command (sd, cmd)
2293 (*sim_callback->printf_filtered) (sim_callback,
2294 "This simulator does not accept any commands.\n");
2298 sim_set_callbacks (ptr)
2299 struct host_callback_struct *ptr;