2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
23 #include <sys/times.h>
24 #include <sys/param.h>
30 #define X(op, size) op*4+size
32 #define SP (Hmode ? SL:SW)
45 #define h8_opcodes ops
47 #include "opcode/h8300.h"
51 #define LOW_BYTE(x) ((x) & 0xff)
52 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
53 #define P(X,Y) ((X<<8) | Y)
55 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
58 c = (cpu.ccr >> 0) & 1;\
59 v = (cpu.ccr >> 1) & 1;\
60 nz = !((cpu.ccr >> 2) & 1);\
61 n = (cpu.ccr >> 3) & 1;
63 #ifdef __CHAR_IS_SIGNED__
64 #define SEXTCHAR(x) ((char)(x))
68 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
71 #define UEXTCHAR(x) ((x) & 0xff)
72 #define UEXTSHORT(x) ((x) & 0xffff)
73 #define SEXTSHORT(x) ((short)(x))
75 static cpu_state_type cpu;
85 return b.tms_utime + b.tms_stime;
108 return Hmode ? SL : SW;
128 return X (OP_MEM, SP);
135 decode (addr, data, dst)
147 struct h8_opcode *q = h8_opcodes;
151 /* Find the exact opcode/arg combo */
155 unsigned int len = 0;
161 op_type looking_for = *nib;
162 int thisnib = data[len >> 1];
164 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
166 if (looking_for < 16)
169 if (looking_for != thisnib)
175 if ((int) looking_for & (int) B31)
177 if (!(((int) thisnib & 0x8) != 0))
179 looking_for = (op_type) ((int) looking_for & ~(int)
184 if ((int) looking_for & (int) B30)
186 if (!(((int) thisnib & 0x8) == 0))
188 looking_for = (op_type) ((int) looking_for & ~(int) B30);
190 if (looking_for & DBIT)
192 if ((looking_for & 5) != (thisnib &5)) goto fail;
193 abs = (thisnib & 0x8) ? 2 : 1;
195 else if (looking_for & (REG | IND | INC | DEC))
197 if (looking_for & REG)
200 * Can work out size from the
203 size = bitfrom (looking_for);
205 if (looking_for & SRC)
214 else if (looking_for & L_16)
216 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
218 if (looking_for & (PCREL|DISP))
223 else if (looking_for & ABSJMP)
230 else if (looking_for & L_32)
233 abs = (data[i] << 24)
234 | (data[i + 1] << 16)
241 else if (looking_for & L_24)
244 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i +
248 else if (looking_for & IGNORE)
252 else if (looking_for & DISPREG)
254 rdisp = thisnib & 0x7;
256 else if (looking_for & KBIT)
271 else if (looking_for & L_8)
275 if (looking_for & PCREL)
277 abs = SEXTCHAR (data[len >> 1]);
281 abs = data[len >> 1] & 0xff;
284 else if (looking_for & L_3)
290 else if (looking_for == E)
294 /* Fill in the args */
296 op_type *args = q->args.nib;
303 int rn = (x & DST) ? rd : rs;
316 if (x & (IMM | KBIT | DBIT))
318 p->type = X (OP_IMM, size);
325 ops (like mul) have two sizes */
328 p->type = X (OP_REG, size);
333 p->type = X (OP_INC, size);
338 p->type = X (OP_DEC, size);
343 p->type = X (OP_DISP, size);
347 else if (x & (ABS | ABSJMP | ABSMOV))
349 p->type = X (OP_DISP, size);
355 p->type = X (OP_MEM, size);
360 p->type = X (OP_PCREL, size);
361 p->literal = abs + addr + 2;
365 p->type = X (OP_IMM, SP);
370 p->type = X (OP_DISP, size);
372 p->reg = rdisp & 0x7;
379 printf ("Hmmmm %x", x);
387 * But a jmp or a jsr gets
388 * automagically lvalued, since we
389 * branch to their address not their
392 if (q->how == O (O_JSR, SB)
393 || q->how == O (O_JMP, SB))
395 dst->src.type = lvalue (dst->src.type, dst->src.reg);
399 if (dst->dst.type == -1)
402 dst->opcode = q->how;
403 dst->cycles = q->time;
405 /* And a jsr to 0xc4 is turned into a magic trap */
407 if (dst->opcode == O(O_JSR, SB))
409 if(dst->src.literal == 0xc4)
411 dst->opcode = O(O_SYSCALL,SB);
415 dst->next_pc = addr + len / 2;
420 printf ("Dont understand %x \n", looking_for);
432 dst->opcode = O (O_ILL, SB);
441 /* find the next cache entry to use */
443 idx = cpu.cache_top + 1;
445 if (idx >= cpu.csize)
451 /* Throw away its old meaning */
452 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
454 /* set to new address */
455 cpu.cache[idx].oldpc = pc;
457 /* fill in instruction info */
458 decode (pc, cpu.memory + pc, cpu.cache + idx);
460 /* point to new cache entry */
461 cpu.cache_idx[pc] = idx;
465 static unsigned char *breg[18];
466 static unsigned short *wreg[18];
467 static unsigned int *lreg[18];
469 #define GET_B_REG(x) *(breg[x])
470 #define SET_B_REG(x,y) (*(breg[x])) = (y)
471 #define GET_W_REG(x) *(wreg[x])
472 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
474 #define GET_L_REG(x) *(lreg[x])
475 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
477 #define GET_MEMORY_L(x) \
478 ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3])
480 #define GET_MEMORY_W(x) \
481 ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0))
484 #define SET_MEMORY_B(x,y) \
485 (cpu.memory[(x)] = y)
487 #define SET_MEMORY_W(x,y) \
488 {register unsigned char *_p = cpu.memory+x;\
489 register int __y = y;\
493 #define SET_MEMORY_L(x,y) \
494 {register unsigned char *_p = cpu.memory+x;register int __y = y;\
495 _p[0] = (__y)>>24; _p[1] = (__y)>>16; _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
497 #define GET_MEMORY_B(x) (cpu.memory[x])
504 int abs = arg->literal;
511 return GET_B_REG (rn);
513 return GET_W_REG (rn);
515 return GET_L_REG (rn);
550 case X (OP_DISP, SB):
551 t = GET_L_REG (rn) + abs;
553 return GET_MEMORY_B (t);
555 case X (OP_DISP, SW):
556 t = GET_L_REG (rn) + abs;
558 return GET_MEMORY_W (t);
560 case X (OP_DISP, SL):
561 t = GET_L_REG (rn) + abs;
563 return GET_MEMORY_L (t);
581 int abs = arg->literal;
597 t = GET_L_REG (rn) - 1;
604 t= (GET_L_REG (rn) - 2 ) & cpu.mask;
610 t = (GET_L_REG(rn) -4 ) & cpu.mask;
615 case X (OP_DISP, SB):
616 t = GET_L_REG (rn) + abs;
621 case X (OP_DISP, SW):
622 t = GET_L_REG (rn) + abs;
627 case X (OP_DISP, SL):
628 t = GET_L_REG (rn) + abs;
664 cpu.memory = (unsigned char *) calloc (sizeof (char), MSIZE);
665 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), MSIZE);
666 cpu.mask = (1<<MPOWER)-1;
668 for (i = 0; i < 9; i++)
673 for (i = 0; i < 8; i++)
675 unsigned char *p = (unsigned char *) (cpu.regs + i);
676 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
677 unsigned short *q = (unsigned short *) (cpu.regs + i);
678 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
679 cpu.regs[i] = 0x00112233;
705 lreg[i] = &cpu.regs[i];
709 lreg[8] = &cpu.regs[8];
711 /* initialize the seg registers */
719 control_c (sig, code, scp, addr)
725 cpu.exception = SIGINT;
739 int tick_start = get_now ();
752 prev = signal (SIGINT, control_c);
756 cpu.exception = SIGTRAP;
773 cidx = cpu.cache_idx[pc];
774 code = cpu.cache + cidx;
777 #define ALUOP(STORE, NAME, HOW) \
778 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
779 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
780 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
783 #define LOGOP(NAME, HOW) \
784 case O(NAME,SB): HOW; goto log8;\
785 case O(NAME, SW): HOW; goto log16;\
786 case O(NAME,SL): HOW; goto log32;
793 printf ("%x %d %s\n", pc, code->opcode,
794 code->op ? code->op->name : "**");
796 cpu.stats[code->opcode]++;
800 cycles += code->cycles;
802 switch (code->opcode)
806 * This opcode is a fake for when we get to an
807 * instruction which hasnt been compiled
815 rd = fetch (&code->dst);
816 ea = fetch (&code->src);
822 rd = fetch (&code->dst);
823 ea = fetch (&code->src);
828 #define RD rd = fetch(&code->src);
829 #define RD_EA rd = fetch(&code->dst); ea = fetch(&code->src);
831 ALUOP (1, O_SUB, RD_EA; ea = -ea ; res = rd + ea);
832 ALUOP (1, O_NEG, RD; ea = -ea ;rd = 0; res = rd + ea);
835 rd = GET_B_REG(code->dst.reg);
836 ea = fetch(&code->src);
840 rd = GET_W_REG(code->dst.reg);
841 ea = fetch(&code->src);
845 rd = GET_L_REG(code->dst.reg);
846 ea = fetch(&code->src);
851 LOGOP (O_AND, RD_EA; res = rd & ea);
853 LOGOP (O_OR, RD_EA; res = rd | ea);
855 LOGOP (O_XOR, RD_EA; res = rd ^ ea);
858 case O(O_MOV_TO_MEM,SB):
859 res = GET_B_REG(code->src.reg);
861 case O(O_MOV_TO_MEM,SW):
862 res = GET_W_REG(code->src.reg);
864 case O(O_MOV_TO_MEM,SL):
865 res = GET_L_REG(code->src.reg);
869 case O(O_MOV_TO_REG,SB):
870 res = fetch(&code->src);
871 SET_B_REG(code->dst.reg, res);
872 goto just_flags_log8;
873 case O(O_MOV_TO_REG,SW):
874 res = fetch(&code->src);
875 SET_W_REG(code->dst.reg, res);
876 goto just_flags_log16;
877 case O(O_MOV_TO_REG,SL):
878 res = fetch(&code->src);
879 SET_L_REG(code->dst.reg, res);
880 goto just_flags_log32;
884 SET_L_REG(code->dst.reg,
885 GET_L_REG(code->dst.reg)
886 + code->src.literal);
891 SET_L_REG(code->dst.reg,
892 GET_L_REG(code->dst.reg)
893 - code->src.literal);
897 rd = fetch (&code->dst);
898 ea = fetch (&code->src);
901 goto just_flags_alu8;
904 rd = fetch (&code->dst);
905 ea = fetch (&code->src);
908 goto just_flags_alu16;
911 rd = fetch (&code->dst);
912 ea = fetch (&code->src);
915 goto just_flags_alu32;
919 rd = GET_B_REG (code->src.reg);
922 SET_B_REG (code->src.reg, res);
923 goto just_flags_inc8;
926 rd = GET_W_REG (code->dst.reg);
927 ea = - code->src.literal;
929 SET_W_REG (code->dst.reg, res);
930 goto just_flags_inc16;
933 rd = GET_L_REG (code->dst.reg);
934 ea = -code->src.literal;
936 SET_L_REG (code->dst.reg, res);
937 goto just_flags_inc32;
941 rd = GET_B_REG (code->src.reg);
944 SET_B_REG (code->src.reg, res);
945 goto just_flags_inc8;
948 rd = GET_W_REG (code->dst.reg);
949 ea = code->src.literal;
951 SET_W_REG (code->dst.reg, res);
952 goto just_flags_inc16;
955 rd = GET_L_REG (code->dst.reg);
956 ea = code->src.literal;
958 SET_L_REG (code->dst.reg, res);
959 goto just_flags_inc32;
962 #define GET_CCR(x) BUILDSR();x = cpu.ccr
966 ea = code->src.literal;
1007 if (((Z || (N ^ V)) == 0))
1013 if (((Z || (N ^ V)) == 1))
1047 case O(O_SYSCALL, SB):
1048 printf("%c", cpu.regs[2]);
1053 #define OSHIFTS(name, how) \
1054 case O(name, SB):{ int t;int hm = 0x80; rd = GET_B_REG(code->src.reg);how; goto shift8;} \
1055 case O(name, SW):{ int t;int hm = 0x8000; rd = GET_W_REG(code->src.reg); how; goto shift16;} \
1056 case O(name, SL):{ int t;int hm = 0x80000000; rd = GET_L_REG(code->src.reg);how; goto shift32;}
1059 OSHIFTS(O_NOT, rd = ~rd);
1060 OSHIFTS(O_SHLL, c = rd & hm; rd<<=1);
1061 OSHIFTS(O_SHLR, c = rd & 1; rd>>=1);
1062 OSHIFTS(O_SHAL, c = rd & hm; rd<<=1);
1063 OSHIFTS(O_SHAR, t = rd & hm; c = rd&1;rd>>=1;rd|=t;);
1064 OSHIFTS(O_ROTL, c = rd & hm; rd <<=1; rd|= C);
1065 OSHIFTS(O_ROTR, c = rd &1 ; rd >>=1; if (c) rd|= hm;);
1066 OSHIFTS(O_ROTXL,t = rd & hm; rd<<=1; rd|=C; c=t;);
1067 OSHIFTS(O_ROTXR,t = rd & 1; rd>>=1; if (C) rd|=hm; c=t;);
1071 pc = fetch (&code->src);
1079 pc = fetch (&code->src);
1086 SET_MEMORY_L (tmp, code->next_pc);
1091 SET_MEMORY_W (tmp, code->next_pc);
1098 pc = code->src.literal;
1110 pc = GET_MEMORY_L (tmp);
1116 pc = GET_MEMORY_W (tmp);
1125 cpu.exception = SIGILL;
1129 cpu.exception = SIGTRAP;
1132 #define OBITOP(name,f, s, op) \
1133 case O(name, SB): {int m;int b; \
1134 if (f) ea = fetch(&code->dst);\
1135 m=1<<code->src.literal;\
1137 if(s) store(&code->dst,ea); goto next;\
1139 OBITOP(O_BNOT,1,1,ea ^= m);
1140 OBITOP(O_BTST,1,0,nz = ea & m);
1141 OBITOP(O_BLD,1,0, c = ea & m);
1142 OBITOP(O_BILD,1,0, c = !(ea & m));
1143 OBITOP(O_BST,1,1, ea &= ~m; if (C) ea |=m);
1144 OBITOP(O_BIST,1,1, ea &= ~m; if (!C) ea |=m);
1145 OBITOP(O_BAND,1,1, b = (ea & m) && C; ea &= ~m; if (b) ea |=m);
1146 OBITOP(O_BIAND,1,1, b = (ea & m) && C; ea &= ~m; if (!b) ea |=m);
1147 OBITOP(O_BOR,1,1, b = (ea & m) || C; ea &= ~m; if (b) ea |=m);
1148 OBITOP(O_BIOR,1,1, b = (ea & m) || C; ea &= ~m; if (!b) ea |=m);
1149 OBITOP(O_BXOR,1,1, b = (ea & m) != C; ea &= ~m; if (b) ea |=m);
1150 OBITOP(O_BIXOR,1,1, b = (ea & m) != C; ea &= ~m; if (!b) ea |=m);
1151 OBITOP(O_BCLR,1,1, ea &= ~m; );
1152 OBITOP(O_BSET,1,1, ea |= m; );
1155 #define MOP(bsize, signed) \
1164 bsize ? SEXTCHAR(GET_W_REG(code->dst.reg)): \
1165 SEXTSHORT(GET_W_REG(code->dst.reg)); \
1167 bsize ? SEXTCHAR(GET_B_REG(code->src.reg)): \
1168 SEXTSHORT(GET_B_REG(code->src.reg)); \
1172 multiplicand = bsize ? UEXTCHAR(GET_W_REG(code->dst.reg)): \
1173 UEXTSHORT(GET_W_REG(code->dst.reg)); \
1175 bsize ? UEXTCHAR(GET_B_REG(code->src.reg)): \
1176 UEXTSHORT(GET_B_REG(code->src.reg)); \
1179 result = multiplier * multiplicand; \
1183 n = result & (bsize ? 0x8000: 0x80000000); \
1184 nz = result & (bsize ? 0xffff: 0xffffffff); \
1188 SET_W_REG(code->dst.reg, result); \
1192 SET_L_REG(code->dst.reg, result); \
1197 case O(O_MULS, SB): MOP(1,1);break;
1198 case O(O_MULS, SW): MOP(0,1); break;
1199 case O(O_MULU, SB): MOP(1,0);break;
1200 case O(O_MULU, SW): MOP(0,0); break;
1206 rd = GET_W_REG(code->dst.reg);
1207 ea = GET_B_REG(code->src.reg);
1213 SET_W_REG(code->dst.reg, (rd & 0xff) | (tmp << 8));
1222 rd = GET_L_REG(code->dst.reg);
1223 ea = GET_W_REG(code->src.reg);
1231 SET_L_REG(code->dst.reg, (rd & 0xffff) | (tmp << 16));
1240 rd = SEXTSHORT(GET_W_REG(code->dst.reg));
1241 ea = SEXTCHAR(GET_B_REG(code->src.reg));
1244 tmp = (int)rd % (int)ea;
1245 rd = (int)rd / (int)ea;
1252 SET_W_REG(code->dst.reg, (rd & 0xff) | (tmp << 8));
1258 rd = GET_L_REG(code->dst.reg);
1259 ea = SEXTSHORT(GET_W_REG(code->src.reg));
1262 tmp = (int)rd % (int)ea;
1263 rd = (int)rd / (int)ea;
1264 n = rd & 0x80000000;
1269 SET_L_REG(code->dst.reg, (rd & 0xffff) | (tmp << 16));
1276 cpu.exception = 123;
1287 /* When a branch works */
1288 pc = code->src.literal;
1291 /* Set the cond codes from res */
1294 /* Set the flags after an 8 bit inc/dec operation */
1298 v = (rd & 0x7f) == 0x7f;
1302 /* Set the flags after an 16 bit inc/dec operation */
1306 v = (rd & 0x7fff) == 0x7fff;
1310 /* Set the flags after an 32 bit inc/dec operation */
1312 n = res & 0x80000000;
1313 nz = res & 0xffffffff;
1314 v = (rd & 0x7fffffff) == 0x7fffffff;
1319 /* Set flags after an 8 bit shift op, carry set in insn */
1323 SET_B_REG(code->src.reg, rd);
1328 /* Set flags after an 16 bit shift op, carry set in insn */
1333 SET_W_REG(code->src.reg, rd);
1338 /* Set flags after an 32 bit shift op, carry set in insn */
1339 n = (rd & 0x80000000);
1341 nz = rd & 0xffffffff;
1342 SET_L_REG(code->src.reg, rd);
1347 store (&code->dst, res);
1349 /* flags after a 32bit logical operation */
1350 n = res & 0x80000000;
1351 nz = res & 0xffffffff;
1356 store (&code->dst, res);
1358 /* flags after a 16bit logical operation */
1366 store (&code->dst, res);
1374 SET_B_REG (code->dst.reg, res);
1378 v = ((ea & 0x80) == (rd & 0x80)) && ((ea & 0x80) != (res & 0x80));
1383 SET_W_REG (code->dst.reg, res);
1387 v = ((ea & 0x8000) == (rd & 0x8000)) && ((ea & 0x8000) != (res & 0x8000));
1388 c = (res & 0x10000);
1392 SET_L_REG (code->dst.reg, res);
1394 n = res & 0x80000000;
1395 nz = res & 0xffffffff;
1396 v = ((ea & 0x80000000) == (rd & 0x80000000))
1397 && ((ea & 0x80000000) != (res & 0x80000000));
1398 c = (res < rd) || (res < ea);
1405 if (cpu.regs[8] ) abort();
1410 while (!cpu.exception);
1411 cpu.ticks += get_now () - tick_start;
1412 cpu.cycles += cycles;
1417 signal (SIGINT, prev);
1424 sim_write (addr, buffer, size)
1426 unsigned char *buffer;
1432 if (addr < 0 || addr + size > MSIZE)
1434 for (i = 0; i < size; i++)
1436 cpu.memory[addr + i] = buffer[i];
1437 cpu.cache_idx[addr + i] = 0;
1442 sim_read (addr, buffer, size)
1448 if (addr < 0 || addr + size > MSIZE)
1450 memcpy (buffer, cpu.memory + addr, size);
1464 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1465 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1468 #define CCR_REGNUM 8 /* Contains processor status */
1469 #define PC_REGNUM 9 /* Contains program counter */
1471 #define CYCLE_REGNUM 10
1472 #define INST_REGNUM 11
1473 #define TICK_REGNUM 12
1477 sim_store_register (rn, value)
1498 cpu.regs[rn] = value;
1518 sim_fetch_register (rn, buf)
1562 if (Hmode || longreg)
1584 return cpu.exception;
1589 sim_store_register (PC_REGNUM, n);
1599 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1600 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1611 double timetaken = (double) cpu.ticks / (double) now_persec ();
1612 double virttime = cpu.cycles / 10.0e6;
1615 printf ("\n\n#instructions executed %10d\n", cpu.insts);
1616 printf ("#cycles (v approximate) %10d\n", cpu.cycles);
1617 printf ("#real time taken %10.4f\n", timetaken);
1618 printf ("#virtual time taked %10.4f\n", virttime);
1619 if (timetaken != 0.0)
1620 printf ("#simulation ratio %10.4f\n", virttime / timetaken);
1621 printf ("#compiles %10d\n", cpu.compiles);
1622 printf ("#cache size %10d\n", cpu.csize);
1629 for (i= 0; i < O_LAST; i++)
1632 printf("%d: %d\n", i, cpu.stats[i]);