2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
37 #include "remote-sim.h"
45 host_callback *sim_callback;
47 static SIM_OPEN_KIND sim_kind;
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
54 void sim_set_simcache_size PARAMS ((int));
56 #define X(op, size) op*4+size
58 #define SP (h8300hmode ? SL:SW)
71 #define h8_opcodes ops
73 #include "opcode/h8300.h"
77 /* The rate at which to call the host's poll_quit callback. */
79 #define POLL_QUIT_INTERVAL 0x80000
81 #define LOW_BYTE(x) ((x) & 0xff)
82 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
83 #define P(X,Y) ((X<<8) | Y)
85 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
88 c = (cpu.ccr >> 0) & 1;\
89 v = (cpu.ccr >> 1) & 1;\
90 nz = !((cpu.ccr >> 2) & 1);\
91 n = (cpu.ccr >> 3) & 1;
93 #ifdef __CHAR_IS_SIGNED__
94 #define SEXTCHAR(x) ((char)(x))
98 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
101 #define UEXTCHAR(x) ((x) & 0xff)
102 #define UEXTSHORT(x) ((x) & 0xffff)
103 #define SEXTSHORT(x) ((short)(x))
105 static cpu_state_type cpu;
110 static int memory_size;
139 return h8300hmode ? SL : SW;
151 return X (OP_IMM, SP);
153 return X (OP_REG, SP);
156 return X (OP_MEM, SP);
164 decode (addr, data, dst)
176 struct h8_opcode *q = h8_opcodes;
182 /* Find the exact opcode/arg combo. */
186 unsigned int len = 0;
192 op_type looking_for = *nib;
193 int thisnib = data[len >> 1];
195 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
197 if (looking_for < 16 && looking_for >= 0)
199 if (looking_for != thisnib)
204 if ((int) looking_for & (int) B31)
206 if (!(((int) thisnib & 0x8) != 0))
209 looking_for = (op_type) ((int) looking_for & ~(int) B31);
213 if ((int) looking_for & (int) B30)
215 if (!(((int) thisnib & 0x8) == 0))
218 looking_for = (op_type) ((int) looking_for & ~(int) B30);
221 if (looking_for & DBIT)
223 if ((looking_for & 5) != (thisnib & 5))
226 abs = (thisnib & 0x8) ? 2 : 1;
228 else if (looking_for & (REG | IND | INC | DEC))
230 if (looking_for & REG)
232 /* Can work out size from the register. */
233 size = bitfrom (looking_for);
235 if (looking_for & SRC)
240 else if (looking_for & L_16)
242 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
244 if (looking_for & (PCREL | DISP))
249 else if (looking_for & ABSJMP)
251 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
253 else if (looking_for & MEMIND)
257 else if (looking_for & L_32)
261 abs = (data[i] << 24)
262 | (data[i + 1] << 16)
268 else if (looking_for & L_24)
272 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
275 else if (looking_for & IGNORE)
279 else if (looking_for & DISPREG)
281 rdisp = thisnib & 0x7;
283 else if (looking_for & KBIT)
298 else if (looking_for & L_8)
302 if (looking_for & PCREL)
304 abs = SEXTCHAR (data[len >> 1]);
306 else if (looking_for & ABS8MEM)
309 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
310 abs |= data[len >> 1] & 0xff;
314 abs = data[len >> 1] & 0xff;
317 else if (looking_for & L_3)
323 else if (looking_for == E)
327 /* Fill in the args. */
329 op_type *args = q->args.nib;
335 int rn = (x & DST) ? rd : rs;
345 p->type = X (OP_IMM, size);
348 else if (x & (IMM | KBIT | DBIT))
350 p->type = X (OP_IMM, size);
355 /* Reset the size, some
356 ops (like mul) have two sizes */
359 p->type = X (OP_REG, size);
364 p->type = X (OP_INC, size);
369 p->type = X (OP_DEC, size);
374 p->type = X (OP_DISP, size);
378 else if (x & (ABS | ABSJMP | ABS8MEM))
380 p->type = X (OP_DISP, size);
386 p->type = X (OP_MEM, size);
391 p->type = X (OP_PCREL, size);
392 p->literal = abs + addr + 2;
398 p->type = X (OP_IMM, SP);
403 p->type = X (OP_DISP, size);
405 p->reg = rdisp & 0x7;
412 printf ("Hmmmm %x", x);
418 /* But a jmp or a jsr gets automagically lvalued,
419 since we branch to their address not their
421 if (q->how == O (O_JSR, SB)
422 || q->how == O (O_JMP, SB))
424 dst->src.type = lvalue (dst->src.type, dst->src.reg);
427 if (dst->dst.type == -1)
430 dst->opcode = q->how;
431 dst->cycles = q->time;
433 /* And a jsr to 0xc4 is turned into a magic trap. */
435 if (dst->opcode == O (O_JSR, SB))
437 if (dst->src.literal == 0xc4)
439 dst->opcode = O (O_SYSCALL, SB);
443 dst->next_pc = addr + len / 2;
447 printf ("Don't understand %x \n", looking_for);
458 /* Fell off the end. */
459 dst->opcode = O (O_ILL, SB);
467 /* find the next cache entry to use */
469 idx = cpu.cache_top + 1;
471 if (idx >= cpu.csize)
477 /* Throw away its old meaning */
478 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
480 /* set to new address */
481 cpu.cache[idx].oldpc = pc;
483 /* fill in instruction info */
484 decode (pc, cpu.memory + pc, cpu.cache + idx);
486 /* point to new cache entry */
487 cpu.cache_idx[pc] = idx;
491 static unsigned char *breg[18];
492 static unsigned short *wreg[18];
493 static unsigned int *lreg[18];
495 #define GET_B_REG(x) *(breg[x])
496 #define SET_B_REG(x,y) (*(breg[x])) = (y)
497 #define GET_W_REG(x) *(wreg[x])
498 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
500 #define GET_L_REG(x) *(lreg[x])
501 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
503 #define GET_MEMORY_L(x) \
505 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
506 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
507 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
508 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
510 #define GET_MEMORY_W(x) \
512 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
513 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
516 #define GET_MEMORY_B(x) \
517 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
519 #define SET_MEMORY_L(x,y) \
520 { register unsigned char *_p; register int __y = y; \
521 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
522 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
523 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
525 #define SET_MEMORY_W(x,y) \
526 { register unsigned char *_p; register int __y = y; \
527 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
528 _p[0] = (__y)>>8; _p[1] =(__y);}
530 #define SET_MEMORY_B(x,y) \
531 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
538 int abs = arg->literal;
545 return GET_B_REG (rn);
547 return GET_W_REG (rn);
549 return GET_L_REG (rn);
560 r = GET_MEMORY_B (t);
569 r = GET_MEMORY_W (t);
577 r = GET_MEMORY_L (t);
584 case X (OP_DISP, SB):
585 t = GET_L_REG (rn) + abs;
587 return GET_MEMORY_B (t);
589 case X (OP_DISP, SW):
590 t = GET_L_REG (rn) + abs;
592 return GET_MEMORY_W (t);
594 case X (OP_DISP, SL):
595 t = GET_L_REG (rn) + abs;
597 return GET_MEMORY_L (t);
600 t = GET_MEMORY_L (abs);
605 t = GET_MEMORY_W (abs);
623 int abs = arg->literal;
639 t = GET_L_REG (rn) - 1;
646 t = (GET_L_REG (rn) - 2) & cpu.mask;
652 t = (GET_L_REG (rn) - 4) & cpu.mask;
657 case X (OP_DISP, SB):
658 t = GET_L_REG (rn) + abs;
663 case X (OP_DISP, SW):
664 t = GET_L_REG (rn) + abs;
669 case X (OP_DISP, SL):
670 t = GET_L_REG (rn) + abs;
707 memory_size = H8300H_MSIZE;
709 memory_size = H8300_MSIZE;
710 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
711 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
712 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
714 /* `msize' must be a power of two */
715 if ((memory_size & (memory_size - 1)) != 0)
717 cpu.mask = memory_size - 1;
719 for (i = 0; i < 9; i++)
724 for (i = 0; i < 8; i++)
726 unsigned char *p = (unsigned char *) (cpu.regs + i);
727 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
728 unsigned short *q = (unsigned short *) (cpu.regs + i);
729 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
730 cpu.regs[i] = 0x00112233;
756 lreg[i] = &cpu.regs[i];
759 lreg[8] = &cpu.regs[8];
761 /* initialize the seg registers */
763 sim_set_simcache_size (CSIZE);
768 control_c (sig, code, scp, addr)
774 cpu.state = SIM_STATE_STOPPED;
775 cpu.exception = SIGINT;
784 mop (code, bsize, sign)
797 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
798 SEXTSHORT (GET_W_REG (code->dst.reg));
800 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
801 SEXTSHORT (GET_W_REG (code->src.reg));
805 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
806 UEXTSHORT (GET_W_REG (code->dst.reg));
808 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
809 UEXTSHORT (GET_W_REG (code->src.reg));
812 result = multiplier * multiplicand;
816 n = result & (bsize ? 0x8000 : 0x80000000);
817 nz = result & (bsize ? 0xffff : 0xffffffff);
821 SET_W_REG (code->dst.reg, result);
825 SET_L_REG (code->dst.reg, result);
827 /* return ((n==1) << 1) | (nz==1); */
831 #define ONOT(name, how) \
836 rd = GET_B_REG (code->src.reg); \
844 rd = GET_W_REG (code->src.reg); \
851 int hm = 0x80000000; \
852 rd = GET_L_REG (code->src.reg); \
857 #define OSHIFTS(name, how1, how2) \
862 rd = GET_B_REG (code->src.reg); \
863 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
877 rd = GET_W_REG (code->src.reg); \
878 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
891 int hm = 0x80000000; \
892 rd = GET_L_REG (code->src.reg); \
893 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
904 #define OBITOP(name,f, s, op) \
909 if (f) ea = fetch (&code->dst); \
910 m=1<< fetch(&code->src); \
912 if(s) store (&code->dst,ea); goto next; \
919 cpu.state = SIM_STATE_STOPPED;
920 cpu.exception = SIGINT;
925 sim_resume (sd, step, siggnal)
931 int tick_start = get_now ();
944 prev = signal (SIGINT, control_c);
948 cpu.state = SIM_STATE_STOPPED;
949 cpu.exception = SIGTRAP;
953 cpu.state = SIM_STATE_RUNNING;
959 /* The PC should never be odd. */
973 cidx = cpu.cache_idx[pc];
974 code = cpu.cache + cidx;
977 #define ALUOP(STORE, NAME, HOW) \
978 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
979 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
980 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
983 #define LOGOP(NAME, HOW) \
984 case O(NAME,SB): HOW; goto log8;\
985 case O(NAME, SW): HOW; goto log16;\
986 case O(NAME,SL): HOW; goto log32;
993 printf ("%x %d %s\n", pc, code->opcode,
994 code->op ? code->op->name : "**");
996 cpu.stats[code->opcode]++;
1000 cycles += code->cycles;
1002 switch (code->opcode)
1006 * This opcode is a fake for when we get to an
1007 * instruction which hasnt been compiled
1014 case O (O_SUBX, SB):
1015 rd = fetch (&code->dst);
1016 ea = fetch (&code->src);
1021 case O (O_ADDX, SB):
1022 rd = fetch (&code->dst);
1023 ea = fetch (&code->src);
1028 #define EA ea = fetch(&code->src);
1029 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1031 ALUOP (1, O_SUB, RD_EA;
1034 ALUOP (1, O_NEG, EA;
1040 rd = GET_B_REG (code->dst.reg);
1041 ea = fetch (&code->src);
1045 rd = GET_W_REG (code->dst.reg);
1046 ea = fetch (&code->src);
1050 rd = GET_L_REG (code->dst.reg);
1051 ea = fetch (&code->src);
1056 LOGOP (O_AND, RD_EA;
1062 LOGOP (O_XOR, RD_EA;
1066 case O (O_MOV_TO_MEM, SB):
1067 res = GET_B_REG (code->src.reg);
1069 case O (O_MOV_TO_MEM, SW):
1070 res = GET_W_REG (code->src.reg);
1072 case O (O_MOV_TO_MEM, SL):
1073 res = GET_L_REG (code->src.reg);
1077 case O (O_MOV_TO_REG, SB):
1078 res = fetch (&code->src);
1079 SET_B_REG (code->dst.reg, res);
1080 goto just_flags_log8;
1081 case O (O_MOV_TO_REG, SW):
1082 res = fetch (&code->src);
1083 SET_W_REG (code->dst.reg, res);
1084 goto just_flags_log16;
1085 case O (O_MOV_TO_REG, SL):
1086 res = fetch (&code->src);
1087 SET_L_REG (code->dst.reg, res);
1088 goto just_flags_log32;
1091 case O (O_ADDS, SL):
1092 SET_L_REG (code->dst.reg,
1093 GET_L_REG (code->dst.reg)
1094 + code->src.literal);
1098 case O (O_SUBS, SL):
1099 SET_L_REG (code->dst.reg,
1100 GET_L_REG (code->dst.reg)
1101 - code->src.literal);
1105 rd = fetch (&code->dst);
1106 ea = fetch (&code->src);
1109 goto just_flags_alu8;
1112 rd = fetch (&code->dst);
1113 ea = fetch (&code->src);
1116 goto just_flags_alu16;
1119 rd = fetch (&code->dst);
1120 ea = fetch (&code->src);
1123 goto just_flags_alu32;
1127 rd = GET_B_REG (code->src.reg);
1130 SET_B_REG (code->src.reg, res);
1131 goto just_flags_inc8;
1134 rd = GET_W_REG (code->dst.reg);
1135 ea = -code->src.literal;
1137 SET_W_REG (code->dst.reg, res);
1138 goto just_flags_inc16;
1141 rd = GET_L_REG (code->dst.reg);
1142 ea = -code->src.literal;
1144 SET_L_REG (code->dst.reg, res);
1145 goto just_flags_inc32;
1149 rd = GET_B_REG (code->src.reg);
1152 SET_B_REG (code->src.reg, res);
1153 goto just_flags_inc8;
1156 rd = GET_W_REG (code->dst.reg);
1157 ea = code->src.literal;
1159 SET_W_REG (code->dst.reg, res);
1160 goto just_flags_inc16;
1163 rd = GET_L_REG (code->dst.reg);
1164 ea = code->src.literal;
1166 SET_L_REG (code->dst.reg, res);
1167 goto just_flags_inc32;
1170 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1172 case O (O_ANDC, SB):
1174 ea = code->src.literal;
1180 ea = code->src.literal;
1184 case O (O_XORC, SB):
1186 ea = code->src.literal;
1227 if (((Z || (N ^ V)) == 0))
1233 if (((Z || (N ^ V)) == 1))
1267 case O (O_SYSCALL, SB):
1269 char c = cpu.regs[2];
1270 sim_callback->write_stdout (sim_callback, &c, 1);
1274 ONOT (O_NOT, rd = ~rd; v = 0;);
1276 c = rd & hm; v = 0; rd <<= 1,
1277 c = rd & (hm >> 1); v = 0; rd <<= 2);
1279 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1280 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1282 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1283 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1285 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1286 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1288 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1289 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1291 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1292 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1294 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1295 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1297 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1298 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1302 pc = fetch (&code->src);
1310 pc = fetch (&code->src);
1317 SET_MEMORY_L (tmp, code->next_pc);
1322 SET_MEMORY_W (tmp, code->next_pc);
1329 pc = code->src.literal;
1340 pc = GET_MEMORY_L (tmp);
1345 pc = GET_MEMORY_W (tmp);
1354 cpu.state = SIM_STATE_STOPPED;
1355 cpu.exception = SIGILL;
1357 case O (O_SLEEP, SN):
1358 /* The format of r0 is defined by devo/include/wait.h. */
1359 #if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */
1360 if (WIFEXITED (cpu.regs[0]))
1362 cpu.state = SIM_STATE_EXITED;
1363 cpu.exception = WEXITSTATUS (cpu.regs[0]);
1365 else if (WIFSTOPPED (cpu.regs[0]))
1367 cpu.state = SIM_STATE_STOPPED;
1368 cpu.exception = WSTOPSIG (cpu.regs[0]);
1372 cpu.state = SIM_STATE_SIGNALLED;
1373 cpu.exception = WTERMSIG (cpu.regs[0]);
1376 /* FIXME: Doesn't this break for breakpoints when r0
1377 contains just the right (er, wrong) value? */
1378 cpu.state = SIM_STATE_STOPPED;
1379 if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0]))
1380 cpu.exception = SIGILL;
1382 cpu.exception = SIGTRAP;
1386 cpu.state = SIM_STATE_STOPPED;
1387 cpu.exception = SIGTRAP;
1390 OBITOP (O_BNOT, 1, 1, ea ^= m);
1391 OBITOP (O_BTST, 1, 0, nz = ea & m);
1392 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1393 OBITOP (O_BSET, 1, 1, ea |= m);
1394 OBITOP (O_BLD, 1, 0, c = ea & m);
1395 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1396 OBITOP (O_BST, 1, 1, ea &= ~m;
1398 OBITOP (O_BIST, 1, 1, ea &= ~m;
1400 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1401 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1402 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1403 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1404 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1405 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1408 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1410 case O (O_MULS, SB):
1413 case O (O_MULS, SW):
1416 case O (O_MULU, SB):
1419 case O (O_MULU, SW):
1424 case O (O_DIVU, SB):
1426 rd = GET_W_REG (code->dst.reg);
1427 ea = GET_B_REG (code->src.reg);
1430 tmp = (unsigned)rd % ea;
1431 rd = (unsigned)rd / ea;
1433 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1439 case O (O_DIVU, SW):
1441 rd = GET_L_REG (code->dst.reg);
1442 ea = GET_W_REG (code->src.reg);
1447 tmp = (unsigned)rd % ea;
1448 rd = (unsigned)rd / ea;
1450 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1454 case O (O_DIVS, SB):
1457 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1458 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1461 tmp = (int) rd % (int) ea;
1462 rd = (int) rd / (int) ea;
1468 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1471 case O (O_DIVS, SW):
1473 rd = GET_L_REG (code->dst.reg);
1474 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1477 tmp = (int) rd % (int) ea;
1478 rd = (int) rd / (int) ea;
1479 n = rd & 0x80000000;
1484 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1487 case O (O_EXTS, SW):
1488 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1489 ea = rd & 0x80 ? -256 : 0;
1492 case O (O_EXTS, SL):
1493 rd = GET_W_REG (code->src.reg) & 0xffff;
1494 ea = rd & 0x8000 ? -65536 : 0;
1497 case O (O_EXTU, SW):
1498 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1502 case O (O_EXTU, SL):
1503 rd = GET_W_REG (code->src.reg) & 0xffff;
1513 int nregs, firstreg, i;
1515 nregs = GET_MEMORY_B (pc + 1);
1518 firstreg = GET_MEMORY_B (pc + 3);
1520 for (i = firstreg; i <= firstreg + nregs; i++)
1523 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1530 int nregs, firstreg, i;
1532 nregs = GET_MEMORY_B (pc + 1);
1535 firstreg = GET_MEMORY_B (pc + 3);
1537 for (i = firstreg; i >= firstreg - nregs; i--)
1539 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1546 cpu.state = SIM_STATE_STOPPED;
1547 cpu.exception = SIGILL;
1559 /* When a branch works */
1560 pc = code->src.literal;
1563 /* Set the cond codes from res */
1566 /* Set the flags after an 8 bit inc/dec operation */
1570 v = (rd & 0x7f) == 0x7f;
1574 /* Set the flags after an 16 bit inc/dec operation */
1578 v = (rd & 0x7fff) == 0x7fff;
1582 /* Set the flags after an 32 bit inc/dec operation */
1584 n = res & 0x80000000;
1585 nz = res & 0xffffffff;
1586 v = (rd & 0x7fffffff) == 0x7fffffff;
1591 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1594 SET_B_REG (code->src.reg, rd);
1598 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1601 SET_W_REG (code->src.reg, rd);
1605 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1606 n = (rd & 0x80000000);
1607 nz = rd & 0xffffffff;
1608 SET_L_REG (code->src.reg, rd);
1612 store (&code->dst, res);
1614 /* flags after a 32bit logical operation */
1615 n = res & 0x80000000;
1616 nz = res & 0xffffffff;
1621 store (&code->dst, res);
1623 /* flags after a 16bit logical operation */
1631 store (&code->dst, res);
1639 SET_B_REG (code->dst.reg, res);
1644 switch (code->opcode / 4)
1647 v = ((rd & 0x80) == (ea & 0x80)
1648 && (rd & 0x80) != (res & 0x80));
1652 v = ((rd & 0x80) != (-ea & 0x80)
1653 && (rd & 0x80) != (res & 0x80));
1662 SET_W_REG (code->dst.reg, res);
1666 c = (res & 0x10000);
1667 switch (code->opcode / 4)
1670 v = ((rd & 0x8000) == (ea & 0x8000)
1671 && (rd & 0x8000) != (res & 0x8000));
1675 v = ((rd & 0x8000) != (-ea & 0x8000)
1676 && (rd & 0x8000) != (res & 0x8000));
1685 SET_L_REG (code->dst.reg, res);
1687 n = res & 0x80000000;
1688 nz = res & 0xffffffff;
1689 switch (code->opcode / 4)
1692 v = ((rd & 0x80000000) == (ea & 0x80000000)
1693 && (rd & 0x80000000) != (res & 0x80000000));
1694 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1698 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1699 && (rd & 0x80000000) != (res & 0x80000000));
1700 c = (unsigned) rd < (unsigned) -ea;
1703 v = (rd == 0x80000000);
1714 /* if (cpu.regs[8] ) abort(); */
1716 if (--poll_count < 0)
1718 poll_count = POLL_QUIT_INTERVAL;
1719 if ((*sim_callback->poll_quit) != NULL
1720 && (*sim_callback->poll_quit) (sim_callback))
1725 while (cpu.state == SIM_STATE_RUNNING);
1726 cpu.ticks += get_now () - tick_start;
1727 cpu.cycles += cycles;
1733 signal (SIGINT, prev);
1740 /* FIXME: unfinished */
1745 sim_write (sd, addr, buffer, size)
1748 unsigned char *buffer;
1756 for (i = 0; i < size; i++)
1758 if (addr < memory_size)
1760 cpu.memory[addr + i] = buffer[i];
1761 cpu.cache_idx[addr + i] = 0;
1764 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1770 sim_read (sd, addr, buffer, size)
1773 unsigned char *buffer;
1779 if (addr < memory_size)
1780 memcpy (buffer, cpu.memory + addr, size);
1782 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1796 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1797 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1800 #define CCR_REGNUM 8 /* Contains processor status */
1801 #define PC_REGNUM 9 /* Contains program counter */
1803 #define CYCLE_REGNUM 10
1804 #define INST_REGNUM 11
1805 #define TICK_REGNUM 12
1809 sim_store_register (sd, rn, value, length)
1812 unsigned char *value;
1818 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1819 shortval = (value[0] << 8) | (value[1]);
1820 intval = h8300hmode ? longval : shortval;
1838 cpu.regs[rn] = intval;
1844 cpu.cycles = longval;
1848 cpu.insts = longval;
1852 cpu.ticks = longval;
1859 sim_fetch_register (sd, rn, buf, length)
1903 if (h8300hmode || longreg)
1919 sim_stop_reason (sd, reason, sigrc)
1921 enum sim_stop *reason;
1924 #if 0 /* FIXME: This should work but we can't use it.
1925 grep for SLEEP above. */
1928 case SIM_STATE_EXITED : *reason = sim_exited; break;
1929 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1930 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1934 *reason = sim_stopped;
1936 *sigrc = cpu.exception;
1939 /* FIXME: Rename to sim_set_mem_size. */
1945 /* Memory size is fixed. */
1949 sim_set_simcache_size (n)
1955 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1956 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1962 sim_info (sd, verbose)
1966 double timetaken = (double) cpu.ticks / (double) now_persec ();
1967 double virttime = cpu.cycles / 10.0e6;
1969 (*sim_callback->printf_filtered) (sim_callback,
1970 "\n\n#instructions executed %10d\n",
1972 (*sim_callback->printf_filtered) (sim_callback,
1973 "#cycles (v approximate) %10d\n",
1975 (*sim_callback->printf_filtered) (sim_callback,
1976 "#real time taken %10.4f\n",
1978 (*sim_callback->printf_filtered) (sim_callback,
1979 "#virtual time taked %10.4f\n",
1981 if (timetaken != 0.0)
1982 (*sim_callback->printf_filtered) (sim_callback,
1983 "#simulation ratio %10.4f\n",
1984 virttime / timetaken);
1985 (*sim_callback->printf_filtered) (sim_callback,
1988 (*sim_callback->printf_filtered) (sim_callback,
1989 "#cache size %10d\n",
1993 /* This to be conditional on `what' (aka `verbose'),
1994 however it was never passed as non-zero. */
1998 for (i = 0; i < O_LAST; i++)
2001 (*sim_callback->printf_filtered) (sim_callback,
2002 "%d: %d\n", i, cpu.stats[i]);
2008 /* Indicate whether the cpu is an h8/300 or h8/300h.
2009 FLAG is non-zero for the h8/300h. */
2015 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2016 This function being replaced by a sim_open:ARGV configuration
2022 sim_open (kind, ptr, abfd, argv)
2024 struct host_callback_struct *ptr;
2028 /* FIXME: Much of the code in sim_load can be moved here */
2033 /* fudge our descriptor */
2034 return (SIM_DESC) 1;
2038 sim_close (sd, quitting)
2045 /* Called by gdb to load a program into memory. */
2048 sim_load (sd, prog, abfd, from_tty)
2056 /* FIXME: The code below that sets a specific variant of the h8/300
2057 being simulated should be moved to sim_open(). */
2059 /* See if the file is for the h8/300 or h8/300h. */
2060 /* ??? This may not be the most efficient way. The z8k simulator
2061 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2065 prog_bfd = bfd_openr (prog, "coff-h8300");
2066 if (prog_bfd != NULL)
2068 /* Set the cpu type. We ignore failure from bfd_check_format
2069 and bfd_openr as sim_load_file checks too. */
2070 if (bfd_check_format (prog_bfd, bfd_object))
2072 unsigned long mach = bfd_get_mach (prog_bfd);
2073 set_h8300h (mach == bfd_mach_h8300h
2074 || mach == bfd_mach_h8300s);
2078 /* If we're using gdb attached to the simulator, then we have to
2079 reallocate memory for the simulator.
2081 When gdb first starts, it calls fetch_registers (among other
2082 functions), which in turn calls init_pointers, which allocates
2085 The problem is when we do that, we don't know whether we're
2086 debugging an h8/300 or h8/300h program.
2088 This is the first point at which we can make that determination,
2089 so we just reallocate memory now; this will also allow us to handle
2090 switching between h8/300 and h8/300h programs without exiting
2093 memory_size = H8300H_MSIZE;
2095 memory_size = H8300_MSIZE;
2100 free (cpu.cache_idx);
2102 free (cpu.eightbit);
2104 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2105 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2106 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2108 /* `msize' must be a power of two */
2109 if ((memory_size & (memory_size - 1)) != 0)
2111 cpu.mask = memory_size - 1;
2113 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2114 sim_kind == SIM_OPEN_DEBUG,
2118 /* Close the bfd if we opened it. */
2119 if (abfd == NULL && prog_bfd != NULL)
2120 bfd_close (prog_bfd);
2124 /* Close the bfd if we opened it. */
2125 if (abfd == NULL && prog_bfd != NULL)
2126 bfd_close (prog_bfd);
2131 sim_create_inferior (sd, abfd, argv, env)
2138 cpu.pc = bfd_get_start_address (abfd);
2145 sim_do_command (sd, cmd)
2149 (*sim_callback->printf_filtered) (sim_callback,
2150 "This simulator does not accept any commands.\n");
2154 sim_set_callbacks (ptr)
2155 struct host_callback_struct *ptr;