2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
29 #include <sys/param.h>
33 #include "remote-sim.h"
39 #define X(op, size) op*4+size
41 #define SP (h8300hmode ? SL:SW)
54 #define h8_opcodes ops
56 #include "opcode/h8300.h"
60 #define LOW_BYTE(x) ((x) & 0xff)
61 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
62 #define P(X,Y) ((X<<8) | Y)
64 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
67 c = (cpu.ccr >> 0) & 1;\
68 v = (cpu.ccr >> 1) & 1;\
69 nz = !((cpu.ccr >> 2) & 1);\
70 n = (cpu.ccr >> 3) & 1;
72 #ifdef __CHAR_IS_SIGNED__
73 #define SEXTCHAR(x) ((char)(x))
77 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
80 #define UEXTCHAR(x) ((x) & 0xff)
81 #define UEXTSHORT(x) ((x) & 0xffff)
82 #define SEXTSHORT(x) ((short)(x))
84 static cpu_state_type cpu;
88 static int memory_size;
119 return h8300hmode ? SL : SW;
132 return X (OP_IMM, SP);
134 return X (OP_REG, SP);
138 return X (OP_MEM, SP);
145 decode (addr, data, dst)
158 struct h8_opcode *q = h8_opcodes;
162 /* Find the exact opcode/arg combo */
166 unsigned int len = 0;
172 op_type looking_for = *nib;
173 int thisnib = data[len >> 1];
175 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
177 if (looking_for < 16 && looking_for >= 0)
179 if (looking_for != thisnib)
184 if ((int) looking_for & (int) B31)
186 if (!(((int) thisnib & 0x8) != 0))
188 looking_for = (op_type) ((int) looking_for & ~(int)
192 if ((int) looking_for & (int) B30)
194 if (!(((int) thisnib & 0x8) == 0))
196 looking_for = (op_type) ((int) looking_for & ~(int) B30);
198 if (looking_for & DBIT)
200 if ((looking_for & 5) != (thisnib & 5))
202 abs = (thisnib & 0x8) ? 2 : 1;
204 else if (looking_for & (REG | IND | INC | DEC))
206 if (looking_for & REG)
209 * Can work out size from the
212 size = bitfrom (looking_for);
214 if (looking_for & SRC)
223 else if (looking_for & L_16)
225 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
227 if (looking_for & (PCREL | DISP))
232 else if (looking_for & ABSJMP)
239 else if (looking_for & MEMIND)
243 else if (looking_for & L_32)
246 abs = (data[i] << 24)
247 | (data[i + 1] << 16)
253 else if (looking_for & L_24)
256 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
259 else if (looking_for & IGNORE)
263 else if (looking_for & DISPREG)
265 rdisp = thisnib & 0x7;
267 else if (looking_for & KBIT)
282 else if (looking_for & L_8)
286 if (looking_for & PCREL)
288 abs = SEXTCHAR (data[len >> 1]);
290 else if (looking_for & ABS8MEM)
293 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
294 abs |= data[len >> 1] & 0xff ;
298 abs = data[len >> 1] & 0xff;
301 else if (looking_for & L_3)
307 else if (looking_for == E)
311 /* Fill in the args */
313 op_type *args = q->args.nib;
319 int rn = (x & DST) ? rd : rs;
333 p->type = X (OP_IMM, size);
336 else if (x & (IMM | KBIT | DBIT))
338 p->type = X (OP_IMM, size);
343 /* Reset the size, some
344 ops (like mul) have two sizes */
347 p->type = X (OP_REG, size);
352 p->type = X (OP_INC, size);
357 p->type = X (OP_DEC, size);
362 p->type = X (OP_DISP, size);
366 else if (x & (ABS | ABSJMP | ABS8MEM))
368 p->type = X (OP_DISP, size);
374 p->type = X (OP_MEM, size);
379 p->type = X (OP_PCREL, size);
380 p->literal = abs + addr + 2;
386 p->type = X (OP_IMM, SP);
391 p->type = X (OP_DISP, size);
393 p->reg = rdisp & 0x7;
400 printf ("Hmmmm %x", x);
407 * But a jmp or a jsr gets
408 * automagically lvalued, since we
409 * branch to their address not their
412 if (q->how == O (O_JSR, SB)
413 || q->how == O (O_JMP, SB))
415 dst->src.type = lvalue (dst->src.type, dst->src.reg);
418 if (dst->dst.type == -1)
421 dst->opcode = q->how;
422 dst->cycles = q->time;
424 /* And a jsr to 0xc4 is turned into a magic trap */
426 if (dst->opcode == O (O_JSR, SB))
428 if (dst->src.literal == 0xc4)
430 dst->opcode = O (O_SYSCALL, SB);
434 dst->next_pc = addr + len / 2;
439 printf ("Dont understand %x \n", looking_for);
451 dst->opcode = O (O_ILL, SB);
460 /* find the next cache entry to use */
462 idx = cpu.cache_top + 1;
464 if (idx >= cpu.csize)
470 /* Throw away its old meaning */
471 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
473 /* set to new address */
474 cpu.cache[idx].oldpc = pc;
476 /* fill in instruction info */
477 decode (pc, cpu.memory + pc, cpu.cache + idx);
479 /* point to new cache entry */
480 cpu.cache_idx[pc] = idx;
484 static unsigned char *breg[18];
485 static unsigned short *wreg[18];
486 static unsigned int *lreg[18];
488 #define GET_B_REG(x) *(breg[x])
489 #define SET_B_REG(x,y) (*(breg[x])) = (y)
490 #define GET_W_REG(x) *(wreg[x])
491 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
493 #define GET_L_REG(x) *(lreg[x])
494 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
496 #define GET_MEMORY_L(x) \
498 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
499 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
500 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
501 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
503 #define GET_MEMORY_W(x) \
505 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
506 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
509 #define GET_MEMORY_B(x) \
510 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
512 #define SET_MEMORY_L(x,y) \
513 { register unsigned char *_p; register int __y = y; \
514 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
515 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
516 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
518 #define SET_MEMORY_W(x,y) \
519 { register unsigned char *_p; register int __y = y; \
520 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
521 _p[0] = (__y)>>8; _p[1] =(__y);}
523 #define SET_MEMORY_B(x,y) \
524 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
531 int abs = arg->literal;
538 return GET_B_REG (rn);
540 return GET_W_REG (rn);
542 return GET_L_REG (rn);
553 r = GET_MEMORY_B (t);
562 r = GET_MEMORY_W (t);
570 r = GET_MEMORY_L (t);
577 case X (OP_DISP, SB):
578 t = GET_L_REG (rn) + abs;
580 return GET_MEMORY_B (t);
582 case X (OP_DISP, SW):
583 t = GET_L_REG (rn) + abs;
585 return GET_MEMORY_W (t);
587 case X (OP_DISP, SL):
588 t = GET_L_REG (rn) + abs;
590 return GET_MEMORY_L (t);
593 t = GET_MEMORY_L (abs);
598 t = GET_MEMORY_W (abs);
616 int abs = arg->literal;
632 t = GET_L_REG (rn) - 1;
639 t = (GET_L_REG (rn) - 2) & cpu.mask;
645 t = (GET_L_REG (rn) - 4) & cpu.mask;
650 case X (OP_DISP, SB):
651 t = GET_L_REG (rn) + abs;
656 case X (OP_DISP, SW):
657 t = GET_L_REG (rn) + abs;
662 case X (OP_DISP, SL):
663 t = GET_L_REG (rn) + abs;
700 memory_size = H8300H_MSIZE;
702 memory_size = H8300_MSIZE;
703 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
704 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
705 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
707 /* `msize' must be a power of two */
708 if ((memory_size & (memory_size - 1)) != 0)
710 cpu.mask = memory_size - 1;
712 for (i = 0; i < 9; i++)
717 for (i = 0; i < 8; i++)
719 unsigned char *p = (unsigned char *) (cpu.regs + i);
720 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
721 unsigned short *q = (unsigned short *) (cpu.regs + i);
722 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
723 cpu.regs[i] = 0x00112233;
749 lreg[i] = &cpu.regs[i];
752 lreg[8] = &cpu.regs[8];
754 /* initialize the seg registers */
761 control_c (sig, code, scp, addr)
767 cpu.exception = SIGINT;
776 mop (code, bsize, sign)
789 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
790 SEXTSHORT (GET_W_REG (code->dst.reg));
792 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
793 SEXTSHORT (GET_W_REG (code->src.reg));
797 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
798 UEXTSHORT (GET_W_REG (code->dst.reg));
800 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
801 UEXTSHORT (GET_W_REG (code->src.reg));
804 result = multiplier * multiplicand;
808 n = result & (bsize ? 0x8000 : 0x80000000);
809 nz = result & (bsize ? 0xffff : 0xffffffff);
813 SET_W_REG (code->dst.reg, result);
817 SET_L_REG (code->dst.reg, result);
819 /* return ((n==1) << 1) | (nz==1); */
823 #define OSHIFTS(name, how) \
828 rd = GET_B_REG (code->src.reg); \
836 rd = GET_W_REG (code->src.reg); \
843 int hm = 0x80000000; \
844 rd = GET_L_REG (code->src.reg); \
849 #define OBITOP(name,f, s, op) \
854 if (f) ea = fetch (&code->dst); \
855 m=1<< fetch(&code->src); \
857 if(s) store (&code->dst,ea); goto next; \
861 sim_resume (step, siggnal)
866 int tick_start = get_now ();
879 prev = signal (SIGINT, control_c);
883 cpu.exception = SIGTRAP;
892 /* The PC should never be odd. */
906 cidx = cpu.cache_idx[pc];
907 code = cpu.cache + cidx;
910 #define ALUOP(STORE, NAME, HOW) \
911 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
912 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
913 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
916 #define LOGOP(NAME, HOW) \
917 case O(NAME,SB): HOW; goto log8;\
918 case O(NAME, SW): HOW; goto log16;\
919 case O(NAME,SL): HOW; goto log32;
926 printf ("%x %d %s\n", pc, code->opcode,
927 code->op ? code->op->name : "**");
929 cpu.stats[code->opcode]++;
933 cycles += code->cycles;
935 switch (code->opcode)
939 * This opcode is a fake for when we get to an
940 * instruction which hasnt been compiled
948 rd = fetch (&code->dst);
949 ea = fetch (&code->src);
955 rd = fetch (&code->dst);
956 ea = fetch (&code->src);
961 #define EA ea = fetch(&code->src);
962 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
964 ALUOP (1, O_SUB, RD_EA;
973 rd = GET_B_REG (code->dst.reg);
974 ea = fetch (&code->src);
978 rd = GET_W_REG (code->dst.reg);
979 ea = fetch (&code->src);
983 rd = GET_L_REG (code->dst.reg);
984 ea = fetch (&code->src);
999 case O (O_MOV_TO_MEM, SB):
1000 res = GET_B_REG (code->src.reg);
1002 case O (O_MOV_TO_MEM, SW):
1003 res = GET_W_REG (code->src.reg);
1005 case O (O_MOV_TO_MEM, SL):
1006 res = GET_L_REG (code->src.reg);
1010 case O (O_MOV_TO_REG, SB):
1011 res = fetch (&code->src);
1012 SET_B_REG (code->dst.reg, res);
1013 goto just_flags_log8;
1014 case O (O_MOV_TO_REG, SW):
1015 res = fetch (&code->src);
1016 SET_W_REG (code->dst.reg, res);
1017 goto just_flags_log16;
1018 case O (O_MOV_TO_REG, SL):
1019 res = fetch (&code->src);
1020 SET_L_REG (code->dst.reg, res);
1021 goto just_flags_log32;
1024 case O (O_ADDS, SL):
1025 SET_L_REG (code->dst.reg,
1026 GET_L_REG (code->dst.reg)
1027 + code->src.literal);
1031 case O (O_SUBS, SL):
1032 SET_L_REG (code->dst.reg,
1033 GET_L_REG (code->dst.reg)
1034 - code->src.literal);
1038 rd = fetch (&code->dst);
1039 ea = fetch (&code->src);
1042 goto just_flags_alu8;
1045 rd = fetch (&code->dst);
1046 ea = fetch (&code->src);
1049 goto just_flags_alu16;
1052 rd = fetch (&code->dst);
1053 ea = fetch (&code->src);
1056 goto just_flags_alu32;
1060 rd = GET_B_REG (code->src.reg);
1063 SET_B_REG (code->src.reg, res);
1064 goto just_flags_inc8;
1067 rd = GET_W_REG (code->dst.reg);
1068 ea = -code->src.literal;
1070 SET_W_REG (code->dst.reg, res);
1071 goto just_flags_inc16;
1074 rd = GET_L_REG (code->dst.reg);
1075 ea = -code->src.literal;
1077 SET_L_REG (code->dst.reg, res);
1078 goto just_flags_inc32;
1082 rd = GET_B_REG (code->src.reg);
1085 SET_B_REG (code->src.reg, res);
1086 goto just_flags_inc8;
1089 rd = GET_W_REG (code->dst.reg);
1090 ea = code->src.literal;
1092 SET_W_REG (code->dst.reg, res);
1093 goto just_flags_inc16;
1096 rd = GET_L_REG (code->dst.reg);
1097 ea = code->src.literal;
1099 SET_L_REG (code->dst.reg, res);
1100 goto just_flags_inc32;
1103 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1105 case O (O_ANDC, SB):
1107 ea = code->src.literal;
1113 ea = code->src.literal;
1117 case O (O_XORC, SB):
1119 ea = code->src.literal;
1160 if (((Z || (N ^ V)) == 0))
1166 if (((Z || (N ^ V)) == 1))
1200 case O (O_SYSCALL, SB):
1201 printf ("%c", cpu.regs[2]);
1204 OSHIFTS (O_NOT, rd = ~rd; v = 0;);
1205 OSHIFTS (O_SHLL, c = rd & hm; v = 0;
1207 OSHIFTS (O_SHLR, c = rd & 1; v = 0;
1208 rd = (unsigned int) rd >> 1);
1209 OSHIFTS (O_SHAL, c = rd & hm;
1210 v = (rd & hm) != ((rd & (hm >> 1)) << 1);
1212 OSHIFTS (O_SHAR, t = rd & hm;
1218 OSHIFTS (O_ROTL, c = rd & hm;
1222 OSHIFTS (O_ROTR, c = rd & 1;
1224 rd = (unsigned int) rd >> 1;
1226 OSHIFTS (O_ROTXL, t = rd & hm;
1232 OSHIFTS (O_ROTXR, t = rd & 1;
1233 rd = (unsigned int) rd >> 1;
1234 if (C) rd |= hm; c = t;
1239 pc = fetch (&code->src);
1247 pc = fetch (&code->src);
1254 SET_MEMORY_L (tmp, code->next_pc);
1259 SET_MEMORY_W (tmp, code->next_pc);
1266 pc = code->src.literal;
1277 pc = GET_MEMORY_L (tmp);
1282 pc = GET_MEMORY_W (tmp);
1291 cpu.exception = SIGILL;
1293 case O (O_SLEEP, SB):
1294 /* The format of r0 is defined by devo/include/wait.h.
1295 cpu.exception handling needs some cleanup: we need to make the
1296 the handling of normal exits vs signals, etc. more sensible. */
1297 if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0]))
1298 cpu.exception = SIGILL;
1300 cpu.exception = SIGTRAP;
1303 cpu.exception = SIGTRAP;
1306 OBITOP (O_BNOT, 1, 1, ea ^= m);
1307 OBITOP (O_BTST, 1, 0, nz = ea & m);
1308 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1309 OBITOP (O_BSET, 1, 1, ea |= m);
1310 OBITOP (O_BLD, 1, 0, c = ea & m);
1311 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1312 OBITOP (O_BST, 1, 1, ea &= ~m;
1314 OBITOP (O_BIST, 1, 1, ea &= ~m;
1316 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1317 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1318 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1319 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1320 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1321 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1324 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1326 case O (O_MULS, SB):
1329 case O (O_MULS, SW):
1332 case O (O_MULU, SB):
1335 case O (O_MULU, SW):
1340 case O (O_DIVU, SB):
1342 rd = GET_W_REG (code->dst.reg);
1343 ea = GET_B_REG (code->src.reg);
1346 tmp = (unsigned)rd % ea;
1347 rd = (unsigned)rd / ea;
1349 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1355 case O (O_DIVU, SW):
1357 rd = GET_L_REG (code->dst.reg);
1358 ea = GET_W_REG (code->src.reg);
1363 tmp = (unsigned)rd % ea;
1364 rd = (unsigned)rd / ea;
1366 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1370 case O (O_DIVS, SB):
1373 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1374 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1377 tmp = (int) rd % (int) ea;
1378 rd = (int) rd / (int) ea;
1384 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1387 case O (O_DIVS, SW):
1389 rd = GET_L_REG (code->dst.reg);
1390 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1393 tmp = (int) rd % (int) ea;
1394 rd = (int) rd / (int) ea;
1395 n = rd & 0x80000000;
1400 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1403 case O (O_EXTS, SW):
1404 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1405 ea = rd & 0x80 ? -256 : 0;
1408 case O (O_EXTS, SL):
1409 rd = GET_W_REG (code->src.reg) & 0xffff;
1410 ea = rd & 0x8000 ? -65536 : 0;
1413 case O (O_EXTU, SW):
1414 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1418 case O (O_EXTU, SL):
1419 rd = GET_W_REG (code->src.reg) & 0xffff;
1428 cpu.exception = SIGILL;
1440 /* When a branch works */
1441 pc = code->src.literal;
1444 /* Set the cond codes from res */
1447 /* Set the flags after an 8 bit inc/dec operation */
1451 v = (rd & 0x7f) == 0x7f;
1455 /* Set the flags after an 16 bit inc/dec operation */
1459 v = (rd & 0x7fff) == 0x7fff;
1463 /* Set the flags after an 32 bit inc/dec operation */
1465 n = res & 0x80000000;
1466 nz = res & 0xffffffff;
1467 v = (rd & 0x7fffffff) == 0x7fffffff;
1472 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1475 SET_B_REG (code->src.reg, rd);
1479 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1482 SET_W_REG (code->src.reg, rd);
1486 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1487 n = (rd & 0x80000000);
1488 nz = rd & 0xffffffff;
1489 SET_L_REG (code->src.reg, rd);
1493 store (&code->dst, res);
1495 /* flags after a 32bit logical operation */
1496 n = res & 0x80000000;
1497 nz = res & 0xffffffff;
1502 store (&code->dst, res);
1504 /* flags after a 16bit logical operation */
1512 store (&code->dst, res);
1520 SET_B_REG (code->dst.reg, res);
1525 switch (code->opcode / 4)
1528 v = ((rd & 0x80) == (ea & 0x80)
1529 && (rd & 0x80) != (res & 0x80));
1533 v = ((rd & 0x80) != (-ea & 0x80)
1534 && (rd & 0x80) != (res & 0x80));
1543 SET_W_REG (code->dst.reg, res);
1547 c = (res & 0x10000);
1548 switch (code->opcode / 4)
1551 v = ((rd & 0x8000) == (ea & 0x8000)
1552 && (rd & 0x8000) != (res & 0x8000));
1556 v = ((rd & 0x8000) != (-ea & 0x8000)
1557 && (rd & 0x8000) != (res & 0x8000));
1566 SET_L_REG (code->dst.reg, res);
1568 n = res & 0x80000000;
1569 nz = res & 0xffffffff;
1570 switch (code->opcode / 4)
1573 v = ((rd & 0x80000000) == (ea & 0x80000000)
1574 && (rd & 0x80000000) != (res & 0x80000000));
1575 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1579 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1580 && (rd & 0x80000000) != (res & 0x80000000));
1581 c = (unsigned) rd < (unsigned) -ea;
1584 v = (rd == 0x80000000);
1595 /* if (cpu.regs[8] ) abort(); */
1598 /* Poll after every 100th insn, */
1599 if (poll_count++ > 100)
1602 if (win32pollquit())
1608 #if defined(__GO32__)
1609 /* Poll after every 100th insn, */
1610 if (poll_count++ > 100)
1622 while (!cpu.exception);
1623 cpu.ticks += get_now () - tick_start;
1624 cpu.cycles += cycles;
1630 signal (SIGINT, prev);
1635 sim_write (addr, buffer, size)
1637 unsigned char *buffer;
1645 for (i = 0; i < size; i++)
1647 if (addr < memory_size)
1649 cpu.memory[addr + i] = buffer[i];
1650 cpu.cache_idx[addr + i] = 0;
1653 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1659 sim_read (addr, buffer, size)
1661 unsigned char *buffer;
1667 if (addr < memory_size)
1668 memcpy (buffer, cpu.memory + addr, size);
1670 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1684 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1685 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1688 #define CCR_REGNUM 8 /* Contains processor status */
1689 #define PC_REGNUM 9 /* Contains program counter */
1691 #define CYCLE_REGNUM 10
1692 #define INST_REGNUM 11
1693 #define TICK_REGNUM 12
1697 sim_store_register (rn, value)
1699 unsigned char *value;
1704 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1705 shortval = (value[0] << 8) | (value[1]);
1706 intval = h8300hmode ? longval : shortval;
1724 cpu.regs[rn] = intval;
1730 cpu.cycles = longval;
1734 cpu.insts = longval;
1738 cpu.ticks = longval;
1744 sim_fetch_register (rn, buf)
1786 if (h8300hmode || longreg)
1801 sim_stop_reason (reason, sigrc)
1802 enum sim_stop *reason;
1805 *reason = sim_stopped;
1806 *sigrc = cpu.exception;
1815 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1816 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1825 double timetaken = (double) cpu.ticks / (double) now_persec ();
1826 double virttime = cpu.cycles / 10.0e6;
1828 printf_filtered ("\n\n#instructions executed %10d\n", cpu.insts);
1829 printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles);
1830 printf_filtered ("#real time taken %10.4f\n", timetaken);
1831 printf_filtered ("#virtual time taked %10.4f\n", virttime);
1832 if (timetaken != 0.0)
1833 printf_filtered ("#simulation ratio %10.4f\n", virttime / timetaken);
1834 printf_filtered ("#compiles %10d\n", cpu.compiles);
1835 printf_filtered ("#cache size %10d\n", cpu.csize);
1841 for (i = 0; i < O_LAST; i++)
1844 printf_filtered ("%d: %d\n", i, cpu.stats[i]);
1850 /* Indicate whether the cpu is an h8/300 or h8/300h.
1851 FLAG is non-zero for the h8/300h. */
1874 sim_close (quitting)
1880 /* Called by gdb to load a program into memory. */
1883 sim_load (prog, from_tty)
1889 /* See if the file is for the h8/300 or h8/300h. */
1890 /* ??? This may not be the most efficient way. The z8k simulator
1891 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
1892 if ((abfd = bfd_openr (prog, "coff-h8300")) != 0)
1894 if (bfd_check_format (abfd, bfd_object))
1895 set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h);
1899 /* If we're using gdb attached to the simulator, then we have to
1900 reallocate memory for the simulator.
1902 When gdb first starts, it calls fetch_registers (among other
1903 functions), which in turn calls init_pointers, which allocates
1906 The problem is when we do that, we don't know whether we're
1907 debugging an h8/300 or h8/300h program.
1909 This is the first point at which we can make that determination,
1910 so we just reallocate memory now; this will also allow us to handle
1911 switching between h8/300 and h8/300h programs without exiting
1914 memory_size = H8300H_MSIZE;
1916 memory_size = H8300_MSIZE;
1921 free (cpu.cache_idx);
1923 free (cpu.eightbit);
1925 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
1926 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
1927 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
1929 /* `msize' must be a power of two */
1930 if ((memory_size & (memory_size - 1)) != 0)
1932 cpu.mask = memory_size - 1;
1934 /* Return non-zero so gdb will handle it. */
1939 sim_create_inferior (start_address, argv, env)
1940 SIM_ADDR start_address;
1944 cpu.pc = start_address;
1948 sim_do_command (cmd)
1951 printf_filtered ("This simulator does not accept any commands.\n");
1957 sim_set_callbacks (ptr)
1958 struct host_callback_struct *ptr;