2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
22 #include <sys/times.h>
24 #include <sys/param.h>
27 #include "remote-sim.h"
33 #define X(op, size) op*4+size
35 #define SP (h8300hmode ? SL:SW)
48 #define h8_opcodes ops
50 #include "opcode/h8300.h"
54 #define LOW_BYTE(x) ((x) & 0xff)
55 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
56 #define P(X,Y) ((X<<8) | Y)
58 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
61 c = (cpu.ccr >> 0) & 1;\
62 v = (cpu.ccr >> 1) & 1;\
63 nz = !((cpu.ccr >> 2) & 1);\
64 n = (cpu.ccr >> 3) & 1;
66 #ifdef __CHAR_IS_SIGNED__
67 #define SEXTCHAR(x) ((char)(x))
71 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
74 #define UEXTCHAR(x) ((x) & 0xff)
75 #define UEXTSHORT(x) ((x) & 0xffff)
76 #define SEXTSHORT(x) ((short)(x))
78 static cpu_state_type cpu;
113 return h8300hmode ? SL : SW;
126 return X (OP_IMM, SP);
128 return X (OP_REG, SP);
132 return X (OP_MEM, SP);
139 decode (addr, data, dst)
151 struct h8_opcode *q = h8_opcodes;
155 /* Find the exact opcode/arg combo */
159 unsigned int len = 0;
165 op_type looking_for = *nib;
166 int thisnib = data[len >> 1];
168 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
170 if (looking_for < 16 && looking_for >= 0)
172 if (looking_for != thisnib)
177 if ((int) looking_for & (int) B31)
179 if (!(((int) thisnib & 0x8) != 0))
181 looking_for = (op_type) ((int) looking_for & ~(int)
185 if ((int) looking_for & (int) B30)
187 if (!(((int) thisnib & 0x8) == 0))
189 looking_for = (op_type) ((int) looking_for & ~(int) B30);
191 if (looking_for & DBIT)
193 if ((looking_for & 5) != (thisnib & 5))
195 abs = (thisnib & 0x8) ? 2 : 1;
197 else if (looking_for & (REG | IND | INC | DEC))
199 if (looking_for & REG)
202 * Can work out size from the
205 size = bitfrom (looking_for);
207 if (looking_for & SRC)
216 else if (looking_for & L_16)
218 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
220 if (looking_for & (PCREL | DISP))
225 else if (looking_for & ABSJMP)
232 else if (looking_for & MEMIND)
236 else if (looking_for & L_32)
239 abs = (data[i] << 24)
240 | (data[i + 1] << 16)
246 else if (looking_for & L_24)
249 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
252 else if (looking_for & IGNORE)
256 else if (looking_for & DISPREG)
258 rdisp = thisnib & 0x7;
260 else if (looking_for & KBIT)
275 else if (looking_for & L_8)
279 if (looking_for & PCREL)
281 abs = SEXTCHAR (data[len >> 1]);
285 abs = data[len >> 1] & 0xff;
288 else if (looking_for & L_3)
294 else if (looking_for == E)
298 /* Fill in the args */
300 op_type *args = q->args.nib;
306 int rn = (x & DST) ? rd : rs;
318 if (x & (IMM | KBIT | DBIT))
320 p->type = X (OP_IMM, size);
325 /* Reset the size, some
326 ops (like mul) have two sizes */
329 p->type = X (OP_REG, size);
334 p->type = X (OP_INC, size);
339 p->type = X (OP_DEC, size);
344 p->type = X (OP_DISP, size);
348 else if (x & (ABS | ABSJMP | ABSMOV))
350 p->type = X (OP_DISP, size);
356 p->type = X (OP_MEM, size);
361 p->type = X (OP_PCREL, size);
362 p->literal = abs + addr + 2;
368 p->type = X (OP_IMM, SP);
373 p->type = X (OP_DISP, size);
375 p->reg = rdisp & 0x7;
382 printf ("Hmmmm %x", x);
389 * But a jmp or a jsr gets
390 * automagically lvalued, since we
391 * branch to their address not their
394 if (q->how == O (O_JSR, SB)
395 || q->how == O (O_JMP, SB))
397 dst->src.type = lvalue (dst->src.type, dst->src.reg);
400 if (dst->dst.type == -1)
403 dst->opcode = q->how;
404 dst->cycles = q->time;
406 /* And a jsr to 0xc4 is turned into a magic trap */
408 if (dst->opcode == O (O_JSR, SB))
410 if (dst->src.literal == 0xc4)
412 dst->opcode = O (O_SYSCALL, SB);
416 dst->next_pc = addr + len / 2;
421 printf ("Dont understand %x \n", looking_for);
433 dst->opcode = O (O_ILL, SB);
442 /* find the next cache entry to use */
444 idx = cpu.cache_top + 1;
446 if (idx >= cpu.csize)
452 /* Throw away its old meaning */
453 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
455 /* set to new address */
456 cpu.cache[idx].oldpc = pc;
458 /* fill in instruction info */
459 decode (pc, cpu.memory + pc, cpu.cache + idx);
461 /* point to new cache entry */
462 cpu.cache_idx[pc] = idx;
466 static unsigned char *breg[18];
467 static unsigned short *wreg[18];
468 static unsigned int *lreg[18];
470 #define GET_B_REG(x) *(breg[x])
471 #define SET_B_REG(x,y) (*(breg[x])) = (y)
472 #define GET_W_REG(x) *(wreg[x])
473 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
475 #define GET_L_REG(x) *(lreg[x])
476 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
478 #define GET_MEMORY_L(x) \
479 ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3])
481 #define GET_MEMORY_W(x) \
482 ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0))
485 #define SET_MEMORY_B(x,y) \
486 (cpu.memory[(x)] = y)
488 #define SET_MEMORY_W(x,y) \
489 {register unsigned char *_p = cpu.memory+x;\
490 register int __y = y;\
494 #define SET_MEMORY_L(x,y) \
495 {register unsigned char *_p = cpu.memory+x;register int __y = y;\
496 _p[0] = (__y)>>24; _p[1] = (__y)>>16; _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
498 #define GET_MEMORY_B(x) (cpu.memory[x])
505 int abs = arg->literal;
512 return GET_B_REG (rn);
514 return GET_W_REG (rn);
516 return GET_L_REG (rn);
527 r = GET_MEMORY_B (t);
536 r = GET_MEMORY_W (t);
544 r = GET_MEMORY_L (t);
551 case X (OP_DISP, SB):
552 t = GET_L_REG (rn) + abs;
554 return GET_MEMORY_B (t);
556 case X (OP_DISP, SW):
557 t = GET_L_REG (rn) + abs;
559 return GET_MEMORY_W (t);
561 case X (OP_DISP, SL):
562 t = GET_L_REG (rn) + abs;
564 return GET_MEMORY_L (t);
567 t = GET_MEMORY_L (abs);
585 int abs = arg->literal;
601 t = GET_L_REG (rn) - 1;
608 t = (GET_L_REG (rn) - 2) & cpu.mask;
614 t = (GET_L_REG (rn) - 4) & cpu.mask;
619 case X (OP_DISP, SB):
620 t = GET_L_REG (rn) + abs;
625 case X (OP_DISP, SW):
626 t = GET_L_REG (rn) + abs;
631 case X (OP_DISP, SL):
632 t = GET_L_REG (rn) + abs;
668 cpu.memory = (unsigned char *) calloc (sizeof (char), MSIZE);
669 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), MSIZE);
671 cpu.mask = (1 << MPOWER) - 1;
672 for (i = 0; i < 9; i++)
677 for (i = 0; i < 8; i++)
679 unsigned char *p = (unsigned char *) (cpu.regs + i);
680 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
681 unsigned short *q = (unsigned short *) (cpu.regs + i);
682 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
683 cpu.regs[i] = 0x00112233;
709 lreg[i] = &cpu.regs[i];
712 lreg[8] = &cpu.regs[8];
714 /* initialize the seg registers */
721 control_c (sig, code, scp, addr)
727 cpu.exception = SIGINT;
736 mop (code, bsize, sign)
749 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
750 SEXTSHORT (GET_W_REG (code->dst.reg));
752 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
753 SEXTSHORT (GET_W_REG (code->src.reg));
757 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
758 UEXTSHORT (GET_W_REG (code->dst.reg));
760 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
761 UEXTSHORT (GET_W_REG (code->src.reg));
764 result = multiplier * multiplicand;
768 n = result & (bsize ? 0x8000 : 0x80000000);
769 nz = result & (bsize ? 0xffff : 0xffffffff);
773 SET_W_REG (code->dst.reg, result);
777 SET_L_REG (code->dst.reg, result);
779 /* return ((n==1) << 1) | (nz==1); */
783 #define OSHIFTS(name, how) \
788 rd = GET_B_REG (code->src.reg); \
796 rd = GET_W_REG (code->src.reg); \
803 int hm = 0x80000000; \
804 rd = GET_L_REG (code->src.reg); \
809 #define OBITOP(name,f, s, op) \
814 if (f) ea = fetch (&code->dst); \
815 m=1<< fetch(&code->src); \
817 if(s) store (&code->dst,ea); goto next; \
821 sim_resume (step, siggnal)
826 int tick_start = get_now ();
839 prev = signal (SIGINT, control_c);
843 cpu.exception = SIGTRAP;
862 cidx = cpu.cache_idx[pc];
863 code = cpu.cache + cidx;
866 #define ALUOP(STORE, NAME, HOW) \
867 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
868 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
869 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
872 #define LOGOP(NAME, HOW) \
873 case O(NAME,SB): HOW; goto log8;\
874 case O(NAME, SW): HOW; goto log16;\
875 case O(NAME,SL): HOW; goto log32;
882 printf ("%x %d %s\n", pc, code->opcode,
883 code->op ? code->op->name : "**");
885 cpu.stats[code->opcode]++;
889 cycles += code->cycles;
891 switch (code->opcode)
895 * This opcode is a fake for when we get to an
896 * instruction which hasnt been compiled
904 rd = fetch (&code->dst);
905 ea = fetch (&code->src);
911 rd = fetch (&code->dst);
912 ea = fetch (&code->src);
917 #define EA ea = fetch(&code->src);
918 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
920 ALUOP (1, O_SUB, RD_EA;
929 rd = GET_B_REG (code->dst.reg);
930 ea = fetch (&code->src);
934 rd = GET_W_REG (code->dst.reg);
935 ea = fetch (&code->src);
939 rd = GET_L_REG (code->dst.reg);
940 ea = fetch (&code->src);
955 case O (O_MOV_TO_MEM, SB):
956 res = GET_B_REG (code->src.reg);
958 case O (O_MOV_TO_MEM, SW):
959 res = GET_W_REG (code->src.reg);
961 case O (O_MOV_TO_MEM, SL):
962 res = GET_L_REG (code->src.reg);
966 case O (O_MOV_TO_REG, SB):
967 res = fetch (&code->src);
968 SET_B_REG (code->dst.reg, res);
969 goto just_flags_log8;
970 case O (O_MOV_TO_REG, SW):
971 res = fetch (&code->src);
972 SET_W_REG (code->dst.reg, res);
973 goto just_flags_log16;
974 case O (O_MOV_TO_REG, SL):
975 res = fetch (&code->src);
976 SET_L_REG (code->dst.reg, res);
977 goto just_flags_log32;
981 SET_L_REG (code->dst.reg,
982 GET_L_REG (code->dst.reg)
983 + code->src.literal);
988 SET_L_REG (code->dst.reg,
989 GET_L_REG (code->dst.reg)
990 - code->src.literal);
994 rd = fetch (&code->dst);
995 ea = fetch (&code->src);
998 goto just_flags_alu8;
1001 rd = fetch (&code->dst);
1002 ea = fetch (&code->src);
1005 goto just_flags_alu16;
1008 rd = fetch (&code->dst);
1009 ea = fetch (&code->src);
1012 goto just_flags_alu32;
1016 rd = GET_B_REG (code->src.reg);
1019 SET_B_REG (code->src.reg, res);
1020 goto just_flags_inc8;
1023 rd = GET_W_REG (code->dst.reg);
1024 ea = -code->src.literal;
1026 SET_W_REG (code->dst.reg, res);
1027 goto just_flags_inc16;
1030 rd = GET_L_REG (code->dst.reg);
1031 ea = -code->src.literal;
1033 SET_L_REG (code->dst.reg, res);
1034 goto just_flags_inc32;
1038 rd = GET_B_REG (code->src.reg);
1041 SET_B_REG (code->src.reg, res);
1042 goto just_flags_inc8;
1045 rd = GET_W_REG (code->dst.reg);
1046 ea = code->src.literal;
1048 SET_W_REG (code->dst.reg, res);
1049 goto just_flags_inc16;
1052 rd = GET_L_REG (code->dst.reg);
1053 ea = code->src.literal;
1055 SET_L_REG (code->dst.reg, res);
1056 goto just_flags_inc32;
1059 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1061 case O (O_ANDC, SB):
1063 ea = code->src.literal;
1069 ea = code->src.literal;
1073 case O (O_XORC, SB):
1075 ea = code->src.literal;
1116 if (((Z || (N ^ V)) == 0))
1122 if (((Z || (N ^ V)) == 1))
1156 case O (O_SYSCALL, SB):
1157 printf ("%c", cpu.regs[2]);
1160 OSHIFTS (O_NOT, rd = ~rd);
1161 OSHIFTS (O_SHLL, c = rd & hm;
1163 OSHIFTS (O_SHLR, c = rd & 1;
1164 rd = (unsigned int) rd >> 1);
1165 OSHIFTS (O_SHAL, c = rd & hm;
1167 OSHIFTS (O_SHAR, t = rd & hm;
1172 OSHIFTS (O_ROTL, c = rd & hm;
1175 OSHIFTS (O_ROTR, c = rd & 1;
1176 rd = (unsigned int) rd >> 1;
1178 OSHIFTS (O_ROTXL, t = rd & hm;
1183 OSHIFTS (O_ROTXR, t = rd & 1;
1184 rd = (unsigned int) rd >> 1;
1185 if (C) rd |= hm; c = t;);
1189 pc = fetch (&code->src);
1197 pc = fetch (&code->src);
1204 SET_MEMORY_L (tmp, code->next_pc);
1209 SET_MEMORY_W (tmp, code->next_pc);
1216 pc = code->src.literal;
1227 pc = GET_MEMORY_L (tmp);
1232 pc = GET_MEMORY_W (tmp);
1241 cpu.exception = SIGILL;
1243 case O (O_SLEEP, SB):
1245 cpu.exception = SIGTRAP;
1248 OBITOP (O_BNOT, 1, 1, ea ^= m);
1249 OBITOP (O_BTST, 1, 0, nz = ea & m);
1250 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1251 OBITOP (O_BSET, 1, 1, ea |= m);
1252 OBITOP (O_BLD, 1, 0, c = ea & m);
1253 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1254 OBITOP (O_BST, 1, 1, ea &= ~m;
1256 OBITOP (O_BIST, 1, 1, ea &= ~m;
1258 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1259 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1260 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1261 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1262 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1263 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1266 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1268 case O (O_MULS, SB):
1271 case O (O_MULS, SW):
1274 case O (O_MULU, SB):
1277 case O (O_MULU, SW):
1282 case O (O_DIVU, SB):
1284 rd = GET_W_REG (code->dst.reg);
1285 ea = GET_B_REG (code->src.reg);
1291 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1297 case O (O_DIVU, SW):
1299 rd = GET_L_REG (code->dst.reg);
1300 ea = GET_W_REG (code->src.reg);
1308 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1312 case O (O_DIVS, SB):
1315 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1316 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1319 tmp = (int) rd % (int) ea;
1320 rd = (int) rd / (int) ea;
1326 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1329 case O (O_DIVS, SW):
1331 rd = GET_L_REG (code->dst.reg);
1332 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1335 tmp = (int) rd % (int) ea;
1336 rd = (int) rd / (int) ea;
1337 n = rd & 0x80000000;
1342 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1345 case O (O_EXTS, SW):
1346 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1347 ea = rd & 0x80 ? -256 : 0;
1350 case O (O_EXTS, SL):
1351 rd = GET_W_REG (code->src.reg) & 0xffff;
1352 ea = rd & 0x8000 ? -65536 : 0;
1355 case O (O_EXTU, SW):
1356 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1360 case O (O_EXTU, SL):
1361 rd = GET_W_REG (code->src.reg) & 0xffff;
1370 cpu.exception = SIGILL;
1382 /* When a branch works */
1383 pc = code->src.literal;
1386 /* Set the cond codes from res */
1389 /* Set the flags after an 8 bit inc/dec operation */
1393 v = (rd & 0x7f) == 0x7f;
1397 /* Set the flags after an 16 bit inc/dec operation */
1401 v = (rd & 0x7fff) == 0x7fff;
1405 /* Set the flags after an 32 bit inc/dec operation */
1407 n = res & 0x80000000;
1408 nz = res & 0xffffffff;
1409 v = (rd & 0x7fffffff) == 0x7fffffff;
1414 /* Set flags after an 8 bit shift op, carry set in insn */
1418 SET_B_REG (code->src.reg, rd);
1423 /* Set flags after an 16 bit shift op, carry set in insn */
1428 SET_W_REG (code->src.reg, rd);
1432 /* Set flags after an 32 bit shift op, carry set in insn */
1433 n = (rd & 0x80000000);
1435 nz = rd & 0xffffffff;
1436 SET_L_REG (code->src.reg, rd);
1440 store (&code->dst, res);
1442 /* flags after a 32bit logical operation */
1443 n = res & 0x80000000;
1444 nz = res & 0xffffffff;
1449 store (&code->dst, res);
1451 /* flags after a 16bit logical operation */
1459 store (&code->dst, res);
1467 SET_B_REG (code->dst.reg, res);
1471 v = ((ea & 0x80) == (rd & 0x80)) && ((ea & 0x80) != (res & 0x80));
1476 SET_W_REG (code->dst.reg, res);
1480 v = ((ea & 0x8000) == (rd & 0x8000)) && ((ea & 0x8000) != (res & 0x8000));
1481 c = (res & 0x10000);
1485 SET_L_REG (code->dst.reg, res);
1487 n = res & 0x80000000;
1488 nz = res & 0xffffffff;
1489 v = ((ea & 0x80000000) == (rd & 0x80000000))
1490 && ((ea & 0x80000000) != (res & 0x80000000));
1491 switch (code->opcode / 4)
1494 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1498 c = (unsigned) rd < (unsigned) -ea;
1511 /* if (cpu.regs[8] ) abort(); */
1514 /* Poll after every 100th insn, */
1515 if (poll_count++ > 100)
1518 if (win32pollquit())
1524 #if defined(__GO32__)
1525 /* Poll after every 100th insn, */
1526 if (poll_count++ > 100)
1538 while (!cpu.exception);
1539 cpu.ticks += get_now () - tick_start;
1540 cpu.cycles += cycles;
1546 signal (SIGINT, prev);
1551 sim_write (addr, buffer, size)
1553 unsigned char *buffer;
1559 if (addr < 0 || addr + size > MSIZE)
1561 for (i = 0; i < size; i++)
1563 cpu.memory[addr + i] = buffer[i];
1564 cpu.cache_idx[addr + i] = 0;
1570 sim_read (addr, buffer, size)
1572 unsigned char *buffer;
1576 if (addr < 0 || addr + size > MSIZE)
1578 memcpy (buffer, cpu.memory + addr, size);
1592 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1593 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1596 #define CCR_REGNUM 8 /* Contains processor status */
1597 #define PC_REGNUM 9 /* Contains program counter */
1599 #define CYCLE_REGNUM 10
1600 #define INST_REGNUM 11
1601 #define TICK_REGNUM 12
1605 sim_store_register (rn, value)
1607 unsigned char *value;
1612 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1613 shortval = (value[0] << 8) | (value[1]);
1614 intval = h8300hmode ? longval : shortval;
1632 cpu.regs[rn] = intval;
1638 cpu.cycles = longval;
1642 cpu.insts = longval;
1646 cpu.ticks = longval;
1652 sim_fetch_register (rn, buf)
1694 if (h8300hmode || longreg)
1709 sim_stop_reason (reason, sigrc)
1710 enum sim_stop *reason;
1713 *reason = sim_stopped;
1714 *sigrc = cpu.exception;
1723 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1724 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1733 double timetaken = (double) cpu.ticks / (double) now_persec ();
1734 double virttime = cpu.cycles / 10.0e6;
1736 printf_filtered ("\n\n#instructions executed %10d\n", cpu.insts);
1737 printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles);
1738 printf_filtered ("#real time taken %10.4f\n", timetaken);
1739 printf_filtered ("#virtual time taked %10.4f\n", virttime);
1740 if (timetaken != 0.0)
1741 printf_filtered ("#simulation ratio %10.4f\n", virttime / timetaken);
1742 printf_filtered ("#compiles %10d\n", cpu.compiles);
1743 printf_filtered ("#cache size %10d\n", cpu.csize);
1749 for (i = 0; i < O_LAST; i++)
1752 printf_filtered ("%d: %d\n", i, cpu.stats[i]);
1758 /* Indicate whether the cpu is an h8/300 or h8/300h.
1759 FLAG is non-zero for the h8/300h. */
1782 sim_close (quitting)
1788 /* Called by gdb to load a program into memory. */
1791 sim_load (prog, from_tty)
1797 /* See if the file is for the h8/300 or h8/300h. */
1798 /* ??? This may not be the most efficient way. The z8k simulator
1799 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
1800 if ((abfd = bfd_openr (prog, "coff-h8300")) != 0)
1802 if (bfd_check_format (abfd, bfd_object))
1803 set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h);
1807 /* Return non-zero so gdb will handle it. */
1812 sim_create_inferior (start_address, argv, env)
1813 SIM_ADDR start_address;
1817 cpu.pc = start_address;