2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
36 #include "remote-sim.h"
44 host_callback *sim_callback;
46 static SIM_OPEN_KIND sim_kind;
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
53 void sim_set_simcache_size PARAMS ((int));
55 #define X(op, size) op*4+size
57 #define SP (h8300hmode ? SL:SW)
70 #define h8_opcodes ops
72 #include "opcode/h8300.h"
76 /* The rate at which to call the host's poll_quit callback. */
78 #define POLL_QUIT_INTERVAL 0x80000
80 #define LOW_BYTE(x) ((x) & 0xff)
81 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
82 #define P(X,Y) ((X<<8) | Y)
84 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
87 c = (cpu.ccr >> 0) & 1;\
88 v = (cpu.ccr >> 1) & 1;\
89 nz = !((cpu.ccr >> 2) & 1);\
90 n = (cpu.ccr >> 3) & 1;
92 #ifdef __CHAR_IS_SIGNED__
93 #define SEXTCHAR(x) ((char)(x))
97 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
100 #define UEXTCHAR(x) ((x) & 0xff)
101 #define UEXTSHORT(x) ((x) & 0xffff)
102 #define SEXTSHORT(x) ((short)(x))
104 static cpu_state_type cpu;
109 static int memory_size;
138 return h8300hmode ? SL : SW;
150 return X (OP_IMM, SP);
152 return X (OP_REG, SP);
155 return X (OP_MEM, SP);
163 decode (addr, data, dst)
181 /* Find the exact opcode/arg combo. */
182 for (q = h8_opcodes; q->name; q++)
184 op_type *nib = q->data.nib;
185 unsigned int len = 0;
189 op_type looking_for = *nib;
190 int thisnib = data[len >> 1];
192 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
194 if (looking_for < 16 && looking_for >= 0)
196 if (looking_for != thisnib)
201 if ((int) looking_for & (int) B31)
203 if (!(((int) thisnib & 0x8) != 0))
206 looking_for = (op_type) ((int) looking_for & ~(int) B31);
210 if ((int) looking_for & (int) B30)
212 if (!(((int) thisnib & 0x8) == 0))
215 looking_for = (op_type) ((int) looking_for & ~(int) B30);
218 if (looking_for & DBIT)
220 /* Exclude adds/subs by looking at bit 0 and 2, and
221 make sure the operand size, either w or l,
222 matches by looking at bit 1. */
223 if ((looking_for & 7) != (thisnib & 7))
226 abs = (thisnib & 0x8) ? 2 : 1;
228 else if (looking_for & (REG | IND | INC | DEC))
230 if (looking_for & REG)
232 /* Can work out size from the register. */
233 size = bitfrom (looking_for);
235 if (looking_for & SRC)
240 else if (looking_for & L_16)
242 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
244 if (looking_for & (PCREL | DISP))
249 else if (looking_for & ABSJMP)
251 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
253 else if (looking_for & MEMIND)
257 else if (looking_for & L_32)
261 abs = (data[i] << 24)
262 | (data[i + 1] << 16)
268 else if (looking_for & L_24)
272 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
275 else if (looking_for & IGNORE)
279 else if (looking_for & DISPREG)
281 rdisp = thisnib & 0x7;
283 else if (looking_for & KBIT)
300 else if (looking_for & L_8)
304 if (looking_for & PCREL)
306 abs = SEXTCHAR (data[len >> 1]);
308 else if (looking_for & ABS8MEM)
311 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
312 abs |= data[len >> 1] & 0xff;
316 abs = data[len >> 1] & 0xff;
319 else if (looking_for & L_3)
325 else if (looking_for == E)
329 /* Fill in the args. */
331 op_type *args = q->args.nib;
337 int rn = (x & DST) ? rd : rs;
347 p->type = X (OP_IMM, size);
350 else if (x & (IMM | KBIT | DBIT))
352 p->type = X (OP_IMM, size);
358 Some ops (like mul) have two sizes. */
361 p->type = X (OP_REG, size);
366 p->type = X (OP_INC, size);
371 p->type = X (OP_DEC, size);
376 p->type = X (OP_DISP, size);
380 else if (x & (ABS | ABSJMP | ABS8MEM))
382 p->type = X (OP_DISP, size);
388 p->type = X (OP_MEM, size);
393 p->type = X (OP_PCREL, size);
394 p->literal = abs + addr + 2;
400 p->type = X (OP_IMM, SP);
405 p->type = X (OP_DISP, size);
407 p->reg = rdisp & 0x7;
414 printf ("Hmmmm %x", x);
420 /* But a jmp or a jsr gets automagically lvalued,
421 since we branch to their address not their
423 if (q->how == O (O_JSR, SB)
424 || q->how == O (O_JMP, SB))
426 dst->src.type = lvalue (dst->src.type, dst->src.reg);
429 if (dst->dst.type == -1)
432 dst->opcode = q->how;
433 dst->cycles = q->time;
435 /* And a jsr to 0xc4 is turned into a magic trap. */
437 if (dst->opcode == O (O_JSR, SB))
439 if (dst->src.literal == 0xc4)
441 dst->opcode = O (O_SYSCALL, SB);
445 dst->next_pc = addr + len / 2;
449 printf ("Don't understand %x \n", looking_for);
460 /* Fell off the end. */
461 dst->opcode = O (O_ILL, SB);
469 /* find the next cache entry to use */
471 idx = cpu.cache_top + 1;
473 if (idx >= cpu.csize)
479 /* Throw away its old meaning */
480 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
482 /* set to new address */
483 cpu.cache[idx].oldpc = pc;
485 /* fill in instruction info */
486 decode (pc, cpu.memory + pc, cpu.cache + idx);
488 /* point to new cache entry */
489 cpu.cache_idx[pc] = idx;
493 static unsigned char *breg[18];
494 static unsigned short *wreg[18];
495 static unsigned int *lreg[18];
497 #define GET_B_REG(x) *(breg[x])
498 #define SET_B_REG(x,y) (*(breg[x])) = (y)
499 #define GET_W_REG(x) *(wreg[x])
500 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
502 #define GET_L_REG(x) *(lreg[x])
503 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
505 #define GET_MEMORY_L(x) \
507 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
508 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
509 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
510 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
512 #define GET_MEMORY_W(x) \
514 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
515 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
518 #define GET_MEMORY_B(x) \
519 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
521 #define SET_MEMORY_L(x,y) \
522 { register unsigned char *_p; register int __y = y; \
523 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
524 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
525 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
527 #define SET_MEMORY_W(x,y) \
528 { register unsigned char *_p; register int __y = y; \
529 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
530 _p[0] = (__y)>>8; _p[1] =(__y);}
532 #define SET_MEMORY_B(x,y) \
533 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
540 int abs = arg->literal;
547 return GET_B_REG (rn);
549 return GET_W_REG (rn);
551 return GET_L_REG (rn);
562 r = GET_MEMORY_B (t);
571 r = GET_MEMORY_W (t);
579 r = GET_MEMORY_L (t);
586 case X (OP_DISP, SB):
587 t = GET_L_REG (rn) + abs;
589 return GET_MEMORY_B (t);
591 case X (OP_DISP, SW):
592 t = GET_L_REG (rn) + abs;
594 return GET_MEMORY_W (t);
596 case X (OP_DISP, SL):
597 t = GET_L_REG (rn) + abs;
599 return GET_MEMORY_L (t);
602 t = GET_MEMORY_L (abs);
607 t = GET_MEMORY_W (abs);
625 int abs = arg->literal;
641 t = GET_L_REG (rn) - 1;
648 t = (GET_L_REG (rn) - 2) & cpu.mask;
654 t = (GET_L_REG (rn) - 4) & cpu.mask;
659 case X (OP_DISP, SB):
660 t = GET_L_REG (rn) + abs;
665 case X (OP_DISP, SW):
666 t = GET_L_REG (rn) + abs;
671 case X (OP_DISP, SL):
672 t = GET_L_REG (rn) + abs;
709 memory_size = H8300H_MSIZE;
711 memory_size = H8300_MSIZE;
712 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
713 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
714 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
716 /* `msize' must be a power of two */
717 if ((memory_size & (memory_size - 1)) != 0)
719 cpu.mask = memory_size - 1;
721 for (i = 0; i < 9; i++)
726 for (i = 0; i < 8; i++)
728 unsigned char *p = (unsigned char *) (cpu.regs + i);
729 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
730 unsigned short *q = (unsigned short *) (cpu.regs + i);
731 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
732 cpu.regs[i] = 0x00112233;
758 lreg[i] = &cpu.regs[i];
761 lreg[8] = &cpu.regs[8];
763 /* initialize the seg registers */
765 sim_set_simcache_size (CSIZE);
770 control_c (sig, code, scp, addr)
776 cpu.state = SIM_STATE_STOPPED;
777 cpu.exception = SIGINT;
786 mop (code, bsize, sign)
799 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
800 SEXTSHORT (GET_W_REG (code->dst.reg));
802 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
803 SEXTSHORT (GET_W_REG (code->src.reg));
807 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
808 UEXTSHORT (GET_W_REG (code->dst.reg));
810 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
811 UEXTSHORT (GET_W_REG (code->src.reg));
814 result = multiplier * multiplicand;
818 n = result & (bsize ? 0x8000 : 0x80000000);
819 nz = result & (bsize ? 0xffff : 0xffffffff);
823 SET_W_REG (code->dst.reg, result);
827 SET_L_REG (code->dst.reg, result);
829 /* return ((n==1) << 1) | (nz==1); */
833 #define ONOT(name, how) \
838 rd = GET_B_REG (code->src.reg); \
846 rd = GET_W_REG (code->src.reg); \
853 int hm = 0x80000000; \
854 rd = GET_L_REG (code->src.reg); \
859 #define OSHIFTS(name, how1, how2) \
864 rd = GET_B_REG (code->src.reg); \
865 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
879 rd = GET_W_REG (code->src.reg); \
880 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
893 int hm = 0x80000000; \
894 rd = GET_L_REG (code->src.reg); \
895 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
906 #define OBITOP(name,f, s, op) \
911 if (f) ea = fetch (&code->dst); \
912 m=1<< fetch(&code->src); \
914 if(s) store (&code->dst,ea); goto next; \
921 cpu.state = SIM_STATE_STOPPED;
922 cpu.exception = SIGINT;
927 sim_resume (sd, step, siggnal)
933 int tick_start = get_now ();
946 prev = signal (SIGINT, control_c);
950 cpu.state = SIM_STATE_STOPPED;
951 cpu.exception = SIGTRAP;
955 cpu.state = SIM_STATE_RUNNING;
961 /* The PC should never be odd. */
975 cidx = cpu.cache_idx[pc];
976 code = cpu.cache + cidx;
979 #define ALUOP(STORE, NAME, HOW) \
980 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
981 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
982 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
985 #define LOGOP(NAME, HOW) \
986 case O(NAME,SB): HOW; goto log8;\
987 case O(NAME, SW): HOW; goto log16;\
988 case O(NAME,SL): HOW; goto log32;
995 printf ("%x %d %s\n", pc, code->opcode,
996 code->op ? code->op->name : "**");
998 cpu.stats[code->opcode]++;
1002 cycles += code->cycles;
1004 switch (code->opcode)
1008 * This opcode is a fake for when we get to an
1009 * instruction which hasnt been compiled
1016 case O (O_SUBX, SB):
1017 rd = fetch (&code->dst);
1018 ea = fetch (&code->src);
1023 case O (O_ADDX, SB):
1024 rd = fetch (&code->dst);
1025 ea = fetch (&code->src);
1030 #define EA ea = fetch(&code->src);
1031 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1033 ALUOP (1, O_SUB, RD_EA;
1036 ALUOP (1, O_NEG, EA;
1042 rd = GET_B_REG (code->dst.reg);
1043 ea = fetch (&code->src);
1047 rd = GET_W_REG (code->dst.reg);
1048 ea = fetch (&code->src);
1052 rd = GET_L_REG (code->dst.reg);
1053 ea = fetch (&code->src);
1058 LOGOP (O_AND, RD_EA;
1064 LOGOP (O_XOR, RD_EA;
1068 case O (O_MOV_TO_MEM, SB):
1069 res = GET_B_REG (code->src.reg);
1071 case O (O_MOV_TO_MEM, SW):
1072 res = GET_W_REG (code->src.reg);
1074 case O (O_MOV_TO_MEM, SL):
1075 res = GET_L_REG (code->src.reg);
1079 case O (O_MOV_TO_REG, SB):
1080 res = fetch (&code->src);
1081 SET_B_REG (code->dst.reg, res);
1082 goto just_flags_log8;
1083 case O (O_MOV_TO_REG, SW):
1084 res = fetch (&code->src);
1085 SET_W_REG (code->dst.reg, res);
1086 goto just_flags_log16;
1087 case O (O_MOV_TO_REG, SL):
1088 res = fetch (&code->src);
1089 SET_L_REG (code->dst.reg, res);
1090 goto just_flags_log32;
1093 case O (O_ADDS, SL):
1094 SET_L_REG (code->dst.reg,
1095 GET_L_REG (code->dst.reg)
1096 + code->src.literal);
1100 case O (O_SUBS, SL):
1101 SET_L_REG (code->dst.reg,
1102 GET_L_REG (code->dst.reg)
1103 - code->src.literal);
1107 rd = fetch (&code->dst);
1108 ea = fetch (&code->src);
1111 goto just_flags_alu8;
1114 rd = fetch (&code->dst);
1115 ea = fetch (&code->src);
1118 goto just_flags_alu16;
1121 rd = fetch (&code->dst);
1122 ea = fetch (&code->src);
1125 goto just_flags_alu32;
1129 rd = GET_B_REG (code->src.reg);
1132 SET_B_REG (code->src.reg, res);
1133 goto just_flags_inc8;
1136 rd = GET_W_REG (code->dst.reg);
1137 ea = -code->src.literal;
1139 SET_W_REG (code->dst.reg, res);
1140 goto just_flags_inc16;
1143 rd = GET_L_REG (code->dst.reg);
1144 ea = -code->src.literal;
1146 SET_L_REG (code->dst.reg, res);
1147 goto just_flags_inc32;
1151 rd = GET_B_REG (code->src.reg);
1154 SET_B_REG (code->src.reg, res);
1155 goto just_flags_inc8;
1158 rd = GET_W_REG (code->dst.reg);
1159 ea = code->src.literal;
1161 SET_W_REG (code->dst.reg, res);
1162 goto just_flags_inc16;
1165 rd = GET_L_REG (code->dst.reg);
1166 ea = code->src.literal;
1168 SET_L_REG (code->dst.reg, res);
1169 goto just_flags_inc32;
1172 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1174 case O (O_ANDC, SB):
1176 ea = code->src.literal;
1182 ea = code->src.literal;
1186 case O (O_XORC, SB):
1188 ea = code->src.literal;
1229 if (((Z || (N ^ V)) == 0))
1235 if (((Z || (N ^ V)) == 1))
1269 case O (O_SYSCALL, SB):
1271 char c = cpu.regs[2];
1272 sim_callback->write_stdout (sim_callback, &c, 1);
1276 ONOT (O_NOT, rd = ~rd; v = 0;);
1278 c = rd & hm; v = 0; rd <<= 1,
1279 c = rd & (hm >> 1); v = 0; rd <<= 2);
1281 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1282 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1284 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1285 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1287 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1288 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1290 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1291 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1293 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1294 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1296 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1297 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1299 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1300 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1304 pc = fetch (&code->src);
1312 pc = fetch (&code->src);
1319 SET_MEMORY_L (tmp, code->next_pc);
1324 SET_MEMORY_W (tmp, code->next_pc);
1331 pc = code->src.literal;
1342 pc = GET_MEMORY_L (tmp);
1347 pc = GET_MEMORY_W (tmp);
1356 cpu.state = SIM_STATE_STOPPED;
1357 cpu.exception = SIGILL;
1359 case O (O_SLEEP, SN):
1360 /* FIXME: Doesn't this break for breakpoints when r0
1361 contains just the right (er, wrong) value? */
1362 cpu.state = SIM_STATE_STOPPED;
1363 /* The format of r0 is defined by target newlib. Expand
1364 the macros here instead of looking for .../sys/wait.h. */
1365 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1366 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1367 if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0]))
1368 cpu.exception = SIGILL;
1370 cpu.exception = SIGTRAP;
1373 cpu.state = SIM_STATE_STOPPED;
1374 cpu.exception = SIGTRAP;
1377 OBITOP (O_BNOT, 1, 1, ea ^= m);
1378 OBITOP (O_BTST, 1, 0, nz = ea & m);
1379 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1380 OBITOP (O_BSET, 1, 1, ea |= m);
1381 OBITOP (O_BLD, 1, 0, c = ea & m);
1382 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1383 OBITOP (O_BST, 1, 1, ea &= ~m;
1385 OBITOP (O_BIST, 1, 1, ea &= ~m;
1387 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1388 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1389 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1390 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1391 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1392 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1395 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1397 case O (O_MULS, SB):
1400 case O (O_MULS, SW):
1403 case O (O_MULU, SB):
1406 case O (O_MULU, SW):
1411 case O (O_DIVU, SB):
1413 rd = GET_W_REG (code->dst.reg);
1414 ea = GET_B_REG (code->src.reg);
1417 tmp = (unsigned)rd % ea;
1418 rd = (unsigned)rd / ea;
1420 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1426 case O (O_DIVU, SW):
1428 rd = GET_L_REG (code->dst.reg);
1429 ea = GET_W_REG (code->src.reg);
1434 tmp = (unsigned)rd % ea;
1435 rd = (unsigned)rd / ea;
1437 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1441 case O (O_DIVS, SB):
1444 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1445 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1448 tmp = (int) rd % (int) ea;
1449 rd = (int) rd / (int) ea;
1455 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1458 case O (O_DIVS, SW):
1460 rd = GET_L_REG (code->dst.reg);
1461 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1464 tmp = (int) rd % (int) ea;
1465 rd = (int) rd / (int) ea;
1466 n = rd & 0x80000000;
1471 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1474 case O (O_EXTS, SW):
1475 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1476 ea = rd & 0x80 ? -256 : 0;
1479 case O (O_EXTS, SL):
1480 rd = GET_W_REG (code->src.reg) & 0xffff;
1481 ea = rd & 0x8000 ? -65536 : 0;
1484 case O (O_EXTU, SW):
1485 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1489 case O (O_EXTU, SL):
1490 rd = GET_W_REG (code->src.reg) & 0xffff;
1500 int nregs, firstreg, i;
1502 nregs = GET_MEMORY_B (pc + 1);
1505 firstreg = GET_MEMORY_B (pc + 3);
1507 for (i = firstreg; i <= firstreg + nregs; i++)
1510 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1517 int nregs, firstreg, i;
1519 nregs = GET_MEMORY_B (pc + 1);
1522 firstreg = GET_MEMORY_B (pc + 3);
1524 for (i = firstreg; i >= firstreg - nregs; i--)
1526 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1533 cpu.state = SIM_STATE_STOPPED;
1534 cpu.exception = SIGILL;
1546 /* When a branch works */
1547 pc = code->src.literal;
1550 /* Set the cond codes from res */
1553 /* Set the flags after an 8 bit inc/dec operation */
1557 v = (rd & 0x7f) == 0x7f;
1561 /* Set the flags after an 16 bit inc/dec operation */
1565 v = (rd & 0x7fff) == 0x7fff;
1569 /* Set the flags after an 32 bit inc/dec operation */
1571 n = res & 0x80000000;
1572 nz = res & 0xffffffff;
1573 v = (rd & 0x7fffffff) == 0x7fffffff;
1578 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1581 SET_B_REG (code->src.reg, rd);
1585 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1588 SET_W_REG (code->src.reg, rd);
1592 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1593 n = (rd & 0x80000000);
1594 nz = rd & 0xffffffff;
1595 SET_L_REG (code->src.reg, rd);
1599 store (&code->dst, res);
1601 /* flags after a 32bit logical operation */
1602 n = res & 0x80000000;
1603 nz = res & 0xffffffff;
1608 store (&code->dst, res);
1610 /* flags after a 16bit logical operation */
1618 store (&code->dst, res);
1626 SET_B_REG (code->dst.reg, res);
1631 switch (code->opcode / 4)
1634 v = ((rd & 0x80) == (ea & 0x80)
1635 && (rd & 0x80) != (res & 0x80));
1639 v = ((rd & 0x80) != (-ea & 0x80)
1640 && (rd & 0x80) != (res & 0x80));
1649 SET_W_REG (code->dst.reg, res);
1653 c = (res & 0x10000);
1654 switch (code->opcode / 4)
1657 v = ((rd & 0x8000) == (ea & 0x8000)
1658 && (rd & 0x8000) != (res & 0x8000));
1662 v = ((rd & 0x8000) != (-ea & 0x8000)
1663 && (rd & 0x8000) != (res & 0x8000));
1672 SET_L_REG (code->dst.reg, res);
1674 n = res & 0x80000000;
1675 nz = res & 0xffffffff;
1676 switch (code->opcode / 4)
1679 v = ((rd & 0x80000000) == (ea & 0x80000000)
1680 && (rd & 0x80000000) != (res & 0x80000000));
1681 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1685 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1686 && (rd & 0x80000000) != (res & 0x80000000));
1687 c = (unsigned) rd < (unsigned) -ea;
1690 v = (rd == 0x80000000);
1701 /* if (cpu.regs[8] ) abort(); */
1703 if (--poll_count < 0)
1705 poll_count = POLL_QUIT_INTERVAL;
1706 if ((*sim_callback->poll_quit) != NULL
1707 && (*sim_callback->poll_quit) (sim_callback))
1712 while (cpu.state == SIM_STATE_RUNNING);
1713 cpu.ticks += get_now () - tick_start;
1714 cpu.cycles += cycles;
1720 signal (SIGINT, prev);
1727 /* FIXME: unfinished */
1732 sim_write (sd, addr, buffer, size)
1735 unsigned char *buffer;
1743 for (i = 0; i < size; i++)
1745 if (addr < memory_size)
1747 cpu.memory[addr + i] = buffer[i];
1748 cpu.cache_idx[addr + i] = 0;
1751 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1757 sim_read (sd, addr, buffer, size)
1760 unsigned char *buffer;
1766 if (addr < memory_size)
1767 memcpy (buffer, cpu.memory + addr, size);
1769 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1783 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1784 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1787 #define CCR_REGNUM 8 /* Contains processor status */
1788 #define PC_REGNUM 9 /* Contains program counter */
1790 #define CYCLE_REGNUM 10
1791 #define INST_REGNUM 11
1792 #define TICK_REGNUM 12
1796 sim_store_register (sd, rn, value, length)
1799 unsigned char *value;
1805 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1806 shortval = (value[0] << 8) | (value[1]);
1807 intval = h8300hmode ? longval : shortval;
1825 cpu.regs[rn] = intval;
1831 cpu.cycles = longval;
1835 cpu.insts = longval;
1839 cpu.ticks = longval;
1846 sim_fetch_register (sd, rn, buf, length)
1890 if (h8300hmode || longreg)
1906 sim_stop_reason (sd, reason, sigrc)
1908 enum sim_stop *reason;
1911 #if 0 /* FIXME: This should work but we can't use it.
1912 grep for SLEEP above. */
1915 case SIM_STATE_EXITED : *reason = sim_exited; break;
1916 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1917 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1921 *reason = sim_stopped;
1923 *sigrc = cpu.exception;
1926 /* FIXME: Rename to sim_set_mem_size. */
1932 /* Memory size is fixed. */
1936 sim_set_simcache_size (n)
1942 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1943 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1949 sim_info (sd, verbose)
1953 double timetaken = (double) cpu.ticks / (double) now_persec ();
1954 double virttime = cpu.cycles / 10.0e6;
1956 (*sim_callback->printf_filtered) (sim_callback,
1957 "\n\n#instructions executed %10d\n",
1959 (*sim_callback->printf_filtered) (sim_callback,
1960 "#cycles (v approximate) %10d\n",
1962 (*sim_callback->printf_filtered) (sim_callback,
1963 "#real time taken %10.4f\n",
1965 (*sim_callback->printf_filtered) (sim_callback,
1966 "#virtual time taked %10.4f\n",
1968 if (timetaken != 0.0)
1969 (*sim_callback->printf_filtered) (sim_callback,
1970 "#simulation ratio %10.4f\n",
1971 virttime / timetaken);
1972 (*sim_callback->printf_filtered) (sim_callback,
1975 (*sim_callback->printf_filtered) (sim_callback,
1976 "#cache size %10d\n",
1980 /* This to be conditional on `what' (aka `verbose'),
1981 however it was never passed as non-zero. */
1985 for (i = 0; i < O_LAST; i++)
1988 (*sim_callback->printf_filtered) (sim_callback,
1989 "%d: %d\n", i, cpu.stats[i]);
1995 /* Indicate whether the cpu is an h8/300 or h8/300h.
1996 FLAG is non-zero for the h8/300h. */
2002 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2003 This function being replaced by a sim_open:ARGV configuration
2009 sim_open (kind, ptr, abfd, argv)
2011 struct host_callback_struct *ptr;
2015 /* FIXME: Much of the code in sim_load can be moved here */
2020 /* fudge our descriptor */
2021 return (SIM_DESC) 1;
2025 sim_close (sd, quitting)
2032 /* Called by gdb to load a program into memory. */
2035 sim_load (sd, prog, abfd, from_tty)
2043 /* FIXME: The code below that sets a specific variant of the h8/300
2044 being simulated should be moved to sim_open(). */
2046 /* See if the file is for the h8/300 or h8/300h. */
2047 /* ??? This may not be the most efficient way. The z8k simulator
2048 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2052 prog_bfd = bfd_openr (prog, "coff-h8300");
2053 if (prog_bfd != NULL)
2055 /* Set the cpu type. We ignore failure from bfd_check_format
2056 and bfd_openr as sim_load_file checks too. */
2057 if (bfd_check_format (prog_bfd, bfd_object))
2059 unsigned long mach = bfd_get_mach (prog_bfd);
2060 set_h8300h (mach == bfd_mach_h8300h
2061 || mach == bfd_mach_h8300s);
2065 /* If we're using gdb attached to the simulator, then we have to
2066 reallocate memory for the simulator.
2068 When gdb first starts, it calls fetch_registers (among other
2069 functions), which in turn calls init_pointers, which allocates
2072 The problem is when we do that, we don't know whether we're
2073 debugging an h8/300 or h8/300h program.
2075 This is the first point at which we can make that determination,
2076 so we just reallocate memory now; this will also allow us to handle
2077 switching between h8/300 and h8/300h programs without exiting
2080 memory_size = H8300H_MSIZE;
2082 memory_size = H8300_MSIZE;
2087 free (cpu.cache_idx);
2089 free (cpu.eightbit);
2091 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2092 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2093 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2095 /* `msize' must be a power of two */
2096 if ((memory_size & (memory_size - 1)) != 0)
2098 cpu.mask = memory_size - 1;
2100 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2101 sim_kind == SIM_OPEN_DEBUG,
2105 /* Close the bfd if we opened it. */
2106 if (abfd == NULL && prog_bfd != NULL)
2107 bfd_close (prog_bfd);
2111 /* Close the bfd if we opened it. */
2112 if (abfd == NULL && prog_bfd != NULL)
2113 bfd_close (prog_bfd);
2118 sim_create_inferior (sd, abfd, argv, env)
2125 cpu.pc = bfd_get_start_address (abfd);
2132 sim_do_command (sd, cmd)
2136 (*sim_callback->printf_filtered) (sim_callback,
2137 "This simulator does not accept any commands.\n");
2141 sim_set_callbacks (ptr)
2142 struct host_callback_struct *ptr;