2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
29 #include <sys/param.h>
33 #include "remote-sim.h"
39 #define X(op, size) op*4+size
41 #define SP (h8300hmode ? SL:SW)
54 #define h8_opcodes ops
56 #include "opcode/h8300.h"
60 #define LOW_BYTE(x) ((x) & 0xff)
61 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
62 #define P(X,Y) ((X<<8) | Y)
64 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
67 c = (cpu.ccr >> 0) & 1;\
68 v = (cpu.ccr >> 1) & 1;\
69 nz = !((cpu.ccr >> 2) & 1);\
70 n = (cpu.ccr >> 3) & 1;
72 #ifdef __CHAR_IS_SIGNED__
73 #define SEXTCHAR(x) ((char)(x))
77 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
80 #define UEXTCHAR(x) ((x) & 0xff)
81 #define UEXTSHORT(x) ((x) & 0xffff)
82 #define SEXTSHORT(x) ((short)(x))
84 static cpu_state_type cpu;
88 static int memory_size;
119 return h8300hmode ? SL : SW;
132 return X (OP_IMM, SP);
134 return X (OP_REG, SP);
138 return X (OP_MEM, SP);
145 decode (addr, data, dst)
157 struct h8_opcode *q = h8_opcodes;
161 /* Find the exact opcode/arg combo */
165 unsigned int len = 0;
171 op_type looking_for = *nib;
172 int thisnib = data[len >> 1];
174 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
176 if (looking_for < 16 && looking_for >= 0)
178 if (looking_for != thisnib)
183 if ((int) looking_for & (int) B31)
185 if (!(((int) thisnib & 0x8) != 0))
187 looking_for = (op_type) ((int) looking_for & ~(int)
191 if ((int) looking_for & (int) B30)
193 if (!(((int) thisnib & 0x8) == 0))
195 looking_for = (op_type) ((int) looking_for & ~(int) B30);
197 if (looking_for & DBIT)
199 if ((looking_for & 5) != (thisnib & 5))
201 abs = (thisnib & 0x8) ? 2 : 1;
203 else if (looking_for & (REG | IND | INC | DEC))
205 if (looking_for & REG)
208 * Can work out size from the
211 size = bitfrom (looking_for);
213 if (looking_for & SRC)
222 else if (looking_for & L_16)
224 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
226 if (looking_for & (PCREL | DISP))
231 else if (looking_for & ABSJMP)
238 else if (looking_for & MEMIND)
242 else if (looking_for & L_32)
245 abs = (data[i] << 24)
246 | (data[i + 1] << 16)
252 else if (looking_for & L_24)
255 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
258 else if (looking_for & IGNORE)
262 else if (looking_for & DISPREG)
264 rdisp = thisnib & 0x7;
266 else if (looking_for & KBIT)
281 else if (looking_for & L_8)
285 if (looking_for & PCREL)
287 abs = SEXTCHAR (data[len >> 1]);
291 abs = data[len >> 1] & 0xff;
294 else if (looking_for & L_3)
300 else if (looking_for == E)
304 /* Fill in the args */
306 op_type *args = q->args.nib;
312 int rn = (x & DST) ? rd : rs;
324 if (x & (IMM | KBIT | DBIT))
326 p->type = X (OP_IMM, size);
331 /* Reset the size, some
332 ops (like mul) have two sizes */
335 p->type = X (OP_REG, size);
340 p->type = X (OP_INC, size);
345 p->type = X (OP_DEC, size);
350 p->type = X (OP_DISP, size);
354 else if (x & (ABS | ABSJMP | ABSMOV))
356 p->type = X (OP_DISP, size);
362 p->type = X (OP_MEM, size);
367 p->type = X (OP_PCREL, size);
368 p->literal = abs + addr + 2;
374 p->type = X (OP_IMM, SP);
379 p->type = X (OP_DISP, size);
381 p->reg = rdisp & 0x7;
388 printf ("Hmmmm %x", x);
395 * But a jmp or a jsr gets
396 * automagically lvalued, since we
397 * branch to their address not their
400 if (q->how == O (O_JSR, SB)
401 || q->how == O (O_JMP, SB))
403 dst->src.type = lvalue (dst->src.type, dst->src.reg);
406 if (dst->dst.type == -1)
409 dst->opcode = q->how;
410 dst->cycles = q->time;
412 /* And a jsr to 0xc4 is turned into a magic trap */
414 if (dst->opcode == O (O_JSR, SB))
416 if (dst->src.literal == 0xc4)
418 dst->opcode = O (O_SYSCALL, SB);
422 dst->next_pc = addr + len / 2;
427 printf ("Dont understand %x \n", looking_for);
439 dst->opcode = O (O_ILL, SB);
448 /* find the next cache entry to use */
450 idx = cpu.cache_top + 1;
452 if (idx >= cpu.csize)
458 /* Throw away its old meaning */
459 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
461 /* set to new address */
462 cpu.cache[idx].oldpc = pc;
464 /* fill in instruction info */
465 decode (pc, cpu.memory + pc, cpu.cache + idx);
467 /* point to new cache entry */
468 cpu.cache_idx[pc] = idx;
472 static unsigned char *breg[18];
473 static unsigned short *wreg[18];
474 static unsigned int *lreg[18];
476 #define GET_B_REG(x) *(breg[x])
477 #define SET_B_REG(x,y) (*(breg[x])) = (y)
478 #define GET_W_REG(x) *(wreg[x])
479 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
481 #define GET_L_REG(x) *(lreg[x])
482 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
484 #define GET_MEMORY_L(x) \
485 ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3])
487 #define GET_MEMORY_W(x) \
488 ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0))
491 #define SET_MEMORY_B(x,y) \
492 (cpu.memory[(x)] = y)
494 #define SET_MEMORY_W(x,y) \
495 {register unsigned char *_p = cpu.memory+x;\
496 register int __y = y;\
500 #define SET_MEMORY_L(x,y) \
501 {register unsigned char *_p = cpu.memory+x;register int __y = y;\
502 _p[0] = (__y)>>24; _p[1] = (__y)>>16; _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
504 #define GET_MEMORY_B(x) (cpu.memory[x])
511 int abs = arg->literal;
518 return GET_B_REG (rn);
520 return GET_W_REG (rn);
522 return GET_L_REG (rn);
533 r = GET_MEMORY_B (t);
542 r = GET_MEMORY_W (t);
550 r = GET_MEMORY_L (t);
557 case X (OP_DISP, SB):
558 t = GET_L_REG (rn) + abs;
560 return GET_MEMORY_B (t);
562 case X (OP_DISP, SW):
563 t = GET_L_REG (rn) + abs;
565 return GET_MEMORY_W (t);
567 case X (OP_DISP, SL):
568 t = GET_L_REG (rn) + abs;
570 return GET_MEMORY_L (t);
573 t = GET_MEMORY_L (abs);
591 int abs = arg->literal;
607 t = GET_L_REG (rn) - 1;
614 t = (GET_L_REG (rn) - 2) & cpu.mask;
620 t = (GET_L_REG (rn) - 4) & cpu.mask;
625 case X (OP_DISP, SB):
626 t = GET_L_REG (rn) + abs;
631 case X (OP_DISP, SW):
632 t = GET_L_REG (rn) + abs;
637 case X (OP_DISP, SL):
638 t = GET_L_REG (rn) + abs;
675 memory_size = H8300H_MSIZE;
677 memory_size = H8300_MSIZE;
678 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
679 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
681 /* `msize' must be a power of two */
682 if ((memory_size & (memory_size - 1)) != 0)
684 cpu.mask = memory_size - 1;
686 for (i = 0; i < 9; i++)
691 for (i = 0; i < 8; i++)
693 unsigned char *p = (unsigned char *) (cpu.regs + i);
694 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
695 unsigned short *q = (unsigned short *) (cpu.regs + i);
696 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
697 cpu.regs[i] = 0x00112233;
723 lreg[i] = &cpu.regs[i];
726 lreg[8] = &cpu.regs[8];
728 /* initialize the seg registers */
735 control_c (sig, code, scp, addr)
741 cpu.exception = SIGINT;
750 mop (code, bsize, sign)
763 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
764 SEXTSHORT (GET_W_REG (code->dst.reg));
766 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
767 SEXTSHORT (GET_W_REG (code->src.reg));
771 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
772 UEXTSHORT (GET_W_REG (code->dst.reg));
774 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
775 UEXTSHORT (GET_W_REG (code->src.reg));
778 result = multiplier * multiplicand;
782 n = result & (bsize ? 0x8000 : 0x80000000);
783 nz = result & (bsize ? 0xffff : 0xffffffff);
787 SET_W_REG (code->dst.reg, result);
791 SET_L_REG (code->dst.reg, result);
793 /* return ((n==1) << 1) | (nz==1); */
797 #define OSHIFTS(name, how) \
802 rd = GET_B_REG (code->src.reg); \
810 rd = GET_W_REG (code->src.reg); \
817 int hm = 0x80000000; \
818 rd = GET_L_REG (code->src.reg); \
823 #define OBITOP(name,f, s, op) \
828 if (f) ea = fetch (&code->dst); \
829 m=1<< fetch(&code->src); \
831 if(s) store (&code->dst,ea); goto next; \
835 sim_resume (step, siggnal)
840 int tick_start = get_now ();
853 prev = signal (SIGINT, control_c);
857 cpu.exception = SIGTRAP;
876 cidx = cpu.cache_idx[pc];
877 code = cpu.cache + cidx;
880 #define ALUOP(STORE, NAME, HOW) \
881 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
882 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
883 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
886 #define LOGOP(NAME, HOW) \
887 case O(NAME,SB): HOW; goto log8;\
888 case O(NAME, SW): HOW; goto log16;\
889 case O(NAME,SL): HOW; goto log32;
896 printf ("%x %d %s\n", pc, code->opcode,
897 code->op ? code->op->name : "**");
899 cpu.stats[code->opcode]++;
903 cycles += code->cycles;
905 switch (code->opcode)
909 * This opcode is a fake for when we get to an
910 * instruction which hasnt been compiled
918 rd = fetch (&code->dst);
919 ea = fetch (&code->src);
925 rd = fetch (&code->dst);
926 ea = fetch (&code->src);
931 #define EA ea = fetch(&code->src);
932 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
934 ALUOP (1, O_SUB, RD_EA;
943 rd = GET_B_REG (code->dst.reg);
944 ea = fetch (&code->src);
948 rd = GET_W_REG (code->dst.reg);
949 ea = fetch (&code->src);
953 rd = GET_L_REG (code->dst.reg);
954 ea = fetch (&code->src);
969 case O (O_MOV_TO_MEM, SB):
970 res = GET_B_REG (code->src.reg);
972 case O (O_MOV_TO_MEM, SW):
973 res = GET_W_REG (code->src.reg);
975 case O (O_MOV_TO_MEM, SL):
976 res = GET_L_REG (code->src.reg);
980 case O (O_MOV_TO_REG, SB):
981 res = fetch (&code->src);
982 SET_B_REG (code->dst.reg, res);
983 goto just_flags_log8;
984 case O (O_MOV_TO_REG, SW):
985 res = fetch (&code->src);
986 SET_W_REG (code->dst.reg, res);
987 goto just_flags_log16;
988 case O (O_MOV_TO_REG, SL):
989 res = fetch (&code->src);
990 SET_L_REG (code->dst.reg, res);
991 goto just_flags_log32;
995 SET_L_REG (code->dst.reg,
996 GET_L_REG (code->dst.reg)
997 + code->src.literal);
1001 case O (O_SUBS, SL):
1002 SET_L_REG (code->dst.reg,
1003 GET_L_REG (code->dst.reg)
1004 - code->src.literal);
1008 rd = fetch (&code->dst);
1009 ea = fetch (&code->src);
1012 goto just_flags_alu8;
1015 rd = fetch (&code->dst);
1016 ea = fetch (&code->src);
1019 goto just_flags_alu16;
1022 rd = fetch (&code->dst);
1023 ea = fetch (&code->src);
1026 goto just_flags_alu32;
1030 rd = GET_B_REG (code->src.reg);
1033 SET_B_REG (code->src.reg, res);
1034 goto just_flags_inc8;
1037 rd = GET_W_REG (code->dst.reg);
1038 ea = -code->src.literal;
1040 SET_W_REG (code->dst.reg, res);
1041 goto just_flags_inc16;
1044 rd = GET_L_REG (code->dst.reg);
1045 ea = -code->src.literal;
1047 SET_L_REG (code->dst.reg, res);
1048 goto just_flags_inc32;
1052 rd = GET_B_REG (code->src.reg);
1055 SET_B_REG (code->src.reg, res);
1056 goto just_flags_inc8;
1059 rd = GET_W_REG (code->dst.reg);
1060 ea = code->src.literal;
1062 SET_W_REG (code->dst.reg, res);
1063 goto just_flags_inc16;
1066 rd = GET_L_REG (code->dst.reg);
1067 ea = code->src.literal;
1069 SET_L_REG (code->dst.reg, res);
1070 goto just_flags_inc32;
1073 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1075 case O (O_ANDC, SB):
1077 ea = code->src.literal;
1083 ea = code->src.literal;
1087 case O (O_XORC, SB):
1089 ea = code->src.literal;
1130 if (((Z || (N ^ V)) == 0))
1136 if (((Z || (N ^ V)) == 1))
1170 case O (O_SYSCALL, SB):
1171 printf ("%c", cpu.regs[2]);
1174 OSHIFTS (O_NOT, rd = ~rd);
1175 OSHIFTS (O_SHLL, c = rd & hm;
1177 OSHIFTS (O_SHLR, c = rd & 1;
1178 rd = (unsigned int) rd >> 1);
1179 OSHIFTS (O_SHAL, c = rd & hm;
1181 OSHIFTS (O_SHAR, t = rd & hm;
1186 OSHIFTS (O_ROTL, c = rd & hm;
1189 OSHIFTS (O_ROTR, c = rd & 1;
1190 rd = (unsigned int) rd >> 1;
1192 OSHIFTS (O_ROTXL, t = rd & hm;
1197 OSHIFTS (O_ROTXR, t = rd & 1;
1198 rd = (unsigned int) rd >> 1;
1199 if (C) rd |= hm; c = t;);
1203 pc = fetch (&code->src);
1211 pc = fetch (&code->src);
1218 SET_MEMORY_L (tmp, code->next_pc);
1223 SET_MEMORY_W (tmp, code->next_pc);
1230 pc = code->src.literal;
1241 pc = GET_MEMORY_L (tmp);
1246 pc = GET_MEMORY_W (tmp);
1255 cpu.exception = SIGILL;
1257 case O (O_SLEEP, SB):
1258 /* The format of r0 is defined by devo/include/wait.h.
1259 cpu.exception handling needs some cleanup: we need to make the
1260 the handling of normal exits vs signals, etc. more sensible. */
1261 if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0]))
1262 cpu.exception = SIGILL;
1264 cpu.exception = SIGTRAP;
1267 cpu.exception = SIGTRAP;
1270 OBITOP (O_BNOT, 1, 1, ea ^= m);
1271 OBITOP (O_BTST, 1, 0, nz = ea & m);
1272 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1273 OBITOP (O_BSET, 1, 1, ea |= m);
1274 OBITOP (O_BLD, 1, 0, c = ea & m);
1275 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1276 OBITOP (O_BST, 1, 1, ea &= ~m;
1278 OBITOP (O_BIST, 1, 1, ea &= ~m;
1280 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1281 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1282 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1283 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1284 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1285 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1288 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1290 case O (O_MULS, SB):
1293 case O (O_MULS, SW):
1296 case O (O_MULU, SB):
1299 case O (O_MULU, SW):
1304 case O (O_DIVU, SB):
1306 rd = GET_W_REG (code->dst.reg);
1307 ea = GET_B_REG (code->src.reg);
1313 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1319 case O (O_DIVU, SW):
1321 rd = GET_L_REG (code->dst.reg);
1322 ea = GET_W_REG (code->src.reg);
1330 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1334 case O (O_DIVS, SB):
1337 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1338 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1341 tmp = (int) rd % (int) ea;
1342 rd = (int) rd / (int) ea;
1348 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1351 case O (O_DIVS, SW):
1353 rd = GET_L_REG (code->dst.reg);
1354 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1357 tmp = (int) rd % (int) ea;
1358 rd = (int) rd / (int) ea;
1359 n = rd & 0x80000000;
1364 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1367 case O (O_EXTS, SW):
1368 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1369 ea = rd & 0x80 ? -256 : 0;
1372 case O (O_EXTS, SL):
1373 rd = GET_W_REG (code->src.reg) & 0xffff;
1374 ea = rd & 0x8000 ? -65536 : 0;
1377 case O (O_EXTU, SW):
1378 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1382 case O (O_EXTU, SL):
1383 rd = GET_W_REG (code->src.reg) & 0xffff;
1392 cpu.exception = SIGILL;
1404 /* When a branch works */
1405 pc = code->src.literal;
1408 /* Set the cond codes from res */
1411 /* Set the flags after an 8 bit inc/dec operation */
1415 v = (rd & 0x7f) == 0x7f;
1419 /* Set the flags after an 16 bit inc/dec operation */
1423 v = (rd & 0x7fff) == 0x7fff;
1427 /* Set the flags after an 32 bit inc/dec operation */
1429 n = res & 0x80000000;
1430 nz = res & 0xffffffff;
1431 v = (rd & 0x7fffffff) == 0x7fffffff;
1436 /* Set flags after an 8 bit shift op, carry set in insn */
1440 SET_B_REG (code->src.reg, rd);
1445 /* Set flags after an 16 bit shift op, carry set in insn */
1450 SET_W_REG (code->src.reg, rd);
1454 /* Set flags after an 32 bit shift op, carry set in insn */
1455 n = (rd & 0x80000000);
1457 nz = rd & 0xffffffff;
1458 SET_L_REG (code->src.reg, rd);
1462 store (&code->dst, res);
1464 /* flags after a 32bit logical operation */
1465 n = res & 0x80000000;
1466 nz = res & 0xffffffff;
1471 store (&code->dst, res);
1473 /* flags after a 16bit logical operation */
1481 store (&code->dst, res);
1489 SET_B_REG (code->dst.reg, res);
1493 v = ((ea & 0x80) == (rd & 0x80)) && ((ea & 0x80) != (res & 0x80));
1498 SET_W_REG (code->dst.reg, res);
1502 v = ((ea & 0x8000) == (rd & 0x8000)) && ((ea & 0x8000) != (res & 0x8000));
1503 c = (res & 0x10000);
1507 SET_L_REG (code->dst.reg, res);
1509 n = res & 0x80000000;
1510 nz = res & 0xffffffff;
1511 v = ((ea & 0x80000000) == (rd & 0x80000000))
1512 && ((ea & 0x80000000) != (res & 0x80000000));
1513 switch (code->opcode / 4)
1516 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1520 c = (unsigned) rd < (unsigned) -ea;
1533 /* if (cpu.regs[8] ) abort(); */
1536 /* Poll after every 100th insn, */
1537 if (poll_count++ > 100)
1540 if (win32pollquit())
1546 #if defined(__GO32__)
1547 /* Poll after every 100th insn, */
1548 if (poll_count++ > 100)
1560 while (!cpu.exception);
1561 cpu.ticks += get_now () - tick_start;
1562 cpu.cycles += cycles;
1568 signal (SIGINT, prev);
1573 sim_write (addr, buffer, size)
1575 unsigned char *buffer;
1581 if (addr < 0 || addr + size > memory_size)
1583 for (i = 0; i < size; i++)
1585 cpu.memory[addr + i] = buffer[i];
1586 cpu.cache_idx[addr + i] = 0;
1592 sim_read (addr, buffer, size)
1594 unsigned char *buffer;
1598 if (addr < 0 || addr + size > memory_size)
1600 memcpy (buffer, cpu.memory + addr, size);
1614 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1615 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1618 #define CCR_REGNUM 8 /* Contains processor status */
1619 #define PC_REGNUM 9 /* Contains program counter */
1621 #define CYCLE_REGNUM 10
1622 #define INST_REGNUM 11
1623 #define TICK_REGNUM 12
1627 sim_store_register (rn, value)
1629 unsigned char *value;
1634 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1635 shortval = (value[0] << 8) | (value[1]);
1636 intval = h8300hmode ? longval : shortval;
1654 cpu.regs[rn] = intval;
1660 cpu.cycles = longval;
1664 cpu.insts = longval;
1668 cpu.ticks = longval;
1674 sim_fetch_register (rn, buf)
1716 if (h8300hmode || longreg)
1731 sim_stop_reason (reason, sigrc)
1732 enum sim_stop *reason;
1735 *reason = sim_stopped;
1736 *sigrc = cpu.exception;
1745 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1746 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1755 double timetaken = (double) cpu.ticks / (double) now_persec ();
1756 double virttime = cpu.cycles / 10.0e6;
1758 printf_filtered ("\n\n#instructions executed %10d\n", cpu.insts);
1759 printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles);
1760 printf_filtered ("#real time taken %10.4f\n", timetaken);
1761 printf_filtered ("#virtual time taked %10.4f\n", virttime);
1762 if (timetaken != 0.0)
1763 printf_filtered ("#simulation ratio %10.4f\n", virttime / timetaken);
1764 printf_filtered ("#compiles %10d\n", cpu.compiles);
1765 printf_filtered ("#cache size %10d\n", cpu.csize);
1771 for (i = 0; i < O_LAST; i++)
1774 printf_filtered ("%d: %d\n", i, cpu.stats[i]);
1780 /* Indicate whether the cpu is an h8/300 or h8/300h.
1781 FLAG is non-zero for the h8/300h. */
1804 sim_close (quitting)
1810 /* Called by gdb to load a program into memory. */
1813 sim_load (prog, from_tty)
1819 /* See if the file is for the h8/300 or h8/300h. */
1820 /* ??? This may not be the most efficient way. The z8k simulator
1821 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
1822 if ((abfd = bfd_openr (prog, "coff-h8300")) != 0)
1824 if (bfd_check_format (abfd, bfd_object))
1825 set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h);
1829 /* Return non-zero so gdb will handle it. */
1834 sim_create_inferior (start_address, argv, env)
1835 SIM_ADDR start_address;
1839 cpu.pc = start_address;
1843 sim_do_command (cmd)
1846 printf_filtered ("This simulator does not accept any commands.\n");
1852 sim_set_callbacks (ptr)
1853 struct host_callback_struct *ptr;