2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
29 #include <sys/param.h>
34 #include "remote-sim.h"
38 host_callback *sim_callback;
40 static SIM_OPEN_KIND sim_kind;
43 /* FIXME: Needs to live in header file.
44 This header should also include the things in remote-sim.h.
45 One could move this to remote-sim.h but this function isn't needed
47 void sim_set_simcache_size PARAMS ((int));
49 #define X(op, size) op*4+size
51 #define SP (h8300hmode ? SL:SW)
64 #define h8_opcodes ops
66 #include "opcode/h8300.h"
70 #define LOW_BYTE(x) ((x) & 0xff)
71 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
72 #define P(X,Y) ((X<<8) | Y)
74 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
77 c = (cpu.ccr >> 0) & 1;\
78 v = (cpu.ccr >> 1) & 1;\
79 nz = !((cpu.ccr >> 2) & 1);\
80 n = (cpu.ccr >> 3) & 1;
82 #ifdef __CHAR_IS_SIGNED__
83 #define SEXTCHAR(x) ((char)(x))
87 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
90 #define UEXTCHAR(x) ((x) & 0xff)
91 #define UEXTSHORT(x) ((x) & 0xffff)
92 #define SEXTSHORT(x) ((short)(x))
94 static cpu_state_type cpu;
99 static int memory_size;
130 return h8300hmode ? SL : SW;
143 return X (OP_IMM, SP);
145 return X (OP_REG, SP);
149 return X (OP_MEM, SP);
156 decode (addr, data, dst)
169 struct h8_opcode *q = h8_opcodes;
173 /* Find the exact opcode/arg combo */
177 unsigned int len = 0;
183 op_type looking_for = *nib;
184 int thisnib = data[len >> 1];
186 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
188 if (looking_for < 16 && looking_for >= 0)
190 if (looking_for != thisnib)
195 if ((int) looking_for & (int) B31)
197 if (!(((int) thisnib & 0x8) != 0))
199 looking_for = (op_type) ((int) looking_for & ~(int)
203 if ((int) looking_for & (int) B30)
205 if (!(((int) thisnib & 0x8) == 0))
207 looking_for = (op_type) ((int) looking_for & ~(int) B30);
209 if (looking_for & DBIT)
211 if ((looking_for & 5) != (thisnib & 5))
213 abs = (thisnib & 0x8) ? 2 : 1;
215 else if (looking_for & (REG | IND | INC | DEC))
217 if (looking_for & REG)
220 * Can work out size from the
223 size = bitfrom (looking_for);
225 if (looking_for & SRC)
234 else if (looking_for & L_16)
236 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
238 if (looking_for & (PCREL | DISP))
243 else if (looking_for & ABSJMP)
250 else if (looking_for & MEMIND)
254 else if (looking_for & L_32)
257 abs = (data[i] << 24)
258 | (data[i + 1] << 16)
264 else if (looking_for & L_24)
267 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
270 else if (looking_for & IGNORE)
274 else if (looking_for & DISPREG)
276 rdisp = thisnib & 0x7;
278 else if (looking_for & KBIT)
293 else if (looking_for & L_8)
297 if (looking_for & PCREL)
299 abs = SEXTCHAR (data[len >> 1]);
301 else if (looking_for & ABS8MEM)
304 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
305 abs |= data[len >> 1] & 0xff ;
309 abs = data[len >> 1] & 0xff;
312 else if (looking_for & L_3)
318 else if (looking_for == E)
322 /* Fill in the args */
324 op_type *args = q->args.nib;
330 int rn = (x & DST) ? rd : rs;
344 p->type = X (OP_IMM, size);
347 else if (x & (IMM | KBIT | DBIT))
349 p->type = X (OP_IMM, size);
354 /* Reset the size, some
355 ops (like mul) have two sizes */
358 p->type = X (OP_REG, size);
363 p->type = X (OP_INC, size);
368 p->type = X (OP_DEC, size);
373 p->type = X (OP_DISP, size);
377 else if (x & (ABS | ABSJMP | ABS8MEM))
379 p->type = X (OP_DISP, size);
385 p->type = X (OP_MEM, size);
390 p->type = X (OP_PCREL, size);
391 p->literal = abs + addr + 2;
397 p->type = X (OP_IMM, SP);
402 p->type = X (OP_DISP, size);
404 p->reg = rdisp & 0x7;
411 printf ("Hmmmm %x", x);
418 * But a jmp or a jsr gets
419 * automagically lvalued, since we
420 * branch to their address not their
423 if (q->how == O (O_JSR, SB)
424 || q->how == O (O_JMP, SB))
426 dst->src.type = lvalue (dst->src.type, dst->src.reg);
429 if (dst->dst.type == -1)
432 dst->opcode = q->how;
433 dst->cycles = q->time;
435 /* And a jsr to 0xc4 is turned into a magic trap */
437 if (dst->opcode == O (O_JSR, SB))
439 if (dst->src.literal == 0xc4)
441 dst->opcode = O (O_SYSCALL, SB);
445 dst->next_pc = addr + len / 2;
450 printf ("Dont understand %x \n", looking_for);
462 dst->opcode = O (O_ILL, SB);
471 /* find the next cache entry to use */
473 idx = cpu.cache_top + 1;
475 if (idx >= cpu.csize)
481 /* Throw away its old meaning */
482 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
484 /* set to new address */
485 cpu.cache[idx].oldpc = pc;
487 /* fill in instruction info */
488 decode (pc, cpu.memory + pc, cpu.cache + idx);
490 /* point to new cache entry */
491 cpu.cache_idx[pc] = idx;
495 static unsigned char *breg[18];
496 static unsigned short *wreg[18];
497 static unsigned int *lreg[18];
499 #define GET_B_REG(x) *(breg[x])
500 #define SET_B_REG(x,y) (*(breg[x])) = (y)
501 #define GET_W_REG(x) *(wreg[x])
502 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
504 #define GET_L_REG(x) *(lreg[x])
505 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
507 #define GET_MEMORY_L(x) \
509 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
510 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
511 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
512 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
514 #define GET_MEMORY_W(x) \
516 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
517 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
520 #define GET_MEMORY_B(x) \
521 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
523 #define SET_MEMORY_L(x,y) \
524 { register unsigned char *_p; register int __y = y; \
525 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
526 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
527 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
529 #define SET_MEMORY_W(x,y) \
530 { register unsigned char *_p; register int __y = y; \
531 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
532 _p[0] = (__y)>>8; _p[1] =(__y);}
534 #define SET_MEMORY_B(x,y) \
535 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
542 int abs = arg->literal;
549 return GET_B_REG (rn);
551 return GET_W_REG (rn);
553 return GET_L_REG (rn);
564 r = GET_MEMORY_B (t);
573 r = GET_MEMORY_W (t);
581 r = GET_MEMORY_L (t);
588 case X (OP_DISP, SB):
589 t = GET_L_REG (rn) + abs;
591 return GET_MEMORY_B (t);
593 case X (OP_DISP, SW):
594 t = GET_L_REG (rn) + abs;
596 return GET_MEMORY_W (t);
598 case X (OP_DISP, SL):
599 t = GET_L_REG (rn) + abs;
601 return GET_MEMORY_L (t);
604 t = GET_MEMORY_L (abs);
609 t = GET_MEMORY_W (abs);
627 int abs = arg->literal;
643 t = GET_L_REG (rn) - 1;
650 t = (GET_L_REG (rn) - 2) & cpu.mask;
656 t = (GET_L_REG (rn) - 4) & cpu.mask;
661 case X (OP_DISP, SB):
662 t = GET_L_REG (rn) + abs;
667 case X (OP_DISP, SW):
668 t = GET_L_REG (rn) + abs;
673 case X (OP_DISP, SL):
674 t = GET_L_REG (rn) + abs;
711 memory_size = H8300H_MSIZE;
713 memory_size = H8300_MSIZE;
714 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
715 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
716 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
718 /* `msize' must be a power of two */
719 if ((memory_size & (memory_size - 1)) != 0)
721 cpu.mask = memory_size - 1;
723 for (i = 0; i < 9; i++)
728 for (i = 0; i < 8; i++)
730 unsigned char *p = (unsigned char *) (cpu.regs + i);
731 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
732 unsigned short *q = (unsigned short *) (cpu.regs + i);
733 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
734 cpu.regs[i] = 0x00112233;
760 lreg[i] = &cpu.regs[i];
763 lreg[8] = &cpu.regs[8];
765 /* initialize the seg registers */
767 sim_set_simcache_size (CSIZE);
772 control_c (sig, code, scp, addr)
778 cpu.state = SIM_STATE_STOPPED;
779 cpu.exception = SIGINT;
788 mop (code, bsize, sign)
801 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
802 SEXTSHORT (GET_W_REG (code->dst.reg));
804 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
805 SEXTSHORT (GET_W_REG (code->src.reg));
809 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
810 UEXTSHORT (GET_W_REG (code->dst.reg));
812 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
813 UEXTSHORT (GET_W_REG (code->src.reg));
816 result = multiplier * multiplicand;
820 n = result & (bsize ? 0x8000 : 0x80000000);
821 nz = result & (bsize ? 0xffff : 0xffffffff);
825 SET_W_REG (code->dst.reg, result);
829 SET_L_REG (code->dst.reg, result);
831 /* return ((n==1) << 1) | (nz==1); */
835 #define ONOT(name, how) \
840 rd = GET_B_REG (code->src.reg); \
848 rd = GET_W_REG (code->src.reg); \
855 int hm = 0x80000000; \
856 rd = GET_L_REG (code->src.reg); \
861 #define OSHIFTS(name, how1, how2) \
866 rd = GET_B_REG (code->src.reg); \
867 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
881 rd = GET_W_REG (code->src.reg); \
882 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
895 int hm = 0x80000000; \
896 rd = GET_L_REG (code->src.reg); \
897 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
908 #define OBITOP(name,f, s, op) \
913 if (f) ea = fetch (&code->dst); \
914 m=1<< fetch(&code->src); \
916 if(s) store (&code->dst,ea); goto next; \
920 sim_resume (sd, step, siggnal)
926 int tick_start = get_now ();
939 prev = signal (SIGINT, control_c);
943 cpu.state = SIM_STATE_STOPPED;
944 cpu.exception = SIGTRAP;
948 cpu.state = SIM_STATE_RUNNING;
954 /* The PC should never be odd. */
968 cidx = cpu.cache_idx[pc];
969 code = cpu.cache + cidx;
972 #define ALUOP(STORE, NAME, HOW) \
973 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
974 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
975 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
978 #define LOGOP(NAME, HOW) \
979 case O(NAME,SB): HOW; goto log8;\
980 case O(NAME, SW): HOW; goto log16;\
981 case O(NAME,SL): HOW; goto log32;
988 printf ("%x %d %s\n", pc, code->opcode,
989 code->op ? code->op->name : "**");
991 cpu.stats[code->opcode]++;
995 cycles += code->cycles;
997 switch (code->opcode)
1001 * This opcode is a fake for when we get to an
1002 * instruction which hasnt been compiled
1009 case O (O_SUBX, SB):
1010 rd = fetch (&code->dst);
1011 ea = fetch (&code->src);
1016 case O (O_ADDX, SB):
1017 rd = fetch (&code->dst);
1018 ea = fetch (&code->src);
1023 #define EA ea = fetch(&code->src);
1024 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1026 ALUOP (1, O_SUB, RD_EA;
1029 ALUOP (1, O_NEG, EA;
1035 rd = GET_B_REG (code->dst.reg);
1036 ea = fetch (&code->src);
1040 rd = GET_W_REG (code->dst.reg);
1041 ea = fetch (&code->src);
1045 rd = GET_L_REG (code->dst.reg);
1046 ea = fetch (&code->src);
1051 LOGOP (O_AND, RD_EA;
1057 LOGOP (O_XOR, RD_EA;
1061 case O (O_MOV_TO_MEM, SB):
1062 res = GET_B_REG (code->src.reg);
1064 case O (O_MOV_TO_MEM, SW):
1065 res = GET_W_REG (code->src.reg);
1067 case O (O_MOV_TO_MEM, SL):
1068 res = GET_L_REG (code->src.reg);
1072 case O (O_MOV_TO_REG, SB):
1073 res = fetch (&code->src);
1074 SET_B_REG (code->dst.reg, res);
1075 goto just_flags_log8;
1076 case O (O_MOV_TO_REG, SW):
1077 res = fetch (&code->src);
1078 SET_W_REG (code->dst.reg, res);
1079 goto just_flags_log16;
1080 case O (O_MOV_TO_REG, SL):
1081 res = fetch (&code->src);
1082 SET_L_REG (code->dst.reg, res);
1083 goto just_flags_log32;
1086 case O (O_ADDS, SL):
1087 SET_L_REG (code->dst.reg,
1088 GET_L_REG (code->dst.reg)
1089 + code->src.literal);
1093 case O (O_SUBS, SL):
1094 SET_L_REG (code->dst.reg,
1095 GET_L_REG (code->dst.reg)
1096 - code->src.literal);
1100 rd = fetch (&code->dst);
1101 ea = fetch (&code->src);
1104 goto just_flags_alu8;
1107 rd = fetch (&code->dst);
1108 ea = fetch (&code->src);
1111 goto just_flags_alu16;
1114 rd = fetch (&code->dst);
1115 ea = fetch (&code->src);
1118 goto just_flags_alu32;
1122 rd = GET_B_REG (code->src.reg);
1125 SET_B_REG (code->src.reg, res);
1126 goto just_flags_inc8;
1129 rd = GET_W_REG (code->dst.reg);
1130 ea = -code->src.literal;
1132 SET_W_REG (code->dst.reg, res);
1133 goto just_flags_inc16;
1136 rd = GET_L_REG (code->dst.reg);
1137 ea = -code->src.literal;
1139 SET_L_REG (code->dst.reg, res);
1140 goto just_flags_inc32;
1144 rd = GET_B_REG (code->src.reg);
1147 SET_B_REG (code->src.reg, res);
1148 goto just_flags_inc8;
1151 rd = GET_W_REG (code->dst.reg);
1152 ea = code->src.literal;
1154 SET_W_REG (code->dst.reg, res);
1155 goto just_flags_inc16;
1158 rd = GET_L_REG (code->dst.reg);
1159 ea = code->src.literal;
1161 SET_L_REG (code->dst.reg, res);
1162 goto just_flags_inc32;
1165 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1167 case O (O_ANDC, SB):
1169 ea = code->src.literal;
1175 ea = code->src.literal;
1179 case O (O_XORC, SB):
1181 ea = code->src.literal;
1222 if (((Z || (N ^ V)) == 0))
1228 if (((Z || (N ^ V)) == 1))
1262 case O (O_SYSCALL, SB):
1263 printf ("%c", cpu.regs[2]);
1266 ONOT (O_NOT, rd = ~rd; v = 0;);
1268 c = rd & hm; v = 0; rd <<= 1,
1269 c = rd & (hm >> 1); v = 0; rd <<= 2);
1271 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1272 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1274 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1275 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1277 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1278 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1280 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1281 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1283 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1284 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1286 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1287 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1289 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1290 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1294 pc = fetch (&code->src);
1302 pc = fetch (&code->src);
1309 SET_MEMORY_L (tmp, code->next_pc);
1314 SET_MEMORY_W (tmp, code->next_pc);
1321 pc = code->src.literal;
1332 pc = GET_MEMORY_L (tmp);
1337 pc = GET_MEMORY_W (tmp);
1346 cpu.state = SIM_STATE_STOPPED;
1347 cpu.exception = SIGILL;
1349 case O (O_SLEEP, SN):
1350 /* The format of r0 is defined by devo/include/wait.h. */
1351 #if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */
1352 if (WIFEXITED (cpu.regs[0]))
1354 cpu.state = SIM_STATE_EXITED;
1355 cpu.exception = WEXITSTATUS (cpu.regs[0]);
1357 else if (WIFSTOPPED (cpu.regs[0]))
1359 cpu.state = SIM_STATE_STOPPED;
1360 cpu.exception = WSTOPSIG (cpu.regs[0]);
1364 cpu.state = SIM_STATE_SIGNALLED;
1365 cpu.exception = WTERMSIG (cpu.regs[0]);
1368 /* FIXME: Doesn't this break for breakpoints when r0
1369 contains just the right (er, wrong) value? */
1370 cpu.state = SIM_STATE_STOPPED;
1371 if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0]))
1372 cpu.exception = SIGILL;
1374 cpu.exception = SIGTRAP;
1378 cpu.state = SIM_STATE_STOPPED;
1379 cpu.exception = SIGTRAP;
1382 OBITOP (O_BNOT, 1, 1, ea ^= m);
1383 OBITOP (O_BTST, 1, 0, nz = ea & m);
1384 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1385 OBITOP (O_BSET, 1, 1, ea |= m);
1386 OBITOP (O_BLD, 1, 0, c = ea & m);
1387 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1388 OBITOP (O_BST, 1, 1, ea &= ~m;
1390 OBITOP (O_BIST, 1, 1, ea &= ~m;
1392 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1393 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1394 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1395 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1396 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1397 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1400 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1402 case O (O_MULS, SB):
1405 case O (O_MULS, SW):
1408 case O (O_MULU, SB):
1411 case O (O_MULU, SW):
1416 case O (O_DIVU, SB):
1418 rd = GET_W_REG (code->dst.reg);
1419 ea = GET_B_REG (code->src.reg);
1422 tmp = (unsigned)rd % ea;
1423 rd = (unsigned)rd / ea;
1425 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1431 case O (O_DIVU, SW):
1433 rd = GET_L_REG (code->dst.reg);
1434 ea = GET_W_REG (code->src.reg);
1439 tmp = (unsigned)rd % ea;
1440 rd = (unsigned)rd / ea;
1442 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1446 case O (O_DIVS, SB):
1449 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1450 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1453 tmp = (int) rd % (int) ea;
1454 rd = (int) rd / (int) ea;
1460 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1463 case O (O_DIVS, SW):
1465 rd = GET_L_REG (code->dst.reg);
1466 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1469 tmp = (int) rd % (int) ea;
1470 rd = (int) rd / (int) ea;
1471 n = rd & 0x80000000;
1476 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1479 case O (O_EXTS, SW):
1480 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1481 ea = rd & 0x80 ? -256 : 0;
1484 case O (O_EXTS, SL):
1485 rd = GET_W_REG (code->src.reg) & 0xffff;
1486 ea = rd & 0x8000 ? -65536 : 0;
1489 case O (O_EXTU, SW):
1490 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1494 case O (O_EXTU, SL):
1495 rd = GET_W_REG (code->src.reg) & 0xffff;
1505 int nregs, firstreg, i;
1507 nregs = GET_MEMORY_B (pc + 1);
1510 firstreg = GET_MEMORY_B (pc + 3);
1512 for (i = firstreg; i <= firstreg + nregs; i++)
1515 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1522 int nregs, firstreg, i;
1524 nregs = GET_MEMORY_B (pc + 1);
1527 firstreg = GET_MEMORY_B (pc + 3);
1529 for (i = firstreg; i >= firstreg - nregs; i--)
1531 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1538 cpu.state = SIM_STATE_STOPPED;
1539 cpu.exception = SIGILL;
1551 /* When a branch works */
1552 pc = code->src.literal;
1555 /* Set the cond codes from res */
1558 /* Set the flags after an 8 bit inc/dec operation */
1562 v = (rd & 0x7f) == 0x7f;
1566 /* Set the flags after an 16 bit inc/dec operation */
1570 v = (rd & 0x7fff) == 0x7fff;
1574 /* Set the flags after an 32 bit inc/dec operation */
1576 n = res & 0x80000000;
1577 nz = res & 0xffffffff;
1578 v = (rd & 0x7fffffff) == 0x7fffffff;
1583 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1586 SET_B_REG (code->src.reg, rd);
1590 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1593 SET_W_REG (code->src.reg, rd);
1597 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1598 n = (rd & 0x80000000);
1599 nz = rd & 0xffffffff;
1600 SET_L_REG (code->src.reg, rd);
1604 store (&code->dst, res);
1606 /* flags after a 32bit logical operation */
1607 n = res & 0x80000000;
1608 nz = res & 0xffffffff;
1613 store (&code->dst, res);
1615 /* flags after a 16bit logical operation */
1623 store (&code->dst, res);
1631 SET_B_REG (code->dst.reg, res);
1636 switch (code->opcode / 4)
1639 v = ((rd & 0x80) == (ea & 0x80)
1640 && (rd & 0x80) != (res & 0x80));
1644 v = ((rd & 0x80) != (-ea & 0x80)
1645 && (rd & 0x80) != (res & 0x80));
1654 SET_W_REG (code->dst.reg, res);
1658 c = (res & 0x10000);
1659 switch (code->opcode / 4)
1662 v = ((rd & 0x8000) == (ea & 0x8000)
1663 && (rd & 0x8000) != (res & 0x8000));
1667 v = ((rd & 0x8000) != (-ea & 0x8000)
1668 && (rd & 0x8000) != (res & 0x8000));
1677 SET_L_REG (code->dst.reg, res);
1679 n = res & 0x80000000;
1680 nz = res & 0xffffffff;
1681 switch (code->opcode / 4)
1684 v = ((rd & 0x80000000) == (ea & 0x80000000)
1685 && (rd & 0x80000000) != (res & 0x80000000));
1686 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1690 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1691 && (rd & 0x80000000) != (res & 0x80000000));
1692 c = (unsigned) rd < (unsigned) -ea;
1695 v = (rd == 0x80000000);
1706 /* if (cpu.regs[8] ) abort(); */
1709 /* Poll after every 100th insn, */
1710 if (poll_count++ > 100)
1713 if (win32pollquit())
1719 #if defined(__GO32__)
1720 /* Poll after every 100th insn, */
1721 if (poll_count++ > 100)
1733 while (cpu.state == SIM_STATE_RUNNING);
1734 cpu.ticks += get_now () - tick_start;
1735 cpu.cycles += cycles;
1741 signal (SIGINT, prev);
1748 /* FIXME: unfinished */
1753 sim_write (sd, addr, buffer, size)
1756 unsigned char *buffer;
1764 for (i = 0; i < size; i++)
1766 if (addr < memory_size)
1768 cpu.memory[addr + i] = buffer[i];
1769 cpu.cache_idx[addr + i] = 0;
1772 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1778 sim_read (sd, addr, buffer, size)
1781 unsigned char *buffer;
1787 if (addr < memory_size)
1788 memcpy (buffer, cpu.memory + addr, size);
1790 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1804 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1805 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1808 #define CCR_REGNUM 8 /* Contains processor status */
1809 #define PC_REGNUM 9 /* Contains program counter */
1811 #define CYCLE_REGNUM 10
1812 #define INST_REGNUM 11
1813 #define TICK_REGNUM 12
1817 sim_store_register (sd, rn, value)
1820 unsigned char *value;
1825 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1826 shortval = (value[0] << 8) | (value[1]);
1827 intval = h8300hmode ? longval : shortval;
1845 cpu.regs[rn] = intval;
1851 cpu.cycles = longval;
1855 cpu.insts = longval;
1859 cpu.ticks = longval;
1865 sim_fetch_register (sd, rn, buf)
1908 if (h8300hmode || longreg)
1923 sim_stop_reason (sd, reason, sigrc)
1925 enum sim_stop *reason;
1928 #if 0 /* FIXME: This should work but we can't use it.
1929 grep for SLEEP above. */
1932 case SIM_STATE_EXITED : *reason = sim_exited; break;
1933 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1934 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1938 *reason = sim_stopped;
1940 *sigrc = cpu.exception;
1943 /* FIXME: Rename to sim_set_mem_size. */
1949 /* Memory size is fixed. */
1953 sim_set_simcache_size (n)
1959 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1960 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1966 sim_info (sd, verbose)
1970 double timetaken = (double) cpu.ticks / (double) now_persec ();
1971 double virttime = cpu.cycles / 10.0e6;
1973 (*sim_callback->printf_filtered) (sim_callback,
1974 "\n\n#instructions executed %10d\n",
1976 (*sim_callback->printf_filtered) (sim_callback,
1977 "#cycles (v approximate) %10d\n",
1979 (*sim_callback->printf_filtered) (sim_callback,
1980 "#real time taken %10.4f\n",
1982 (*sim_callback->printf_filtered) (sim_callback,
1983 "#virtual time taked %10.4f\n",
1985 if (timetaken != 0.0)
1986 (*sim_callback->printf_filtered) (sim_callback,
1987 "#simulation ratio %10.4f\n",
1988 virttime / timetaken);
1989 (*sim_callback->printf_filtered) (sim_callback,
1992 (*sim_callback->printf_filtered) (sim_callback,
1993 "#cache size %10d\n",
1997 /* This to be conditional on `what' (aka `verbose'),
1998 however it was never passed as non-zero. */
2002 for (i = 0; i < O_LAST; i++)
2005 (*sim_callback->printf_filtered) (sim_callback,
2006 "%d: %d\n", i, cpu.stats[i]);
2012 /* Indicate whether the cpu is an h8/300 or h8/300h.
2013 FLAG is non-zero for the h8/300h. */
2030 sim_open (kind,argv)
2036 /* fudge our descriptor */
2037 return (SIM_DESC) 1;
2041 sim_close (sd, quitting)
2048 /* Called by gdb to load a program into memory. */
2051 sim_load (sd, prog, abfd, from_tty)
2059 /* See if the file is for the h8/300 or h8/300h. */
2060 /* ??? This may not be the most efficient way. The z8k simulator
2061 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2065 prog_bfd = bfd_openr (prog, "coff-h8300");
2066 if (prog_bfd != NULL)
2068 if (bfd_check_format (prog_bfd, bfd_object))
2070 set_h8300h (prog_bfd->arch_info->mach == bfd_mach_h8300h
2071 || prog_bfd->arch_info->mach == bfd_mach_h8300s);
2075 /* If we're using gdb attached to the simulator, then we have to
2076 reallocate memory for the simulator.
2078 When gdb first starts, it calls fetch_registers (among other
2079 functions), which in turn calls init_pointers, which allocates
2082 The problem is when we do that, we don't know whether we're
2083 debugging an h8/300 or h8/300h program.
2085 This is the first point at which we can make that determination,
2086 so we just reallocate memory now; this will also allow us to handle
2087 switching between h8/300 and h8/300h programs without exiting
2090 memory_size = H8300H_MSIZE;
2092 memory_size = H8300_MSIZE;
2097 free (cpu.cache_idx);
2099 free (cpu.eightbit);
2101 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2102 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2103 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2105 /* `msize' must be a power of two */
2106 if ((memory_size & (memory_size - 1)) != 0)
2108 cpu.mask = memory_size - 1;
2110 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2111 sim_kind == SIM_OPEN_DEBUG)
2114 /* Close the bfd if we opened it. */
2115 if (abfd == NULL && prog_bfd != NULL)
2116 bfd_close (prog_bfd);
2120 cpu.pc = bfd_get_start_address (prog_bfd);
2121 /* Close the bfd if we opened it. */
2122 if (abfd == NULL && prog_bfd != NULL)
2123 bfd_close (prog_bfd);
2128 sim_create_inferior (sd, argv, env)
2137 sim_do_command (sd, cmd)
2141 (*sim_callback->printf_filtered) (sim_callback,
2142 "This simulator does not accept any commands.\n");
2146 sim_set_callbacks (sd, ptr)
2148 struct host_callback_struct *ptr;