2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
36 #include "remote-sim.h"
44 host_callback *sim_callback;
46 static SIM_OPEN_KIND sim_kind;
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
53 void sim_set_simcache_size PARAMS ((int));
55 #define X(op, size) op * 4 + size
57 #define SP (h8300hmode ? SL : SW)
70 #define h8_opcodes ops
72 #include "opcode/h8300.h"
76 /* The rate at which to call the host's poll_quit callback. */
78 #define POLL_QUIT_INTERVAL 0x80000
80 #define LOW_BYTE(x) ((x) & 0xff)
81 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
82 #define P(X,Y) ((X << 8) | Y)
84 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V << 1) | C;
87 c = (cpu.ccr >> 0) & 1;\
88 v = (cpu.ccr >> 1) & 1;\
89 nz = !((cpu.ccr >> 2) & 1);\
90 n = (cpu.ccr >> 3) & 1;
92 #ifdef __CHAR_IS_SIGNED__
93 #define SEXTCHAR(x) ((char) (x))
97 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
100 #define UEXTCHAR(x) ((x) & 0xff)
101 #define UEXTSHORT(x) ((x) & 0xffff)
102 #define SEXTSHORT(x) ((short) (x))
104 static cpu_state_type cpu;
109 static int memory_size;
114 return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */
135 return h8300hmode ? SL : SW;
147 return X (OP_IMM, SP);
149 return X (OP_REG, SP);
152 return X (OP_MEM, SP);
155 abort (); /* ?? May be something more usefull? */
160 decode (addr, data, dst)
178 /* Find the exact opcode/arg combo. */
179 for (q = h8_opcodes; q->name; q++)
181 op_type *nib = q->data.nib;
182 unsigned int len = 0;
186 op_type looking_for = *nib;
187 int thisnib = data[len >> 1];
189 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
191 if (looking_for < 16 && looking_for >= 0)
193 if (looking_for != thisnib)
198 if ((int) looking_for & (int) B31)
200 if (!(((int) thisnib & 0x8) != 0))
203 looking_for = (op_type) ((int) looking_for & ~(int) B31);
207 if ((int) looking_for & (int) B30)
209 if (!(((int) thisnib & 0x8) == 0))
212 looking_for = (op_type) ((int) looking_for & ~(int) B30);
215 if (looking_for & DBIT)
217 /* Exclude adds/subs by looking at bit 0 and 2, and
218 make sure the operand size, either w or l,
219 matches by looking at bit 1. */
220 if ((looking_for & 7) != (thisnib & 7))
223 abs = (thisnib & 0x8) ? 2 : 1;
225 else if (looking_for & (REG | IND | INC | DEC))
227 if (looking_for & REG)
229 /* Can work out size from the register. */
230 size = bitfrom (looking_for);
232 if (looking_for & SRC)
237 else if (looking_for & L_16)
239 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
241 if (looking_for & (PCREL | DISP))
246 else if (looking_for & ABSJMP)
248 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
250 else if (looking_for & MEMIND)
254 else if (looking_for & L_32)
258 abs = (data[i] << 24)
259 | (data[i + 1] << 16)
265 else if (looking_for & L_24)
269 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
272 else if (looking_for & IGNORE)
276 else if (looking_for & DISPREG)
278 rdisp = thisnib & 0x7;
280 else if (looking_for & KBIT)
297 else if (looking_for & L_8)
301 if (looking_for & PCREL)
303 abs = SEXTCHAR (data[len >> 1]);
305 else if (looking_for & ABS8MEM)
308 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
309 abs |= data[len >> 1] & 0xff;
313 abs = data[len >> 1] & 0xff;
316 else if (looking_for & L_3)
322 else if (looking_for == E)
326 /* Fill in the args. */
328 op_type *args = q->args.nib;
334 int rn = (x & DST) ? rd : rs;
344 p->type = X (OP_IMM, size);
347 else if (x & (IMM | KBIT | DBIT))
349 p->type = X (OP_IMM, size);
355 Some ops (like mul) have two sizes. */
358 p->type = X (OP_REG, size);
363 p->type = X (OP_INC, size);
368 p->type = X (OP_DEC, size);
373 p->type = X (OP_DISP, size);
377 else if (x & (ABS | ABSJMP | ABS8MEM))
379 p->type = X (OP_DISP, size);
385 p->type = X (OP_MEM, size);
390 p->type = X (OP_PCREL, size);
391 p->literal = abs + addr + 2;
397 p->type = X (OP_IMM, SP);
402 p->type = X (OP_DISP, size);
404 p->reg = rdisp & 0x7;
411 printf ("Hmmmm %x", x);
417 /* But a jmp or a jsr gets automagically lvalued,
418 since we branch to their address not their
420 if (q->how == O (O_JSR, SB)
421 || q->how == O (O_JMP, SB))
423 dst->src.type = lvalue (dst->src.type, dst->src.reg);
426 if (dst->dst.type == -1)
429 dst->opcode = q->how;
430 dst->cycles = q->time;
432 /* And a jsr to 0xc4 is turned into a magic trap. */
434 if (dst->opcode == O (O_JSR, SB))
436 if (dst->src.literal == 0xc4)
438 dst->opcode = O (O_SYSCALL, SB);
442 dst->next_pc = addr + len / 2;
446 printf ("Don't understand %x \n", looking_for);
457 /* Fell off the end. */
458 dst->opcode = O (O_ILL, SB);
466 /* Find the next cache entry to use. */
467 idx = cpu.cache_top + 1;
469 if (idx >= cpu.csize)
475 /* Throw away its old meaning. */
476 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
478 /* Set to new address. */
479 cpu.cache[idx].oldpc = pc;
481 /* Fill in instruction info. */
482 decode (pc, cpu.memory + pc, cpu.cache + idx);
484 /* Point to new cache entry. */
485 cpu.cache_idx[pc] = idx;
489 static unsigned char *breg[18];
490 static unsigned short *wreg[18];
491 static unsigned int *lreg[18];
493 #define GET_B_REG(x) *(breg[x])
494 #define SET_B_REG(x,y) (*(breg[x])) = (y)
495 #define GET_W_REG(x) *(wreg[x])
496 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
498 #define GET_L_REG(x) *(lreg[x])
499 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
501 #define GET_MEMORY_L(x) \
503 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
504 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
505 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
506 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
508 #define GET_MEMORY_W(x) \
510 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
511 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
514 #define GET_MEMORY_B(x) \
515 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
517 #define SET_MEMORY_L(x,y) \
518 { register unsigned char *_p; register int __y = y; \
519 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
520 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
521 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
523 #define SET_MEMORY_W(x,y) \
524 { register unsigned char *_p; register int __y = y; \
525 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
526 _p[0] = (__y)>>8; _p[1] =(__y);}
528 #define SET_MEMORY_B(x,y) \
529 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
536 int abs = arg->literal;
543 return GET_B_REG (rn);
545 return GET_W_REG (rn);
547 return GET_L_REG (rn);
558 r = GET_MEMORY_B (t);
567 r = GET_MEMORY_W (t);
575 r = GET_MEMORY_L (t);
582 case X (OP_DISP, SB):
583 t = GET_L_REG (rn) + abs;
585 return GET_MEMORY_B (t);
587 case X (OP_DISP, SW):
588 t = GET_L_REG (rn) + abs;
590 return GET_MEMORY_W (t);
592 case X (OP_DISP, SL):
593 t = GET_L_REG (rn) + abs;
595 return GET_MEMORY_L (t);
598 t = GET_MEMORY_L (abs);
603 t = GET_MEMORY_W (abs);
608 abort (); /* ?? May be something more usefull? */
620 int abs = arg->literal;
636 t = GET_L_REG (rn) - 1;
643 t = (GET_L_REG (rn) - 2) & cpu.mask;
649 t = (GET_L_REG (rn) - 4) & cpu.mask;
654 case X (OP_DISP, SB):
655 t = GET_L_REG (rn) + abs;
660 case X (OP_DISP, SW):
661 t = GET_L_REG (rn) + abs;
666 case X (OP_DISP, SL):
667 t = GET_L_REG (rn) + abs;
703 memory_size = H8300H_MSIZE;
705 memory_size = H8300_MSIZE;
706 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
707 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
708 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
710 /* `msize' must be a power of two. */
711 if ((memory_size & (memory_size - 1)) != 0)
713 cpu.mask = memory_size - 1;
715 for (i = 0; i < 9; i++)
720 for (i = 0; i < 8; i++)
722 unsigned char *p = (unsigned char *) (cpu.regs + i);
723 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
724 unsigned short *q = (unsigned short *) (cpu.regs + i);
725 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
726 cpu.regs[i] = 0x00112233;
752 lreg[i] = &cpu.regs[i];
755 lreg[8] = &cpu.regs[8];
757 /* Initialize the seg registers. */
759 sim_set_simcache_size (CSIZE);
764 control_c (sig, code, scp, addr)
770 cpu.state = SIM_STATE_STOPPED;
771 cpu.exception = SIGINT;
780 mop (code, bsize, sign)
793 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
794 SEXTSHORT (GET_W_REG (code->dst.reg));
796 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
797 SEXTSHORT (GET_W_REG (code->src.reg));
801 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
802 UEXTSHORT (GET_W_REG (code->dst.reg));
804 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
805 UEXTSHORT (GET_W_REG (code->src.reg));
808 result = multiplier * multiplicand;
812 n = result & (bsize ? 0x8000 : 0x80000000);
813 nz = result & (bsize ? 0xffff : 0xffffffff);
817 SET_W_REG (code->dst.reg, result);
821 SET_L_REG (code->dst.reg, result);
824 return ((n == 1) << 1) | (nz == 1);
828 #define ONOT(name, how) \
833 rd = GET_B_REG (code->src.reg); \
841 rd = GET_W_REG (code->src.reg); \
848 int hm = 0x80000000; \
849 rd = GET_L_REG (code->src.reg); \
854 #define OSHIFTS(name, how1, how2) \
859 rd = GET_B_REG (code->src.reg); \
860 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
874 rd = GET_W_REG (code->src.reg); \
875 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
888 int hm = 0x80000000; \
889 rd = GET_L_REG (code->src.reg); \
890 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
901 #define OBITOP(name,f, s, op) \
906 if (f) ea = fetch (&code->dst); \
907 m=1<< fetch(&code->src); \
909 if(s) store (&code->dst,ea); goto next; \
916 cpu.state = SIM_STATE_STOPPED;
917 cpu.exception = SIGINT;
922 sim_resume (sd, step, siggnal)
928 int tick_start = get_now ();
941 prev = signal (SIGINT, control_c);
945 cpu.state = SIM_STATE_STOPPED;
946 cpu.exception = SIGTRAP;
950 cpu.state = SIM_STATE_RUNNING;
956 /* The PC should never be odd. */
970 cidx = cpu.cache_idx[pc];
971 code = cpu.cache + cidx;
974 #define ALUOP(STORE, NAME, HOW) \
975 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
976 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
977 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
980 #define LOGOP(NAME, HOW) \
981 case O(NAME,SB): HOW; goto log8;\
982 case O(NAME, SW): HOW; goto log16;\
983 case O(NAME,SL): HOW; goto log32;
990 printf ("%x %d %s\n", pc, code->opcode,
991 code->op ? code->op->name : "**");
993 cpu.stats[code->opcode]++;
999 cycles += code->cycles;
1003 switch (code->opcode)
1007 * This opcode is a fake for when we get to an
1008 * instruction which hasnt been compiled
1015 case O (O_SUBX, SB):
1016 rd = fetch (&code->dst);
1017 ea = fetch (&code->src);
1022 case O (O_ADDX, SB):
1023 rd = fetch (&code->dst);
1024 ea = fetch (&code->src);
1029 #define EA ea = fetch(&code->src);
1030 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1032 ALUOP (1, O_SUB, RD_EA;
1035 ALUOP (1, O_NEG, EA;
1041 rd = GET_B_REG (code->dst.reg);
1042 ea = fetch (&code->src);
1046 rd = GET_W_REG (code->dst.reg);
1047 ea = fetch (&code->src);
1051 rd = GET_L_REG (code->dst.reg);
1052 ea = fetch (&code->src);
1057 LOGOP (O_AND, RD_EA;
1063 LOGOP (O_XOR, RD_EA;
1067 case O (O_MOV_TO_MEM, SB):
1068 res = GET_B_REG (code->src.reg);
1070 case O (O_MOV_TO_MEM, SW):
1071 res = GET_W_REG (code->src.reg);
1073 case O (O_MOV_TO_MEM, SL):
1074 res = GET_L_REG (code->src.reg);
1078 case O (O_MOV_TO_REG, SB):
1079 res = fetch (&code->src);
1080 SET_B_REG (code->dst.reg, res);
1081 goto just_flags_log8;
1082 case O (O_MOV_TO_REG, SW):
1083 res = fetch (&code->src);
1084 SET_W_REG (code->dst.reg, res);
1085 goto just_flags_log16;
1086 case O (O_MOV_TO_REG, SL):
1087 res = fetch (&code->src);
1088 SET_L_REG (code->dst.reg, res);
1089 goto just_flags_log32;
1092 case O (O_ADDS, SL):
1093 SET_L_REG (code->dst.reg,
1094 GET_L_REG (code->dst.reg)
1095 + code->src.literal);
1099 case O (O_SUBS, SL):
1100 SET_L_REG (code->dst.reg,
1101 GET_L_REG (code->dst.reg)
1102 - code->src.literal);
1106 rd = fetch (&code->dst);
1107 ea = fetch (&code->src);
1110 goto just_flags_alu8;
1113 rd = fetch (&code->dst);
1114 ea = fetch (&code->src);
1117 goto just_flags_alu16;
1120 rd = fetch (&code->dst);
1121 ea = fetch (&code->src);
1124 goto just_flags_alu32;
1128 rd = GET_B_REG (code->src.reg);
1131 SET_B_REG (code->src.reg, res);
1132 goto just_flags_inc8;
1135 rd = GET_W_REG (code->dst.reg);
1136 ea = -code->src.literal;
1138 SET_W_REG (code->dst.reg, res);
1139 goto just_flags_inc16;
1142 rd = GET_L_REG (code->dst.reg);
1143 ea = -code->src.literal;
1145 SET_L_REG (code->dst.reg, res);
1146 goto just_flags_inc32;
1150 rd = GET_B_REG (code->src.reg);
1153 SET_B_REG (code->src.reg, res);
1154 goto just_flags_inc8;
1157 rd = GET_W_REG (code->dst.reg);
1158 ea = code->src.literal;
1160 SET_W_REG (code->dst.reg, res);
1161 goto just_flags_inc16;
1164 rd = GET_L_REG (code->dst.reg);
1165 ea = code->src.literal;
1167 SET_L_REG (code->dst.reg, res);
1168 goto just_flags_inc32;
1171 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1173 case O (O_ANDC, SB):
1175 ea = code->src.literal;
1181 ea = code->src.literal;
1185 case O (O_XORC, SB):
1187 ea = code->src.literal;
1228 if (((Z || (N ^ V)) == 0))
1234 if (((Z || (N ^ V)) == 1))
1268 case O (O_SYSCALL, SB):
1270 char c = cpu.regs[2];
1271 sim_callback->write_stdout (sim_callback, &c, 1);
1275 ONOT (O_NOT, rd = ~rd; v = 0;);
1277 c = rd & hm; v = 0; rd <<= 1,
1278 c = rd & (hm >> 1); v = 0; rd <<= 2);
1280 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1281 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1283 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1284 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1286 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1287 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1289 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1290 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1292 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1293 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1295 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1296 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1298 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1299 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1303 pc = fetch (&code->src);
1311 pc = fetch (&code->src);
1318 SET_MEMORY_L (tmp, code->next_pc);
1323 SET_MEMORY_W (tmp, code->next_pc);
1330 pc = code->src.literal;
1341 pc = GET_MEMORY_L (tmp);
1346 pc = GET_MEMORY_W (tmp);
1355 cpu.state = SIM_STATE_STOPPED;
1356 cpu.exception = SIGILL;
1358 case O (O_SLEEP, SN):
1359 /* FIXME: Doesn't this break for breakpoints when r0
1360 contains just the right (er, wrong) value? */
1361 cpu.state = SIM_STATE_STOPPED;
1362 /* The format of r0 is defined by target newlib. Expand
1363 the macros here instead of looking for .../sys/wait.h. */
1364 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1365 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1366 if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0]))
1367 cpu.exception = SIGILL;
1369 cpu.exception = SIGTRAP;
1372 cpu.state = SIM_STATE_STOPPED;
1373 cpu.exception = SIGTRAP;
1376 OBITOP (O_BNOT, 1, 1, ea ^= m);
1377 OBITOP (O_BTST, 1, 0, nz = ea & m);
1378 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1379 OBITOP (O_BSET, 1, 1, ea |= m);
1380 OBITOP (O_BLD, 1, 0, c = ea & m);
1381 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1382 OBITOP (O_BST, 1, 1, ea &= ~m;
1384 OBITOP (O_BIST, 1, 1, ea &= ~m;
1386 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1387 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1388 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1389 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1390 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1391 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1393 #define MOP(bsize, signed) \
1394 mop (code, bsize, signed); \
1397 case O (O_MULS, SB):
1400 case O (O_MULS, SW):
1403 case O (O_MULU, SB):
1406 case O (O_MULU, SW):
1411 case O (O_DIVU, SB):
1413 rd = GET_W_REG (code->dst.reg);
1414 ea = GET_B_REG (code->src.reg);
1417 tmp = (unsigned) rd % ea;
1418 rd = (unsigned) rd / ea;
1420 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1426 case O (O_DIVU, SW):
1428 rd = GET_L_REG (code->dst.reg);
1429 ea = GET_W_REG (code->src.reg);
1434 tmp = (unsigned) rd % ea;
1435 rd = (unsigned) rd / ea;
1437 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1441 case O (O_DIVS, SB):
1444 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1445 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1448 tmp = (int) rd % (int) ea;
1449 rd = (int) rd / (int) ea;
1455 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1458 case O (O_DIVS, SW):
1460 rd = GET_L_REG (code->dst.reg);
1461 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1464 tmp = (int) rd % (int) ea;
1465 rd = (int) rd / (int) ea;
1466 n = rd & 0x80000000;
1471 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1474 case O (O_EXTS, SW):
1475 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1476 ea = rd & 0x80 ? -256 : 0;
1479 case O (O_EXTS, SL):
1480 rd = GET_W_REG (code->src.reg) & 0xffff;
1481 ea = rd & 0x8000 ? -65536 : 0;
1484 case O (O_EXTU, SW):
1485 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1489 case O (O_EXTU, SL):
1490 rd = GET_W_REG (code->src.reg) & 0xffff;
1500 int nregs, firstreg, i;
1502 nregs = GET_MEMORY_B (pc + 1);
1505 firstreg = GET_MEMORY_B (pc + 3);
1507 for (i = firstreg; i <= firstreg + nregs; i++)
1510 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1517 int nregs, firstreg, i;
1519 nregs = GET_MEMORY_B (pc + 1);
1522 firstreg = GET_MEMORY_B (pc + 3);
1524 for (i = firstreg; i >= firstreg - nregs; i--)
1526 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1533 cpu.state = SIM_STATE_STOPPED;
1534 cpu.exception = SIGILL;
1546 /* When a branch works */
1547 pc = code->src.literal;
1550 /* Set the cond codes from res */
1553 /* Set the flags after an 8 bit inc/dec operation */
1557 v = (rd & 0x7f) == 0x7f;
1561 /* Set the flags after an 16 bit inc/dec operation */
1565 v = (rd & 0x7fff) == 0x7fff;
1569 /* Set the flags after an 32 bit inc/dec operation */
1571 n = res & 0x80000000;
1572 nz = res & 0xffffffff;
1573 v = (rd & 0x7fffffff) == 0x7fffffff;
1578 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1581 SET_B_REG (code->src.reg, rd);
1585 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1588 SET_W_REG (code->src.reg, rd);
1592 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1593 n = (rd & 0x80000000);
1594 nz = rd & 0xffffffff;
1595 SET_L_REG (code->src.reg, rd);
1599 store (&code->dst, res);
1601 /* flags after a 32bit logical operation */
1602 n = res & 0x80000000;
1603 nz = res & 0xffffffff;
1608 store (&code->dst, res);
1610 /* flags after a 16bit logical operation */
1618 store (&code->dst, res);
1626 SET_B_REG (code->dst.reg, res);
1631 switch (code->opcode / 4)
1634 v = ((rd & 0x80) == (ea & 0x80)
1635 && (rd & 0x80) != (res & 0x80));
1639 v = ((rd & 0x80) != (-ea & 0x80)
1640 && (rd & 0x80) != (res & 0x80));
1649 SET_W_REG (code->dst.reg, res);
1653 c = (res & 0x10000);
1654 switch (code->opcode / 4)
1657 v = ((rd & 0x8000) == (ea & 0x8000)
1658 && (rd & 0x8000) != (res & 0x8000));
1662 v = ((rd & 0x8000) != (-ea & 0x8000)
1663 && (rd & 0x8000) != (res & 0x8000));
1672 SET_L_REG (code->dst.reg, res);
1674 n = res & 0x80000000;
1675 nz = res & 0xffffffff;
1676 switch (code->opcode / 4)
1679 v = ((rd & 0x80000000) == (ea & 0x80000000)
1680 && (rd & 0x80000000) != (res & 0x80000000));
1681 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1685 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1686 && (rd & 0x80000000) != (res & 0x80000000));
1687 c = (unsigned) rd < (unsigned) -ea;
1690 v = (rd == 0x80000000);
1706 if (--poll_count < 0)
1708 poll_count = POLL_QUIT_INTERVAL;
1709 if ((*sim_callback->poll_quit) != NULL
1710 && (*sim_callback->poll_quit) (sim_callback))
1715 while (cpu.state == SIM_STATE_RUNNING);
1716 cpu.ticks += get_now () - tick_start;
1717 cpu.cycles += cycles;
1723 signal (SIGINT, prev);
1730 /* FIXME: Unfinished. */
1735 sim_write (sd, addr, buffer, size)
1738 unsigned char *buffer;
1746 for (i = 0; i < size; i++)
1748 if (addr < memory_size)
1750 cpu.memory[addr + i] = buffer[i];
1751 cpu.cache_idx[addr + i] = 0;
1754 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1760 sim_read (sd, addr, buffer, size)
1763 unsigned char *buffer;
1769 if (addr < memory_size)
1770 memcpy (buffer, cpu.memory + addr, size);
1772 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1786 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1787 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1790 #define CCR_REGNUM 8 /* Contains processor status */
1791 #define PC_REGNUM 9 /* Contains program counter */
1793 #define CYCLE_REGNUM 10
1794 #define INST_REGNUM 11
1795 #define TICK_REGNUM 12
1799 sim_store_register (sd, rn, value, length)
1802 unsigned char *value;
1808 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1809 shortval = (value[0] << 8) | (value[1]);
1810 intval = h8300hmode ? longval : shortval;
1828 cpu.regs[rn] = intval;
1834 cpu.cycles = longval;
1838 cpu.insts = longval;
1842 cpu.ticks = longval;
1849 sim_fetch_register (sd, rn, buf, length)
1893 if (h8300hmode || longreg)
1909 sim_stop_reason (sd, reason, sigrc)
1911 enum sim_stop *reason;
1914 #if 0 /* FIXME: This should work but we can't use it.
1915 grep for SLEEP above. */
1918 case SIM_STATE_EXITED : *reason = sim_exited; break;
1919 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1920 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1924 *reason = sim_stopped;
1926 *sigrc = cpu.exception;
1929 /* FIXME: Rename to sim_set_mem_size. */
1935 /* Memory size is fixed. */
1939 sim_set_simcache_size (n)
1945 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1946 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1952 sim_info (sd, verbose)
1956 double timetaken = (double) cpu.ticks / (double) now_persec ();
1957 double virttime = cpu.cycles / 10.0e6;
1959 (*sim_callback->printf_filtered) (sim_callback,
1960 "\n\n#instructions executed %10d\n",
1962 (*sim_callback->printf_filtered) (sim_callback,
1963 "#cycles (v approximate) %10d\n",
1965 (*sim_callback->printf_filtered) (sim_callback,
1966 "#real time taken %10.4f\n",
1968 (*sim_callback->printf_filtered) (sim_callback,
1969 "#virtual time taked %10.4f\n",
1971 if (timetaken != 0.0)
1972 (*sim_callback->printf_filtered) (sim_callback,
1973 "#simulation ratio %10.4f\n",
1974 virttime / timetaken);
1975 (*sim_callback->printf_filtered) (sim_callback,
1978 (*sim_callback->printf_filtered) (sim_callback,
1979 "#cache size %10d\n",
1983 /* This to be conditional on `what' (aka `verbose'),
1984 however it was never passed as non-zero. */
1988 for (i = 0; i < O_LAST; i++)
1991 (*sim_callback->printf_filtered) (sim_callback,
1992 "%d: %d\n", i, cpu.stats[i]);
1998 /* Indicate whether the cpu is an H8/300 or H8/300H.
1999 FLAG is non-zero for the H8/300H. */
2005 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2006 This function being replaced by a sim_open:ARGV configuration
2012 sim_open (kind, ptr, abfd, argv)
2014 struct host_callback_struct *ptr;
2018 /* FIXME: Much of the code in sim_load can be moved here. */
2023 /* Fudge our descriptor. */
2024 return (SIM_DESC) 1;
2028 sim_close (sd, quitting)
2032 /* Nothing to do. */
2035 /* Called by gdb to load a program into memory. */
2038 sim_load (sd, prog, abfd, from_tty)
2046 /* FIXME: The code below that sets a specific variant of the H8/300
2047 being simulated should be moved to sim_open(). */
2049 /* See if the file is for the H8/300 or H8/300H. */
2050 /* ??? This may not be the most efficient way. The z8k simulator
2051 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2055 prog_bfd = bfd_openr (prog, "coff-h8300");
2056 if (prog_bfd != NULL)
2058 /* Set the cpu type. We ignore failure from bfd_check_format
2059 and bfd_openr as sim_load_file checks too. */
2060 if (bfd_check_format (prog_bfd, bfd_object))
2062 unsigned long mach = bfd_get_mach (prog_bfd);
2063 set_h8300h (mach == bfd_mach_h8300h
2064 || mach == bfd_mach_h8300s);
2068 /* If we're using gdb attached to the simulator, then we have to
2069 reallocate memory for the simulator.
2071 When gdb first starts, it calls fetch_registers (among other
2072 functions), which in turn calls init_pointers, which allocates
2075 The problem is when we do that, we don't know whether we're
2076 debugging an H8/300 or H8/300H program.
2078 This is the first point at which we can make that determination,
2079 so we just reallocate memory now; this will also allow us to handle
2080 switching between H8/300 and H8/300H programs without exiting
2083 memory_size = H8300H_MSIZE;
2085 memory_size = H8300_MSIZE;
2090 free (cpu.cache_idx);
2092 free (cpu.eightbit);
2094 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2095 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2096 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2098 /* `msize' must be a power of two. */
2099 if ((memory_size & (memory_size - 1)) != 0)
2101 cpu.mask = memory_size - 1;
2103 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2104 sim_kind == SIM_OPEN_DEBUG,
2108 /* Close the bfd if we opened it. */
2109 if (abfd == NULL && prog_bfd != NULL)
2110 bfd_close (prog_bfd);
2114 /* Close the bfd if we opened it. */
2115 if (abfd == NULL && prog_bfd != NULL)
2116 bfd_close (prog_bfd);
2121 sim_create_inferior (sd, abfd, argv, env)
2128 cpu.pc = bfd_get_start_address (abfd);
2135 sim_do_command (sd, cmd)
2139 (*sim_callback->printf_filtered) (sim_callback,
2140 "This simulator does not accept any commands.\n");
2144 sim_set_callbacks (ptr)
2145 struct host_callback_struct *ptr;