2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
36 #include "remote-sim.h"
44 host_callback *sim_callback;
46 static SIM_OPEN_KIND sim_kind;
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
53 void sim_set_simcache_size PARAMS ((int));
55 #define X(op, size) op*4+size
57 #define SP (h8300hmode ? SL:SW)
70 #define h8_opcodes ops
72 #include "opcode/h8300.h"
76 /* The rate at which to call the host's poll_quit callback. */
78 #define POLL_QUIT_INTERVAL 0x80000
80 #define LOW_BYTE(x) ((x) & 0xff)
81 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
82 #define P(X,Y) ((X<<8) | Y)
84 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
87 c = (cpu.ccr >> 0) & 1;\
88 v = (cpu.ccr >> 1) & 1;\
89 nz = !((cpu.ccr >> 2) & 1);\
90 n = (cpu.ccr >> 3) & 1;
92 #ifdef __CHAR_IS_SIGNED__
93 #define SEXTCHAR(x) ((char)(x))
97 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
100 #define UEXTCHAR(x) ((x) & 0xff)
101 #define UEXTSHORT(x) ((x) & 0xffff)
102 #define SEXTSHORT(x) ((short)(x))
104 static cpu_state_type cpu;
109 static int memory_size;
138 return h8300hmode ? SL : SW;
150 return X (OP_IMM, SP);
152 return X (OP_REG, SP);
155 return X (OP_MEM, SP);
163 decode (addr, data, dst)
181 /* Find the exact opcode/arg combo. */
182 for (q = h8_opcodes; q->name; q++)
184 op_type *nib = q->data.nib;
185 unsigned int len = 0;
189 op_type looking_for = *nib;
190 int thisnib = data[len >> 1];
192 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
194 if (looking_for < 16 && looking_for >= 0)
196 if (looking_for != thisnib)
201 if ((int) looking_for & (int) B31)
203 if (!(((int) thisnib & 0x8) != 0))
206 looking_for = (op_type) ((int) looking_for & ~(int) B31);
210 if ((int) looking_for & (int) B30)
212 if (!(((int) thisnib & 0x8) == 0))
215 looking_for = (op_type) ((int) looking_for & ~(int) B30);
218 if (looking_for & DBIT)
220 /* Exclude adds/subs by looking at bit 0 and 2, and
221 make sure the operand size, either w or l,
222 matches by looking at bit 1. */
223 if ((looking_for & 7) != (thisnib & 7))
226 abs = (thisnib & 0x8) ? 2 : 1;
228 else if (looking_for & (REG | IND | INC | DEC))
230 if (looking_for & REG)
232 /* Can work out size from the register. */
233 size = bitfrom (looking_for);
235 if (looking_for & SRC)
240 else if (looking_for & L_16)
242 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
244 if (looking_for & (PCREL | DISP))
249 else if (looking_for & ABSJMP)
251 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
253 else if (looking_for & MEMIND)
257 else if (looking_for & L_32)
261 abs = (data[i] << 24)
262 | (data[i + 1] << 16)
268 else if (looking_for & L_24)
272 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
275 else if (looking_for & IGNORE)
279 else if (looking_for & DISPREG)
281 rdisp = thisnib & 0x7;
283 else if (looking_for & KBIT)
300 else if (looking_for & L_8)
304 if (looking_for & PCREL)
306 abs = SEXTCHAR (data[len >> 1]);
308 else if (looking_for & ABS8MEM)
311 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
312 abs |= data[len >> 1] & 0xff;
316 abs = data[len >> 1] & 0xff;
319 else if (looking_for & L_3)
325 else if (looking_for == E)
329 /* Fill in the args. */
331 op_type *args = q->args.nib;
337 int rn = (x & DST) ? rd : rs;
347 p->type = X (OP_IMM, size);
350 else if (x & (IMM | KBIT | DBIT))
352 p->type = X (OP_IMM, size);
358 Some ops (like mul) have two sizes. */
361 p->type = X (OP_REG, size);
366 p->type = X (OP_INC, size);
371 p->type = X (OP_DEC, size);
376 p->type = X (OP_DISP, size);
380 else if (x & (ABS | ABSJMP | ABS8MEM))
382 p->type = X (OP_DISP, size);
388 p->type = X (OP_MEM, size);
393 p->type = X (OP_PCREL, size);
394 p->literal = abs + addr + 2;
400 p->type = X (OP_IMM, SP);
405 p->type = X (OP_DISP, size);
407 p->reg = rdisp & 0x7;
414 printf ("Hmmmm %x", x);
420 /* But a jmp or a jsr gets automagically lvalued,
421 since we branch to their address not their
423 if (q->how == O (O_JSR, SB)
424 || q->how == O (O_JMP, SB))
426 dst->src.type = lvalue (dst->src.type, dst->src.reg);
429 if (dst->dst.type == -1)
432 dst->opcode = q->how;
433 dst->cycles = q->time;
435 /* And a jsr to 0xc4 is turned into a magic trap. */
437 if (dst->opcode == O (O_JSR, SB))
439 if (dst->src.literal == 0xc4)
441 dst->opcode = O (O_SYSCALL, SB);
445 dst->next_pc = addr + len / 2;
449 printf ("Don't understand %x \n", looking_for);
460 /* Fell off the end. */
461 dst->opcode = O (O_ILL, SB);
469 /* Find the next cache entry to use. */
470 idx = cpu.cache_top + 1;
472 if (idx >= cpu.csize)
478 /* Throw away its old meaning. */
479 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
481 /* Set to new address. */
482 cpu.cache[idx].oldpc = pc;
484 /* Fill in instruction info. */
485 decode (pc, cpu.memory + pc, cpu.cache + idx);
487 /* Point to new cache entry. */
488 cpu.cache_idx[pc] = idx;
492 static unsigned char *breg[18];
493 static unsigned short *wreg[18];
494 static unsigned int *lreg[18];
496 #define GET_B_REG(x) *(breg[x])
497 #define SET_B_REG(x,y) (*(breg[x])) = (y)
498 #define GET_W_REG(x) *(wreg[x])
499 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
501 #define GET_L_REG(x) *(lreg[x])
502 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
504 #define GET_MEMORY_L(x) \
506 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
507 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
508 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
509 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
511 #define GET_MEMORY_W(x) \
513 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
514 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
517 #define GET_MEMORY_B(x) \
518 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
520 #define SET_MEMORY_L(x,y) \
521 { register unsigned char *_p; register int __y = y; \
522 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
523 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
524 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
526 #define SET_MEMORY_W(x,y) \
527 { register unsigned char *_p; register int __y = y; \
528 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
529 _p[0] = (__y)>>8; _p[1] =(__y);}
531 #define SET_MEMORY_B(x,y) \
532 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
539 int abs = arg->literal;
546 return GET_B_REG (rn);
548 return GET_W_REG (rn);
550 return GET_L_REG (rn);
561 r = GET_MEMORY_B (t);
570 r = GET_MEMORY_W (t);
578 r = GET_MEMORY_L (t);
585 case X (OP_DISP, SB):
586 t = GET_L_REG (rn) + abs;
588 return GET_MEMORY_B (t);
590 case X (OP_DISP, SW):
591 t = GET_L_REG (rn) + abs;
593 return GET_MEMORY_W (t);
595 case X (OP_DISP, SL):
596 t = GET_L_REG (rn) + abs;
598 return GET_MEMORY_L (t);
601 t = GET_MEMORY_L (abs);
606 t = GET_MEMORY_W (abs);
624 int abs = arg->literal;
640 t = GET_L_REG (rn) - 1;
647 t = (GET_L_REG (rn) - 2) & cpu.mask;
653 t = (GET_L_REG (rn) - 4) & cpu.mask;
658 case X (OP_DISP, SB):
659 t = GET_L_REG (rn) + abs;
664 case X (OP_DISP, SW):
665 t = GET_L_REG (rn) + abs;
670 case X (OP_DISP, SL):
671 t = GET_L_REG (rn) + abs;
708 memory_size = H8300H_MSIZE;
710 memory_size = H8300_MSIZE;
711 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
712 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
713 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
715 /* `msize' must be a power of two. */
716 if ((memory_size & (memory_size - 1)) != 0)
718 cpu.mask = memory_size - 1;
720 for (i = 0; i < 9; i++)
725 for (i = 0; i < 8; i++)
727 unsigned char *p = (unsigned char *) (cpu.regs + i);
728 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
729 unsigned short *q = (unsigned short *) (cpu.regs + i);
730 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
731 cpu.regs[i] = 0x00112233;
757 lreg[i] = &cpu.regs[i];
760 lreg[8] = &cpu.regs[8];
762 /* Initialize the seg registers. */
764 sim_set_simcache_size (CSIZE);
769 control_c (sig, code, scp, addr)
775 cpu.state = SIM_STATE_STOPPED;
776 cpu.exception = SIGINT;
785 mop (code, bsize, sign)
798 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
799 SEXTSHORT (GET_W_REG (code->dst.reg));
801 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
802 SEXTSHORT (GET_W_REG (code->src.reg));
806 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
807 UEXTSHORT (GET_W_REG (code->dst.reg));
809 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
810 UEXTSHORT (GET_W_REG (code->src.reg));
813 result = multiplier * multiplicand;
817 n = result & (bsize ? 0x8000 : 0x80000000);
818 nz = result & (bsize ? 0xffff : 0xffffffff);
822 SET_W_REG (code->dst.reg, result);
826 SET_L_REG (code->dst.reg, result);
828 /* return ((n==1) << 1) | (nz==1); */
832 #define ONOT(name, how) \
837 rd = GET_B_REG (code->src.reg); \
845 rd = GET_W_REG (code->src.reg); \
852 int hm = 0x80000000; \
853 rd = GET_L_REG (code->src.reg); \
858 #define OSHIFTS(name, how1, how2) \
863 rd = GET_B_REG (code->src.reg); \
864 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
878 rd = GET_W_REG (code->src.reg); \
879 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
892 int hm = 0x80000000; \
893 rd = GET_L_REG (code->src.reg); \
894 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
905 #define OBITOP(name,f, s, op) \
910 if (f) ea = fetch (&code->dst); \
911 m=1<< fetch(&code->src); \
913 if(s) store (&code->dst,ea); goto next; \
920 cpu.state = SIM_STATE_STOPPED;
921 cpu.exception = SIGINT;
926 sim_resume (sd, step, siggnal)
932 int tick_start = get_now ();
945 prev = signal (SIGINT, control_c);
949 cpu.state = SIM_STATE_STOPPED;
950 cpu.exception = SIGTRAP;
954 cpu.state = SIM_STATE_RUNNING;
960 /* The PC should never be odd. */
974 cidx = cpu.cache_idx[pc];
975 code = cpu.cache + cidx;
978 #define ALUOP(STORE, NAME, HOW) \
979 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
980 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
981 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
984 #define LOGOP(NAME, HOW) \
985 case O(NAME,SB): HOW; goto log8;\
986 case O(NAME, SW): HOW; goto log16;\
987 case O(NAME,SL): HOW; goto log32;
994 printf ("%x %d %s\n", pc, code->opcode,
995 code->op ? code->op->name : "**");
997 cpu.stats[code->opcode]++;
1001 cycles += code->cycles;
1003 switch (code->opcode)
1007 * This opcode is a fake for when we get to an
1008 * instruction which hasnt been compiled
1015 case O (O_SUBX, SB):
1016 rd = fetch (&code->dst);
1017 ea = fetch (&code->src);
1022 case O (O_ADDX, SB):
1023 rd = fetch (&code->dst);
1024 ea = fetch (&code->src);
1029 #define EA ea = fetch(&code->src);
1030 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1032 ALUOP (1, O_SUB, RD_EA;
1035 ALUOP (1, O_NEG, EA;
1041 rd = GET_B_REG (code->dst.reg);
1042 ea = fetch (&code->src);
1046 rd = GET_W_REG (code->dst.reg);
1047 ea = fetch (&code->src);
1051 rd = GET_L_REG (code->dst.reg);
1052 ea = fetch (&code->src);
1057 LOGOP (O_AND, RD_EA;
1063 LOGOP (O_XOR, RD_EA;
1067 case O (O_MOV_TO_MEM, SB):
1068 res = GET_B_REG (code->src.reg);
1070 case O (O_MOV_TO_MEM, SW):
1071 res = GET_W_REG (code->src.reg);
1073 case O (O_MOV_TO_MEM, SL):
1074 res = GET_L_REG (code->src.reg);
1078 case O (O_MOV_TO_REG, SB):
1079 res = fetch (&code->src);
1080 SET_B_REG (code->dst.reg, res);
1081 goto just_flags_log8;
1082 case O (O_MOV_TO_REG, SW):
1083 res = fetch (&code->src);
1084 SET_W_REG (code->dst.reg, res);
1085 goto just_flags_log16;
1086 case O (O_MOV_TO_REG, SL):
1087 res = fetch (&code->src);
1088 SET_L_REG (code->dst.reg, res);
1089 goto just_flags_log32;
1092 case O (O_ADDS, SL):
1093 SET_L_REG (code->dst.reg,
1094 GET_L_REG (code->dst.reg)
1095 + code->src.literal);
1099 case O (O_SUBS, SL):
1100 SET_L_REG (code->dst.reg,
1101 GET_L_REG (code->dst.reg)
1102 - code->src.literal);
1106 rd = fetch (&code->dst);
1107 ea = fetch (&code->src);
1110 goto just_flags_alu8;
1113 rd = fetch (&code->dst);
1114 ea = fetch (&code->src);
1117 goto just_flags_alu16;
1120 rd = fetch (&code->dst);
1121 ea = fetch (&code->src);
1124 goto just_flags_alu32;
1128 rd = GET_B_REG (code->src.reg);
1131 SET_B_REG (code->src.reg, res);
1132 goto just_flags_inc8;
1135 rd = GET_W_REG (code->dst.reg);
1136 ea = -code->src.literal;
1138 SET_W_REG (code->dst.reg, res);
1139 goto just_flags_inc16;
1142 rd = GET_L_REG (code->dst.reg);
1143 ea = -code->src.literal;
1145 SET_L_REG (code->dst.reg, res);
1146 goto just_flags_inc32;
1150 rd = GET_B_REG (code->src.reg);
1153 SET_B_REG (code->src.reg, res);
1154 goto just_flags_inc8;
1157 rd = GET_W_REG (code->dst.reg);
1158 ea = code->src.literal;
1160 SET_W_REG (code->dst.reg, res);
1161 goto just_flags_inc16;
1164 rd = GET_L_REG (code->dst.reg);
1165 ea = code->src.literal;
1167 SET_L_REG (code->dst.reg, res);
1168 goto just_flags_inc32;
1171 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1173 case O (O_ANDC, SB):
1175 ea = code->src.literal;
1181 ea = code->src.literal;
1185 case O (O_XORC, SB):
1187 ea = code->src.literal;
1228 if (((Z || (N ^ V)) == 0))
1234 if (((Z || (N ^ V)) == 1))
1268 case O (O_SYSCALL, SB):
1270 char c = cpu.regs[2];
1271 sim_callback->write_stdout (sim_callback, &c, 1);
1275 ONOT (O_NOT, rd = ~rd; v = 0;);
1277 c = rd & hm; v = 0; rd <<= 1,
1278 c = rd & (hm >> 1); v = 0; rd <<= 2);
1280 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1281 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1283 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1284 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1286 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1287 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1289 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1290 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1292 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1293 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1295 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1296 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1298 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1299 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1303 pc = fetch (&code->src);
1311 pc = fetch (&code->src);
1318 SET_MEMORY_L (tmp, code->next_pc);
1323 SET_MEMORY_W (tmp, code->next_pc);
1330 pc = code->src.literal;
1341 pc = GET_MEMORY_L (tmp);
1346 pc = GET_MEMORY_W (tmp);
1355 cpu.state = SIM_STATE_STOPPED;
1356 cpu.exception = SIGILL;
1358 case O (O_SLEEP, SN):
1359 /* FIXME: Doesn't this break for breakpoints when r0
1360 contains just the right (er, wrong) value? */
1361 cpu.state = SIM_STATE_STOPPED;
1362 /* The format of r0 is defined by target newlib. Expand
1363 the macros here instead of looking for .../sys/wait.h. */
1364 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1365 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1366 if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0]))
1367 cpu.exception = SIGILL;
1369 cpu.exception = SIGTRAP;
1372 cpu.state = SIM_STATE_STOPPED;
1373 cpu.exception = SIGTRAP;
1376 OBITOP (O_BNOT, 1, 1, ea ^= m);
1377 OBITOP (O_BTST, 1, 0, nz = ea & m);
1378 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1379 OBITOP (O_BSET, 1, 1, ea |= m);
1380 OBITOP (O_BLD, 1, 0, c = ea & m);
1381 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1382 OBITOP (O_BST, 1, 1, ea &= ~m;
1384 OBITOP (O_BIST, 1, 1, ea &= ~m;
1386 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1387 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1388 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1389 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1390 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1391 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1394 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1396 case O (O_MULS, SB):
1399 case O (O_MULS, SW):
1402 case O (O_MULU, SB):
1405 case O (O_MULU, SW):
1410 case O (O_DIVU, SB):
1412 rd = GET_W_REG (code->dst.reg);
1413 ea = GET_B_REG (code->src.reg);
1416 tmp = (unsigned)rd % ea;
1417 rd = (unsigned)rd / ea;
1419 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1425 case O (O_DIVU, SW):
1427 rd = GET_L_REG (code->dst.reg);
1428 ea = GET_W_REG (code->src.reg);
1433 tmp = (unsigned)rd % ea;
1434 rd = (unsigned)rd / ea;
1436 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1440 case O (O_DIVS, SB):
1443 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1444 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1447 tmp = (int) rd % (int) ea;
1448 rd = (int) rd / (int) ea;
1454 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1457 case O (O_DIVS, SW):
1459 rd = GET_L_REG (code->dst.reg);
1460 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1463 tmp = (int) rd % (int) ea;
1464 rd = (int) rd / (int) ea;
1465 n = rd & 0x80000000;
1470 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1473 case O (O_EXTS, SW):
1474 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1475 ea = rd & 0x80 ? -256 : 0;
1478 case O (O_EXTS, SL):
1479 rd = GET_W_REG (code->src.reg) & 0xffff;
1480 ea = rd & 0x8000 ? -65536 : 0;
1483 case O (O_EXTU, SW):
1484 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1488 case O (O_EXTU, SL):
1489 rd = GET_W_REG (code->src.reg) & 0xffff;
1499 int nregs, firstreg, i;
1501 nregs = GET_MEMORY_B (pc + 1);
1504 firstreg = GET_MEMORY_B (pc + 3);
1506 for (i = firstreg; i <= firstreg + nregs; i++)
1509 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1516 int nregs, firstreg, i;
1518 nregs = GET_MEMORY_B (pc + 1);
1521 firstreg = GET_MEMORY_B (pc + 3);
1523 for (i = firstreg; i >= firstreg - nregs; i--)
1525 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1532 cpu.state = SIM_STATE_STOPPED;
1533 cpu.exception = SIGILL;
1545 /* When a branch works */
1546 pc = code->src.literal;
1549 /* Set the cond codes from res */
1552 /* Set the flags after an 8 bit inc/dec operation */
1556 v = (rd & 0x7f) == 0x7f;
1560 /* Set the flags after an 16 bit inc/dec operation */
1564 v = (rd & 0x7fff) == 0x7fff;
1568 /* Set the flags after an 32 bit inc/dec operation */
1570 n = res & 0x80000000;
1571 nz = res & 0xffffffff;
1572 v = (rd & 0x7fffffff) == 0x7fffffff;
1577 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1580 SET_B_REG (code->src.reg, rd);
1584 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1587 SET_W_REG (code->src.reg, rd);
1591 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1592 n = (rd & 0x80000000);
1593 nz = rd & 0xffffffff;
1594 SET_L_REG (code->src.reg, rd);
1598 store (&code->dst, res);
1600 /* flags after a 32bit logical operation */
1601 n = res & 0x80000000;
1602 nz = res & 0xffffffff;
1607 store (&code->dst, res);
1609 /* flags after a 16bit logical operation */
1617 store (&code->dst, res);
1625 SET_B_REG (code->dst.reg, res);
1630 switch (code->opcode / 4)
1633 v = ((rd & 0x80) == (ea & 0x80)
1634 && (rd & 0x80) != (res & 0x80));
1638 v = ((rd & 0x80) != (-ea & 0x80)
1639 && (rd & 0x80) != (res & 0x80));
1648 SET_W_REG (code->dst.reg, res);
1652 c = (res & 0x10000);
1653 switch (code->opcode / 4)
1656 v = ((rd & 0x8000) == (ea & 0x8000)
1657 && (rd & 0x8000) != (res & 0x8000));
1661 v = ((rd & 0x8000) != (-ea & 0x8000)
1662 && (rd & 0x8000) != (res & 0x8000));
1671 SET_L_REG (code->dst.reg, res);
1673 n = res & 0x80000000;
1674 nz = res & 0xffffffff;
1675 switch (code->opcode / 4)
1678 v = ((rd & 0x80000000) == (ea & 0x80000000)
1679 && (rd & 0x80000000) != (res & 0x80000000));
1680 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1684 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1685 && (rd & 0x80000000) != (res & 0x80000000));
1686 c = (unsigned) rd < (unsigned) -ea;
1689 v = (rd == 0x80000000);
1700 /* if (cpu.regs[8] ) abort(); */
1702 if (--poll_count < 0)
1704 poll_count = POLL_QUIT_INTERVAL;
1705 if ((*sim_callback->poll_quit) != NULL
1706 && (*sim_callback->poll_quit) (sim_callback))
1711 while (cpu.state == SIM_STATE_RUNNING);
1712 cpu.ticks += get_now () - tick_start;
1713 cpu.cycles += cycles;
1719 signal (SIGINT, prev);
1726 /* FIXME: Unfinished. */
1731 sim_write (sd, addr, buffer, size)
1734 unsigned char *buffer;
1742 for (i = 0; i < size; i++)
1744 if (addr < memory_size)
1746 cpu.memory[addr + i] = buffer[i];
1747 cpu.cache_idx[addr + i] = 0;
1750 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1756 sim_read (sd, addr, buffer, size)
1759 unsigned char *buffer;
1765 if (addr < memory_size)
1766 memcpy (buffer, cpu.memory + addr, size);
1768 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1782 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1783 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1786 #define CCR_REGNUM 8 /* Contains processor status */
1787 #define PC_REGNUM 9 /* Contains program counter */
1789 #define CYCLE_REGNUM 10
1790 #define INST_REGNUM 11
1791 #define TICK_REGNUM 12
1795 sim_store_register (sd, rn, value, length)
1798 unsigned char *value;
1804 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1805 shortval = (value[0] << 8) | (value[1]);
1806 intval = h8300hmode ? longval : shortval;
1824 cpu.regs[rn] = intval;
1830 cpu.cycles = longval;
1834 cpu.insts = longval;
1838 cpu.ticks = longval;
1845 sim_fetch_register (sd, rn, buf, length)
1889 if (h8300hmode || longreg)
1905 sim_stop_reason (sd, reason, sigrc)
1907 enum sim_stop *reason;
1910 #if 0 /* FIXME: This should work but we can't use it.
1911 grep for SLEEP above. */
1914 case SIM_STATE_EXITED : *reason = sim_exited; break;
1915 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1916 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1920 *reason = sim_stopped;
1922 *sigrc = cpu.exception;
1925 /* FIXME: Rename to sim_set_mem_size. */
1931 /* Memory size is fixed. */
1935 sim_set_simcache_size (n)
1941 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1942 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1948 sim_info (sd, verbose)
1952 double timetaken = (double) cpu.ticks / (double) now_persec ();
1953 double virttime = cpu.cycles / 10.0e6;
1955 (*sim_callback->printf_filtered) (sim_callback,
1956 "\n\n#instructions executed %10d\n",
1958 (*sim_callback->printf_filtered) (sim_callback,
1959 "#cycles (v approximate) %10d\n",
1961 (*sim_callback->printf_filtered) (sim_callback,
1962 "#real time taken %10.4f\n",
1964 (*sim_callback->printf_filtered) (sim_callback,
1965 "#virtual time taked %10.4f\n",
1967 if (timetaken != 0.0)
1968 (*sim_callback->printf_filtered) (sim_callback,
1969 "#simulation ratio %10.4f\n",
1970 virttime / timetaken);
1971 (*sim_callback->printf_filtered) (sim_callback,
1974 (*sim_callback->printf_filtered) (sim_callback,
1975 "#cache size %10d\n",
1979 /* This to be conditional on `what' (aka `verbose'),
1980 however it was never passed as non-zero. */
1984 for (i = 0; i < O_LAST; i++)
1987 (*sim_callback->printf_filtered) (sim_callback,
1988 "%d: %d\n", i, cpu.stats[i]);
1994 /* Indicate whether the cpu is an H8/300 or H8/300H.
1995 FLAG is non-zero for the H8/300H. */
2001 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2002 This function being replaced by a sim_open:ARGV configuration
2008 sim_open (kind, ptr, abfd, argv)
2010 struct host_callback_struct *ptr;
2014 /* FIXME: Much of the code in sim_load can be moved here. */
2019 /* Fudge our descriptor. */
2020 return (SIM_DESC) 1;
2024 sim_close (sd, quitting)
2028 /* Nothing to do. */
2031 /* Called by gdb to load a program into memory. */
2034 sim_load (sd, prog, abfd, from_tty)
2042 /* FIXME: The code below that sets a specific variant of the H8/300
2043 being simulated should be moved to sim_open(). */
2045 /* See if the file is for the H8/300 or H8/300H. */
2046 /* ??? This may not be the most efficient way. The z8k simulator
2047 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2051 prog_bfd = bfd_openr (prog, "coff-h8300");
2052 if (prog_bfd != NULL)
2054 /* Set the cpu type. We ignore failure from bfd_check_format
2055 and bfd_openr as sim_load_file checks too. */
2056 if (bfd_check_format (prog_bfd, bfd_object))
2058 unsigned long mach = bfd_get_mach (prog_bfd);
2059 set_h8300h (mach == bfd_mach_h8300h
2060 || mach == bfd_mach_h8300s);
2064 /* If we're using gdb attached to the simulator, then we have to
2065 reallocate memory for the simulator.
2067 When gdb first starts, it calls fetch_registers (among other
2068 functions), which in turn calls init_pointers, which allocates
2071 The problem is when we do that, we don't know whether we're
2072 debugging an H8/300 or H8/300H program.
2074 This is the first point at which we can make that determination,
2075 so we just reallocate memory now; this will also allow us to handle
2076 switching between H8/300 and H8/300H programs without exiting
2079 memory_size = H8300H_MSIZE;
2081 memory_size = H8300_MSIZE;
2086 free (cpu.cache_idx);
2088 free (cpu.eightbit);
2090 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2091 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2092 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2094 /* `msize' must be a power of two. */
2095 if ((memory_size & (memory_size - 1)) != 0)
2097 cpu.mask = memory_size - 1;
2099 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2100 sim_kind == SIM_OPEN_DEBUG,
2104 /* Close the bfd if we opened it. */
2105 if (abfd == NULL && prog_bfd != NULL)
2106 bfd_close (prog_bfd);
2110 /* Close the bfd if we opened it. */
2111 if (abfd == NULL && prog_bfd != NULL)
2112 bfd_close (prog_bfd);
2117 sim_create_inferior (sd, abfd, argv, env)
2124 cpu.pc = bfd_get_start_address (abfd);
2131 sim_do_command (sd, cmd)
2135 (*sim_callback->printf_filtered) (sim_callback,
2136 "This simulator does not accept any commands.\n");
2140 sim_set_callbacks (ptr)
2141 struct host_callback_struct *ptr;