2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
29 #include <sys/param.h>
34 #include "remote-sim.h"
38 host_callback *sim_callback;
40 static SIM_OPEN_KIND sim_kind;
43 /* FIXME: Needs to live in header file.
44 This header should also include the things in remote-sim.h.
45 One could move this to remote-sim.h but this function isn't needed
47 void sim_set_simcache_size PARAMS ((int));
49 #define X(op, size) op*4+size
51 #define SP (h8300hmode ? SL:SW)
64 #define h8_opcodes ops
66 #include "opcode/h8300.h"
70 #define LOW_BYTE(x) ((x) & 0xff)
71 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
72 #define P(X,Y) ((X<<8) | Y)
74 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
77 c = (cpu.ccr >> 0) & 1;\
78 v = (cpu.ccr >> 1) & 1;\
79 nz = !((cpu.ccr >> 2) & 1);\
80 n = (cpu.ccr >> 3) & 1;
82 #ifdef __CHAR_IS_SIGNED__
83 #define SEXTCHAR(x) ((char)(x))
87 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
90 #define UEXTCHAR(x) ((x) & 0xff)
91 #define UEXTSHORT(x) ((x) & 0xffff)
92 #define SEXTSHORT(x) ((short)(x))
94 static cpu_state_type cpu;
99 static int memory_size;
130 return h8300hmode ? SL : SW;
143 return X (OP_IMM, SP);
145 return X (OP_REG, SP);
149 return X (OP_MEM, SP);
156 decode (addr, data, dst)
169 struct h8_opcode *q = h8_opcodes;
173 /* Find the exact opcode/arg combo */
177 unsigned int len = 0;
183 op_type looking_for = *nib;
184 int thisnib = data[len >> 1];
186 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
188 if (looking_for < 16 && looking_for >= 0)
190 if (looking_for != thisnib)
195 if ((int) looking_for & (int) B31)
197 if (!(((int) thisnib & 0x8) != 0))
199 looking_for = (op_type) ((int) looking_for & ~(int)
203 if ((int) looking_for & (int) B30)
205 if (!(((int) thisnib & 0x8) == 0))
207 looking_for = (op_type) ((int) looking_for & ~(int) B30);
209 if (looking_for & DBIT)
211 if ((looking_for & 5) != (thisnib & 5))
213 abs = (thisnib & 0x8) ? 2 : 1;
215 else if (looking_for & (REG | IND | INC | DEC))
217 if (looking_for & REG)
220 * Can work out size from the
223 size = bitfrom (looking_for);
225 if (looking_for & SRC)
234 else if (looking_for & L_16)
236 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
238 if (looking_for & (PCREL | DISP))
243 else if (looking_for & ABSJMP)
250 else if (looking_for & MEMIND)
254 else if (looking_for & L_32)
257 abs = (data[i] << 24)
258 | (data[i + 1] << 16)
264 else if (looking_for & L_24)
267 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
270 else if (looking_for & IGNORE)
274 else if (looking_for & DISPREG)
276 rdisp = thisnib & 0x7;
278 else if (looking_for & KBIT)
293 else if (looking_for & L_8)
297 if (looking_for & PCREL)
299 abs = SEXTCHAR (data[len >> 1]);
301 else if (looking_for & ABS8MEM)
304 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
305 abs |= data[len >> 1] & 0xff ;
309 abs = data[len >> 1] & 0xff;
312 else if (looking_for & L_3)
318 else if (looking_for == E)
322 /* Fill in the args */
324 op_type *args = q->args.nib;
330 int rn = (x & DST) ? rd : rs;
344 p->type = X (OP_IMM, size);
347 else if (x & (IMM | KBIT | DBIT))
349 p->type = X (OP_IMM, size);
354 /* Reset the size, some
355 ops (like mul) have two sizes */
358 p->type = X (OP_REG, size);
363 p->type = X (OP_INC, size);
368 p->type = X (OP_DEC, size);
373 p->type = X (OP_DISP, size);
377 else if (x & (ABS | ABSJMP | ABS8MEM))
379 p->type = X (OP_DISP, size);
385 p->type = X (OP_MEM, size);
390 p->type = X (OP_PCREL, size);
391 p->literal = abs + addr + 2;
397 p->type = X (OP_IMM, SP);
402 p->type = X (OP_DISP, size);
404 p->reg = rdisp & 0x7;
411 printf ("Hmmmm %x", x);
418 * But a jmp or a jsr gets
419 * automagically lvalued, since we
420 * branch to their address not their
423 if (q->how == O (O_JSR, SB)
424 || q->how == O (O_JMP, SB))
426 dst->src.type = lvalue (dst->src.type, dst->src.reg);
429 if (dst->dst.type == -1)
432 dst->opcode = q->how;
433 dst->cycles = q->time;
435 /* And a jsr to 0xc4 is turned into a magic trap */
437 if (dst->opcode == O (O_JSR, SB))
439 if (dst->src.literal == 0xc4)
441 dst->opcode = O (O_SYSCALL, SB);
445 dst->next_pc = addr + len / 2;
450 printf ("Dont understand %x \n", looking_for);
462 dst->opcode = O (O_ILL, SB);
471 /* find the next cache entry to use */
473 idx = cpu.cache_top + 1;
475 if (idx >= cpu.csize)
481 /* Throw away its old meaning */
482 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
484 /* set to new address */
485 cpu.cache[idx].oldpc = pc;
487 /* fill in instruction info */
488 decode (pc, cpu.memory + pc, cpu.cache + idx);
490 /* point to new cache entry */
491 cpu.cache_idx[pc] = idx;
495 static unsigned char *breg[18];
496 static unsigned short *wreg[18];
497 static unsigned int *lreg[18];
499 #define GET_B_REG(x) *(breg[x])
500 #define SET_B_REG(x,y) (*(breg[x])) = (y)
501 #define GET_W_REG(x) *(wreg[x])
502 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
504 #define GET_L_REG(x) *(lreg[x])
505 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
507 #define GET_MEMORY_L(x) \
509 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
510 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
511 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
512 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
514 #define GET_MEMORY_W(x) \
516 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
517 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
520 #define GET_MEMORY_B(x) \
521 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
523 #define SET_MEMORY_L(x,y) \
524 { register unsigned char *_p; register int __y = y; \
525 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
526 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
527 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
529 #define SET_MEMORY_W(x,y) \
530 { register unsigned char *_p; register int __y = y; \
531 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
532 _p[0] = (__y)>>8; _p[1] =(__y);}
534 #define SET_MEMORY_B(x,y) \
535 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
542 int abs = arg->literal;
549 return GET_B_REG (rn);
551 return GET_W_REG (rn);
553 return GET_L_REG (rn);
564 r = GET_MEMORY_B (t);
573 r = GET_MEMORY_W (t);
581 r = GET_MEMORY_L (t);
588 case X (OP_DISP, SB):
589 t = GET_L_REG (rn) + abs;
591 return GET_MEMORY_B (t);
593 case X (OP_DISP, SW):
594 t = GET_L_REG (rn) + abs;
596 return GET_MEMORY_W (t);
598 case X (OP_DISP, SL):
599 t = GET_L_REG (rn) + abs;
601 return GET_MEMORY_L (t);
604 t = GET_MEMORY_L (abs);
609 t = GET_MEMORY_W (abs);
627 int abs = arg->literal;
643 t = GET_L_REG (rn) - 1;
650 t = (GET_L_REG (rn) - 2) & cpu.mask;
656 t = (GET_L_REG (rn) - 4) & cpu.mask;
661 case X (OP_DISP, SB):
662 t = GET_L_REG (rn) + abs;
667 case X (OP_DISP, SW):
668 t = GET_L_REG (rn) + abs;
673 case X (OP_DISP, SL):
674 t = GET_L_REG (rn) + abs;
711 memory_size = H8300H_MSIZE;
713 memory_size = H8300_MSIZE;
714 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
715 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
716 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
718 /* `msize' must be a power of two */
719 if ((memory_size & (memory_size - 1)) != 0)
721 cpu.mask = memory_size - 1;
723 for (i = 0; i < 9; i++)
728 for (i = 0; i < 8; i++)
730 unsigned char *p = (unsigned char *) (cpu.regs + i);
731 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
732 unsigned short *q = (unsigned short *) (cpu.regs + i);
733 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
734 cpu.regs[i] = 0x00112233;
760 lreg[i] = &cpu.regs[i];
763 lreg[8] = &cpu.regs[8];
765 /* initialize the seg registers */
767 sim_set_simcache_size (CSIZE);
772 control_c (sig, code, scp, addr)
778 cpu.state = SIM_STATE_STOPPED;
779 cpu.exception = SIGINT;
788 mop (code, bsize, sign)
801 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
802 SEXTSHORT (GET_W_REG (code->dst.reg));
804 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
805 SEXTSHORT (GET_W_REG (code->src.reg));
809 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
810 UEXTSHORT (GET_W_REG (code->dst.reg));
812 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
813 UEXTSHORT (GET_W_REG (code->src.reg));
816 result = multiplier * multiplicand;
820 n = result & (bsize ? 0x8000 : 0x80000000);
821 nz = result & (bsize ? 0xffff : 0xffffffff);
825 SET_W_REG (code->dst.reg, result);
829 SET_L_REG (code->dst.reg, result);
831 /* return ((n==1) << 1) | (nz==1); */
835 #define ONOT(name, how) \
840 rd = GET_B_REG (code->src.reg); \
848 rd = GET_W_REG (code->src.reg); \
855 int hm = 0x80000000; \
856 rd = GET_L_REG (code->src.reg); \
861 #define OSHIFTS(name, how1, how2) \
866 rd = GET_B_REG (code->src.reg); \
867 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
881 rd = GET_W_REG (code->src.reg); \
882 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
895 int hm = 0x80000000; \
896 rd = GET_L_REG (code->src.reg); \
897 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
908 #define OBITOP(name,f, s, op) \
913 if (f) ea = fetch (&code->dst); \
914 m=1<< fetch(&code->src); \
916 if(s) store (&code->dst,ea); goto next; \
923 cpu.state = SIM_STATE_STOPPED;
924 cpu.exception = SIGINT;
929 sim_resume (sd, step, siggnal)
935 int tick_start = get_now ();
948 prev = signal (SIGINT, control_c);
952 cpu.state = SIM_STATE_STOPPED;
953 cpu.exception = SIGTRAP;
957 cpu.state = SIM_STATE_RUNNING;
963 /* The PC should never be odd. */
977 cidx = cpu.cache_idx[pc];
978 code = cpu.cache + cidx;
981 #define ALUOP(STORE, NAME, HOW) \
982 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
983 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
984 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
987 #define LOGOP(NAME, HOW) \
988 case O(NAME,SB): HOW; goto log8;\
989 case O(NAME, SW): HOW; goto log16;\
990 case O(NAME,SL): HOW; goto log32;
997 printf ("%x %d %s\n", pc, code->opcode,
998 code->op ? code->op->name : "**");
1000 cpu.stats[code->opcode]++;
1004 cycles += code->cycles;
1006 switch (code->opcode)
1010 * This opcode is a fake for when we get to an
1011 * instruction which hasnt been compiled
1018 case O (O_SUBX, SB):
1019 rd = fetch (&code->dst);
1020 ea = fetch (&code->src);
1025 case O (O_ADDX, SB):
1026 rd = fetch (&code->dst);
1027 ea = fetch (&code->src);
1032 #define EA ea = fetch(&code->src);
1033 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1035 ALUOP (1, O_SUB, RD_EA;
1038 ALUOP (1, O_NEG, EA;
1044 rd = GET_B_REG (code->dst.reg);
1045 ea = fetch (&code->src);
1049 rd = GET_W_REG (code->dst.reg);
1050 ea = fetch (&code->src);
1054 rd = GET_L_REG (code->dst.reg);
1055 ea = fetch (&code->src);
1060 LOGOP (O_AND, RD_EA;
1066 LOGOP (O_XOR, RD_EA;
1070 case O (O_MOV_TO_MEM, SB):
1071 res = GET_B_REG (code->src.reg);
1073 case O (O_MOV_TO_MEM, SW):
1074 res = GET_W_REG (code->src.reg);
1076 case O (O_MOV_TO_MEM, SL):
1077 res = GET_L_REG (code->src.reg);
1081 case O (O_MOV_TO_REG, SB):
1082 res = fetch (&code->src);
1083 SET_B_REG (code->dst.reg, res);
1084 goto just_flags_log8;
1085 case O (O_MOV_TO_REG, SW):
1086 res = fetch (&code->src);
1087 SET_W_REG (code->dst.reg, res);
1088 goto just_flags_log16;
1089 case O (O_MOV_TO_REG, SL):
1090 res = fetch (&code->src);
1091 SET_L_REG (code->dst.reg, res);
1092 goto just_flags_log32;
1095 case O (O_ADDS, SL):
1096 SET_L_REG (code->dst.reg,
1097 GET_L_REG (code->dst.reg)
1098 + code->src.literal);
1102 case O (O_SUBS, SL):
1103 SET_L_REG (code->dst.reg,
1104 GET_L_REG (code->dst.reg)
1105 - code->src.literal);
1109 rd = fetch (&code->dst);
1110 ea = fetch (&code->src);
1113 goto just_flags_alu8;
1116 rd = fetch (&code->dst);
1117 ea = fetch (&code->src);
1120 goto just_flags_alu16;
1123 rd = fetch (&code->dst);
1124 ea = fetch (&code->src);
1127 goto just_flags_alu32;
1131 rd = GET_B_REG (code->src.reg);
1134 SET_B_REG (code->src.reg, res);
1135 goto just_flags_inc8;
1138 rd = GET_W_REG (code->dst.reg);
1139 ea = -code->src.literal;
1141 SET_W_REG (code->dst.reg, res);
1142 goto just_flags_inc16;
1145 rd = GET_L_REG (code->dst.reg);
1146 ea = -code->src.literal;
1148 SET_L_REG (code->dst.reg, res);
1149 goto just_flags_inc32;
1153 rd = GET_B_REG (code->src.reg);
1156 SET_B_REG (code->src.reg, res);
1157 goto just_flags_inc8;
1160 rd = GET_W_REG (code->dst.reg);
1161 ea = code->src.literal;
1163 SET_W_REG (code->dst.reg, res);
1164 goto just_flags_inc16;
1167 rd = GET_L_REG (code->dst.reg);
1168 ea = code->src.literal;
1170 SET_L_REG (code->dst.reg, res);
1171 goto just_flags_inc32;
1174 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1176 case O (O_ANDC, SB):
1178 ea = code->src.literal;
1184 ea = code->src.literal;
1188 case O (O_XORC, SB):
1190 ea = code->src.literal;
1231 if (((Z || (N ^ V)) == 0))
1237 if (((Z || (N ^ V)) == 1))
1271 case O (O_SYSCALL, SB):
1272 printf ("%c", cpu.regs[2]);
1275 ONOT (O_NOT, rd = ~rd; v = 0;);
1277 c = rd & hm; v = 0; rd <<= 1,
1278 c = rd & (hm >> 1); v = 0; rd <<= 2);
1280 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1281 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1283 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1284 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1286 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1287 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1289 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1290 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1292 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1293 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1295 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1296 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1298 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1299 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1303 pc = fetch (&code->src);
1311 pc = fetch (&code->src);
1318 SET_MEMORY_L (tmp, code->next_pc);
1323 SET_MEMORY_W (tmp, code->next_pc);
1330 pc = code->src.literal;
1341 pc = GET_MEMORY_L (tmp);
1346 pc = GET_MEMORY_W (tmp);
1355 cpu.state = SIM_STATE_STOPPED;
1356 cpu.exception = SIGILL;
1358 case O (O_SLEEP, SN):
1359 /* The format of r0 is defined by devo/include/wait.h. */
1360 #if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */
1361 if (WIFEXITED (cpu.regs[0]))
1363 cpu.state = SIM_STATE_EXITED;
1364 cpu.exception = WEXITSTATUS (cpu.regs[0]);
1366 else if (WIFSTOPPED (cpu.regs[0]))
1368 cpu.state = SIM_STATE_STOPPED;
1369 cpu.exception = WSTOPSIG (cpu.regs[0]);
1373 cpu.state = SIM_STATE_SIGNALLED;
1374 cpu.exception = WTERMSIG (cpu.regs[0]);
1377 /* FIXME: Doesn't this break for breakpoints when r0
1378 contains just the right (er, wrong) value? */
1379 cpu.state = SIM_STATE_STOPPED;
1380 if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0]))
1381 cpu.exception = SIGILL;
1383 cpu.exception = SIGTRAP;
1387 cpu.state = SIM_STATE_STOPPED;
1388 cpu.exception = SIGTRAP;
1391 OBITOP (O_BNOT, 1, 1, ea ^= m);
1392 OBITOP (O_BTST, 1, 0, nz = ea & m);
1393 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1394 OBITOP (O_BSET, 1, 1, ea |= m);
1395 OBITOP (O_BLD, 1, 0, c = ea & m);
1396 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1397 OBITOP (O_BST, 1, 1, ea &= ~m;
1399 OBITOP (O_BIST, 1, 1, ea &= ~m;
1401 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1402 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1403 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1404 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1405 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1406 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1409 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1411 case O (O_MULS, SB):
1414 case O (O_MULS, SW):
1417 case O (O_MULU, SB):
1420 case O (O_MULU, SW):
1425 case O (O_DIVU, SB):
1427 rd = GET_W_REG (code->dst.reg);
1428 ea = GET_B_REG (code->src.reg);
1431 tmp = (unsigned)rd % ea;
1432 rd = (unsigned)rd / ea;
1434 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1440 case O (O_DIVU, SW):
1442 rd = GET_L_REG (code->dst.reg);
1443 ea = GET_W_REG (code->src.reg);
1448 tmp = (unsigned)rd % ea;
1449 rd = (unsigned)rd / ea;
1451 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1455 case O (O_DIVS, SB):
1458 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1459 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1462 tmp = (int) rd % (int) ea;
1463 rd = (int) rd / (int) ea;
1469 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1472 case O (O_DIVS, SW):
1474 rd = GET_L_REG (code->dst.reg);
1475 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1478 tmp = (int) rd % (int) ea;
1479 rd = (int) rd / (int) ea;
1480 n = rd & 0x80000000;
1485 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1488 case O (O_EXTS, SW):
1489 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1490 ea = rd & 0x80 ? -256 : 0;
1493 case O (O_EXTS, SL):
1494 rd = GET_W_REG (code->src.reg) & 0xffff;
1495 ea = rd & 0x8000 ? -65536 : 0;
1498 case O (O_EXTU, SW):
1499 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1503 case O (O_EXTU, SL):
1504 rd = GET_W_REG (code->src.reg) & 0xffff;
1514 int nregs, firstreg, i;
1516 nregs = GET_MEMORY_B (pc + 1);
1519 firstreg = GET_MEMORY_B (pc + 3);
1521 for (i = firstreg; i <= firstreg + nregs; i++)
1524 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1531 int nregs, firstreg, i;
1533 nregs = GET_MEMORY_B (pc + 1);
1536 firstreg = GET_MEMORY_B (pc + 3);
1538 for (i = firstreg; i >= firstreg - nregs; i--)
1540 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1547 cpu.state = SIM_STATE_STOPPED;
1548 cpu.exception = SIGILL;
1560 /* When a branch works */
1561 pc = code->src.literal;
1564 /* Set the cond codes from res */
1567 /* Set the flags after an 8 bit inc/dec operation */
1571 v = (rd & 0x7f) == 0x7f;
1575 /* Set the flags after an 16 bit inc/dec operation */
1579 v = (rd & 0x7fff) == 0x7fff;
1583 /* Set the flags after an 32 bit inc/dec operation */
1585 n = res & 0x80000000;
1586 nz = res & 0xffffffff;
1587 v = (rd & 0x7fffffff) == 0x7fffffff;
1592 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1595 SET_B_REG (code->src.reg, rd);
1599 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1602 SET_W_REG (code->src.reg, rd);
1606 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1607 n = (rd & 0x80000000);
1608 nz = rd & 0xffffffff;
1609 SET_L_REG (code->src.reg, rd);
1613 store (&code->dst, res);
1615 /* flags after a 32bit logical operation */
1616 n = res & 0x80000000;
1617 nz = res & 0xffffffff;
1622 store (&code->dst, res);
1624 /* flags after a 16bit logical operation */
1632 store (&code->dst, res);
1640 SET_B_REG (code->dst.reg, res);
1645 switch (code->opcode / 4)
1648 v = ((rd & 0x80) == (ea & 0x80)
1649 && (rd & 0x80) != (res & 0x80));
1653 v = ((rd & 0x80) != (-ea & 0x80)
1654 && (rd & 0x80) != (res & 0x80));
1663 SET_W_REG (code->dst.reg, res);
1667 c = (res & 0x10000);
1668 switch (code->opcode / 4)
1671 v = ((rd & 0x8000) == (ea & 0x8000)
1672 && (rd & 0x8000) != (res & 0x8000));
1676 v = ((rd & 0x8000) != (-ea & 0x8000)
1677 && (rd & 0x8000) != (res & 0x8000));
1686 SET_L_REG (code->dst.reg, res);
1688 n = res & 0x80000000;
1689 nz = res & 0xffffffff;
1690 switch (code->opcode / 4)
1693 v = ((rd & 0x80000000) == (ea & 0x80000000)
1694 && (rd & 0x80000000) != (res & 0x80000000));
1695 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1699 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1700 && (rd & 0x80000000) != (res & 0x80000000));
1701 c = (unsigned) rd < (unsigned) -ea;
1704 v = (rd == 0x80000000);
1715 /* if (cpu.regs[8] ) abort(); */
1717 if (poll_count++ > 100)
1720 if ((*sim_callback->poll_quit) != NULL
1721 && (*sim_callback->poll_quit) (sim_callback))
1726 while (cpu.state == SIM_STATE_RUNNING);
1727 cpu.ticks += get_now () - tick_start;
1728 cpu.cycles += cycles;
1734 signal (SIGINT, prev);
1741 /* FIXME: unfinished */
1746 sim_write (sd, addr, buffer, size)
1749 unsigned char *buffer;
1757 for (i = 0; i < size; i++)
1759 if (addr < memory_size)
1761 cpu.memory[addr + i] = buffer[i];
1762 cpu.cache_idx[addr + i] = 0;
1765 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1771 sim_read (sd, addr, buffer, size)
1774 unsigned char *buffer;
1780 if (addr < memory_size)
1781 memcpy (buffer, cpu.memory + addr, size);
1783 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1797 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1798 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1801 #define CCR_REGNUM 8 /* Contains processor status */
1802 #define PC_REGNUM 9 /* Contains program counter */
1804 #define CYCLE_REGNUM 10
1805 #define INST_REGNUM 11
1806 #define TICK_REGNUM 12
1810 sim_store_register (sd, rn, value)
1813 unsigned char *value;
1818 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1819 shortval = (value[0] << 8) | (value[1]);
1820 intval = h8300hmode ? longval : shortval;
1838 cpu.regs[rn] = intval;
1844 cpu.cycles = longval;
1848 cpu.insts = longval;
1852 cpu.ticks = longval;
1858 sim_fetch_register (sd, rn, buf)
1901 if (h8300hmode || longreg)
1916 sim_stop_reason (sd, reason, sigrc)
1918 enum sim_stop *reason;
1921 #if 0 /* FIXME: This should work but we can't use it.
1922 grep for SLEEP above. */
1925 case SIM_STATE_EXITED : *reason = sim_exited; break;
1926 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1927 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1931 *reason = sim_stopped;
1933 *sigrc = cpu.exception;
1936 /* FIXME: Rename to sim_set_mem_size. */
1942 /* Memory size is fixed. */
1946 sim_set_simcache_size (n)
1952 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1953 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1959 sim_info (sd, verbose)
1963 double timetaken = (double) cpu.ticks / (double) now_persec ();
1964 double virttime = cpu.cycles / 10.0e6;
1966 (*sim_callback->printf_filtered) (sim_callback,
1967 "\n\n#instructions executed %10d\n",
1969 (*sim_callback->printf_filtered) (sim_callback,
1970 "#cycles (v approximate) %10d\n",
1972 (*sim_callback->printf_filtered) (sim_callback,
1973 "#real time taken %10.4f\n",
1975 (*sim_callback->printf_filtered) (sim_callback,
1976 "#virtual time taked %10.4f\n",
1978 if (timetaken != 0.0)
1979 (*sim_callback->printf_filtered) (sim_callback,
1980 "#simulation ratio %10.4f\n",
1981 virttime / timetaken);
1982 (*sim_callback->printf_filtered) (sim_callback,
1985 (*sim_callback->printf_filtered) (sim_callback,
1986 "#cache size %10d\n",
1990 /* This to be conditional on `what' (aka `verbose'),
1991 however it was never passed as non-zero. */
1995 for (i = 0; i < O_LAST; i++)
1998 (*sim_callback->printf_filtered) (sim_callback,
1999 "%d: %d\n", i, cpu.stats[i]);
2005 /* Indicate whether the cpu is an h8/300 or h8/300h.
2006 FLAG is non-zero for the h8/300h. */
2023 sim_open (kind, ptr, abfd, argv)
2025 struct host_callback_struct *ptr;
2032 /* fudge our descriptor */
2033 return (SIM_DESC) 1;
2037 sim_close (sd, quitting)
2044 /* Called by gdb to load a program into memory. */
2047 sim_load (sd, prog, abfd, from_tty)
2055 /* See if the file is for the h8/300 or h8/300h. */
2056 /* ??? This may not be the most efficient way. The z8k simulator
2057 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2061 prog_bfd = bfd_openr (prog, "coff-h8300");
2062 if (prog_bfd != NULL)
2064 /* Set the cpu type. We ignore failure from bfd_check_format
2065 and bfd_openr as sim_load_file checks too. */
2066 if (bfd_check_format (prog_bfd, bfd_object))
2068 unsigned long mach = bfd_get_mach (prog_bfd);
2069 set_h8300h (mach == bfd_mach_h8300h
2070 || mach == bfd_mach_h8300s);
2074 /* If we're using gdb attached to the simulator, then we have to
2075 reallocate memory for the simulator.
2077 When gdb first starts, it calls fetch_registers (among other
2078 functions), which in turn calls init_pointers, which allocates
2081 The problem is when we do that, we don't know whether we're
2082 debugging an h8/300 or h8/300h program.
2084 This is the first point at which we can make that determination,
2085 so we just reallocate memory now; this will also allow us to handle
2086 switching between h8/300 and h8/300h programs without exiting
2089 memory_size = H8300H_MSIZE;
2091 memory_size = H8300_MSIZE;
2096 free (cpu.cache_idx);
2098 free (cpu.eightbit);
2100 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2101 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2102 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2104 /* `msize' must be a power of two */
2105 if ((memory_size & (memory_size - 1)) != 0)
2107 cpu.mask = memory_size - 1;
2109 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2110 sim_kind == SIM_OPEN_DEBUG)
2113 /* Close the bfd if we opened it. */
2114 if (abfd == NULL && prog_bfd != NULL)
2115 bfd_close (prog_bfd);
2119 cpu.pc = bfd_get_start_address (prog_bfd);
2120 /* Close the bfd if we opened it. */
2121 if (abfd == NULL && prog_bfd != NULL)
2122 bfd_close (prog_bfd);
2127 sim_create_inferior (sd, argv, env)
2136 sim_do_command (sd, cmd)
2140 (*sim_callback->printf_filtered) (sim_callback,
2141 "This simulator does not accept any commands.\n");
2145 sim_set_callbacks (ptr)
2146 struct host_callback_struct *ptr;