2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
37 #include "remote-sim.h"
45 host_callback *sim_callback;
47 static SIM_OPEN_KIND sim_kind;
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
54 void sim_set_simcache_size PARAMS ((int));
56 #define X(op, size) op*4+size
58 #define SP (h8300hmode ? SL:SW)
71 #define h8_opcodes ops
73 #include "opcode/h8300.h"
77 #define LOW_BYTE(x) ((x) & 0xff)
78 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
79 #define P(X,Y) ((X<<8) | Y)
81 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
84 c = (cpu.ccr >> 0) & 1;\
85 v = (cpu.ccr >> 1) & 1;\
86 nz = !((cpu.ccr >> 2) & 1);\
87 n = (cpu.ccr >> 3) & 1;
89 #ifdef __CHAR_IS_SIGNED__
90 #define SEXTCHAR(x) ((char)(x))
94 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
97 #define UEXTCHAR(x) ((x) & 0xff)
98 #define UEXTSHORT(x) ((x) & 0xffff)
99 #define SEXTSHORT(x) ((short)(x))
101 static cpu_state_type cpu;
106 static int memory_size;
137 return h8300hmode ? SL : SW;
150 return X (OP_IMM, SP);
152 return X (OP_REG, SP);
156 return X (OP_MEM, SP);
163 decode (addr, data, dst)
176 struct h8_opcode *q = h8_opcodes;
180 /* Find the exact opcode/arg combo */
184 unsigned int len = 0;
190 op_type looking_for = *nib;
191 int thisnib = data[len >> 1];
193 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
195 if (looking_for < 16 && looking_for >= 0)
197 if (looking_for != thisnib)
202 if ((int) looking_for & (int) B31)
204 if (!(((int) thisnib & 0x8) != 0))
206 looking_for = (op_type) ((int) looking_for & ~(int)
210 if ((int) looking_for & (int) B30)
212 if (!(((int) thisnib & 0x8) == 0))
214 looking_for = (op_type) ((int) looking_for & ~(int) B30);
216 if (looking_for & DBIT)
218 if ((looking_for & 5) != (thisnib & 5))
220 abs = (thisnib & 0x8) ? 2 : 1;
222 else if (looking_for & (REG | IND | INC | DEC))
224 if (looking_for & REG)
227 * Can work out size from the
230 size = bitfrom (looking_for);
232 if (looking_for & SRC)
241 else if (looking_for & L_16)
243 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
245 if (looking_for & (PCREL | DISP))
250 else if (looking_for & ABSJMP)
257 else if (looking_for & MEMIND)
261 else if (looking_for & L_32)
264 abs = (data[i] << 24)
265 | (data[i + 1] << 16)
271 else if (looking_for & L_24)
274 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
277 else if (looking_for & IGNORE)
281 else if (looking_for & DISPREG)
283 rdisp = thisnib & 0x7;
285 else if (looking_for & KBIT)
300 else if (looking_for & L_8)
304 if (looking_for & PCREL)
306 abs = SEXTCHAR (data[len >> 1]);
308 else if (looking_for & ABS8MEM)
311 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
312 abs |= data[len >> 1] & 0xff ;
316 abs = data[len >> 1] & 0xff;
319 else if (looking_for & L_3)
325 else if (looking_for == E)
329 /* Fill in the args */
331 op_type *args = q->args.nib;
337 int rn = (x & DST) ? rd : rs;
351 p->type = X (OP_IMM, size);
354 else if (x & (IMM | KBIT | DBIT))
356 p->type = X (OP_IMM, size);
361 /* Reset the size, some
362 ops (like mul) have two sizes */
365 p->type = X (OP_REG, size);
370 p->type = X (OP_INC, size);
375 p->type = X (OP_DEC, size);
380 p->type = X (OP_DISP, size);
384 else if (x & (ABS | ABSJMP | ABS8MEM))
386 p->type = X (OP_DISP, size);
392 p->type = X (OP_MEM, size);
397 p->type = X (OP_PCREL, size);
398 p->literal = abs + addr + 2;
404 p->type = X (OP_IMM, SP);
409 p->type = X (OP_DISP, size);
411 p->reg = rdisp & 0x7;
418 printf ("Hmmmm %x", x);
425 * But a jmp or a jsr gets
426 * automagically lvalued, since we
427 * branch to their address not their
430 if (q->how == O (O_JSR, SB)
431 || q->how == O (O_JMP, SB))
433 dst->src.type = lvalue (dst->src.type, dst->src.reg);
436 if (dst->dst.type == -1)
439 dst->opcode = q->how;
440 dst->cycles = q->time;
442 /* And a jsr to 0xc4 is turned into a magic trap */
444 if (dst->opcode == O (O_JSR, SB))
446 if (dst->src.literal == 0xc4)
448 dst->opcode = O (O_SYSCALL, SB);
452 dst->next_pc = addr + len / 2;
457 printf ("Dont understand %x \n", looking_for);
469 dst->opcode = O (O_ILL, SB);
478 /* find the next cache entry to use */
480 idx = cpu.cache_top + 1;
482 if (idx >= cpu.csize)
488 /* Throw away its old meaning */
489 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
491 /* set to new address */
492 cpu.cache[idx].oldpc = pc;
494 /* fill in instruction info */
495 decode (pc, cpu.memory + pc, cpu.cache + idx);
497 /* point to new cache entry */
498 cpu.cache_idx[pc] = idx;
502 static unsigned char *breg[18];
503 static unsigned short *wreg[18];
504 static unsigned int *lreg[18];
506 #define GET_B_REG(x) *(breg[x])
507 #define SET_B_REG(x,y) (*(breg[x])) = (y)
508 #define GET_W_REG(x) *(wreg[x])
509 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
511 #define GET_L_REG(x) *(lreg[x])
512 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
514 #define GET_MEMORY_L(x) \
516 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
517 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
518 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
519 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
521 #define GET_MEMORY_W(x) \
523 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
524 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
527 #define GET_MEMORY_B(x) \
528 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
530 #define SET_MEMORY_L(x,y) \
531 { register unsigned char *_p; register int __y = y; \
532 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
533 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
534 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
536 #define SET_MEMORY_W(x,y) \
537 { register unsigned char *_p; register int __y = y; \
538 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
539 _p[0] = (__y)>>8; _p[1] =(__y);}
541 #define SET_MEMORY_B(x,y) \
542 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
549 int abs = arg->literal;
556 return GET_B_REG (rn);
558 return GET_W_REG (rn);
560 return GET_L_REG (rn);
571 r = GET_MEMORY_B (t);
580 r = GET_MEMORY_W (t);
588 r = GET_MEMORY_L (t);
595 case X (OP_DISP, SB):
596 t = GET_L_REG (rn) + abs;
598 return GET_MEMORY_B (t);
600 case X (OP_DISP, SW):
601 t = GET_L_REG (rn) + abs;
603 return GET_MEMORY_W (t);
605 case X (OP_DISP, SL):
606 t = GET_L_REG (rn) + abs;
608 return GET_MEMORY_L (t);
611 t = GET_MEMORY_L (abs);
616 t = GET_MEMORY_W (abs);
634 int abs = arg->literal;
650 t = GET_L_REG (rn) - 1;
657 t = (GET_L_REG (rn) - 2) & cpu.mask;
663 t = (GET_L_REG (rn) - 4) & cpu.mask;
668 case X (OP_DISP, SB):
669 t = GET_L_REG (rn) + abs;
674 case X (OP_DISP, SW):
675 t = GET_L_REG (rn) + abs;
680 case X (OP_DISP, SL):
681 t = GET_L_REG (rn) + abs;
718 memory_size = H8300H_MSIZE;
720 memory_size = H8300_MSIZE;
721 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
722 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
723 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
725 /* `msize' must be a power of two */
726 if ((memory_size & (memory_size - 1)) != 0)
728 cpu.mask = memory_size - 1;
730 for (i = 0; i < 9; i++)
735 for (i = 0; i < 8; i++)
737 unsigned char *p = (unsigned char *) (cpu.regs + i);
738 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
739 unsigned short *q = (unsigned short *) (cpu.regs + i);
740 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
741 cpu.regs[i] = 0x00112233;
767 lreg[i] = &cpu.regs[i];
770 lreg[8] = &cpu.regs[8];
772 /* initialize the seg registers */
774 sim_set_simcache_size (CSIZE);
779 control_c (sig, code, scp, addr)
785 cpu.state = SIM_STATE_STOPPED;
786 cpu.exception = SIGINT;
795 mop (code, bsize, sign)
808 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
809 SEXTSHORT (GET_W_REG (code->dst.reg));
811 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
812 SEXTSHORT (GET_W_REG (code->src.reg));
816 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
817 UEXTSHORT (GET_W_REG (code->dst.reg));
819 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
820 UEXTSHORT (GET_W_REG (code->src.reg));
823 result = multiplier * multiplicand;
827 n = result & (bsize ? 0x8000 : 0x80000000);
828 nz = result & (bsize ? 0xffff : 0xffffffff);
832 SET_W_REG (code->dst.reg, result);
836 SET_L_REG (code->dst.reg, result);
838 /* return ((n==1) << 1) | (nz==1); */
842 #define ONOT(name, how) \
847 rd = GET_B_REG (code->src.reg); \
855 rd = GET_W_REG (code->src.reg); \
862 int hm = 0x80000000; \
863 rd = GET_L_REG (code->src.reg); \
868 #define OSHIFTS(name, how1, how2) \
873 rd = GET_B_REG (code->src.reg); \
874 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
888 rd = GET_W_REG (code->src.reg); \
889 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
902 int hm = 0x80000000; \
903 rd = GET_L_REG (code->src.reg); \
904 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
915 #define OBITOP(name,f, s, op) \
920 if (f) ea = fetch (&code->dst); \
921 m=1<< fetch(&code->src); \
923 if(s) store (&code->dst,ea); goto next; \
930 cpu.state = SIM_STATE_STOPPED;
931 cpu.exception = SIGINT;
936 sim_resume (sd, step, siggnal)
942 int tick_start = get_now ();
955 prev = signal (SIGINT, control_c);
959 cpu.state = SIM_STATE_STOPPED;
960 cpu.exception = SIGTRAP;
964 cpu.state = SIM_STATE_RUNNING;
970 /* The PC should never be odd. */
984 cidx = cpu.cache_idx[pc];
985 code = cpu.cache + cidx;
988 #define ALUOP(STORE, NAME, HOW) \
989 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
990 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
991 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
994 #define LOGOP(NAME, HOW) \
995 case O(NAME,SB): HOW; goto log8;\
996 case O(NAME, SW): HOW; goto log16;\
997 case O(NAME,SL): HOW; goto log32;
1004 printf ("%x %d %s\n", pc, code->opcode,
1005 code->op ? code->op->name : "**");
1007 cpu.stats[code->opcode]++;
1011 cycles += code->cycles;
1013 switch (code->opcode)
1017 * This opcode is a fake for when we get to an
1018 * instruction which hasnt been compiled
1025 case O (O_SUBX, SB):
1026 rd = fetch (&code->dst);
1027 ea = fetch (&code->src);
1032 case O (O_ADDX, SB):
1033 rd = fetch (&code->dst);
1034 ea = fetch (&code->src);
1039 #define EA ea = fetch(&code->src);
1040 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1042 ALUOP (1, O_SUB, RD_EA;
1045 ALUOP (1, O_NEG, EA;
1051 rd = GET_B_REG (code->dst.reg);
1052 ea = fetch (&code->src);
1056 rd = GET_W_REG (code->dst.reg);
1057 ea = fetch (&code->src);
1061 rd = GET_L_REG (code->dst.reg);
1062 ea = fetch (&code->src);
1067 LOGOP (O_AND, RD_EA;
1073 LOGOP (O_XOR, RD_EA;
1077 case O (O_MOV_TO_MEM, SB):
1078 res = GET_B_REG (code->src.reg);
1080 case O (O_MOV_TO_MEM, SW):
1081 res = GET_W_REG (code->src.reg);
1083 case O (O_MOV_TO_MEM, SL):
1084 res = GET_L_REG (code->src.reg);
1088 case O (O_MOV_TO_REG, SB):
1089 res = fetch (&code->src);
1090 SET_B_REG (code->dst.reg, res);
1091 goto just_flags_log8;
1092 case O (O_MOV_TO_REG, SW):
1093 res = fetch (&code->src);
1094 SET_W_REG (code->dst.reg, res);
1095 goto just_flags_log16;
1096 case O (O_MOV_TO_REG, SL):
1097 res = fetch (&code->src);
1098 SET_L_REG (code->dst.reg, res);
1099 goto just_flags_log32;
1102 case O (O_ADDS, SL):
1103 SET_L_REG (code->dst.reg,
1104 GET_L_REG (code->dst.reg)
1105 + code->src.literal);
1109 case O (O_SUBS, SL):
1110 SET_L_REG (code->dst.reg,
1111 GET_L_REG (code->dst.reg)
1112 - code->src.literal);
1116 rd = fetch (&code->dst);
1117 ea = fetch (&code->src);
1120 goto just_flags_alu8;
1123 rd = fetch (&code->dst);
1124 ea = fetch (&code->src);
1127 goto just_flags_alu16;
1130 rd = fetch (&code->dst);
1131 ea = fetch (&code->src);
1134 goto just_flags_alu32;
1138 rd = GET_B_REG (code->src.reg);
1141 SET_B_REG (code->src.reg, res);
1142 goto just_flags_inc8;
1145 rd = GET_W_REG (code->dst.reg);
1146 ea = -code->src.literal;
1148 SET_W_REG (code->dst.reg, res);
1149 goto just_flags_inc16;
1152 rd = GET_L_REG (code->dst.reg);
1153 ea = -code->src.literal;
1155 SET_L_REG (code->dst.reg, res);
1156 goto just_flags_inc32;
1160 rd = GET_B_REG (code->src.reg);
1163 SET_B_REG (code->src.reg, res);
1164 goto just_flags_inc8;
1167 rd = GET_W_REG (code->dst.reg);
1168 ea = code->src.literal;
1170 SET_W_REG (code->dst.reg, res);
1171 goto just_flags_inc16;
1174 rd = GET_L_REG (code->dst.reg);
1175 ea = code->src.literal;
1177 SET_L_REG (code->dst.reg, res);
1178 goto just_flags_inc32;
1181 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1183 case O (O_ANDC, SB):
1185 ea = code->src.literal;
1191 ea = code->src.literal;
1195 case O (O_XORC, SB):
1197 ea = code->src.literal;
1238 if (((Z || (N ^ V)) == 0))
1244 if (((Z || (N ^ V)) == 1))
1278 case O (O_SYSCALL, SB):
1280 char c = cpu.regs[2];
1281 sim_callback->write_stdout (sim_callback, &c, 1);
1285 ONOT (O_NOT, rd = ~rd; v = 0;);
1287 c = rd & hm; v = 0; rd <<= 1,
1288 c = rd & (hm >> 1); v = 0; rd <<= 2);
1290 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1291 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1293 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1294 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1296 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1297 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1299 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1300 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1302 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1303 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1305 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1306 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1308 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1309 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1313 pc = fetch (&code->src);
1321 pc = fetch (&code->src);
1328 SET_MEMORY_L (tmp, code->next_pc);
1333 SET_MEMORY_W (tmp, code->next_pc);
1340 pc = code->src.literal;
1351 pc = GET_MEMORY_L (tmp);
1356 pc = GET_MEMORY_W (tmp);
1365 cpu.state = SIM_STATE_STOPPED;
1366 cpu.exception = SIGILL;
1368 case O (O_SLEEP, SN):
1369 /* The format of r0 is defined by devo/include/wait.h. */
1370 #if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */
1371 if (WIFEXITED (cpu.regs[0]))
1373 cpu.state = SIM_STATE_EXITED;
1374 cpu.exception = WEXITSTATUS (cpu.regs[0]);
1376 else if (WIFSTOPPED (cpu.regs[0]))
1378 cpu.state = SIM_STATE_STOPPED;
1379 cpu.exception = WSTOPSIG (cpu.regs[0]);
1383 cpu.state = SIM_STATE_SIGNALLED;
1384 cpu.exception = WTERMSIG (cpu.regs[0]);
1387 /* FIXME: Doesn't this break for breakpoints when r0
1388 contains just the right (er, wrong) value? */
1389 cpu.state = SIM_STATE_STOPPED;
1390 if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0]))
1391 cpu.exception = SIGILL;
1393 cpu.exception = SIGTRAP;
1397 cpu.state = SIM_STATE_STOPPED;
1398 cpu.exception = SIGTRAP;
1401 OBITOP (O_BNOT, 1, 1, ea ^= m);
1402 OBITOP (O_BTST, 1, 0, nz = ea & m);
1403 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1404 OBITOP (O_BSET, 1, 1, ea |= m);
1405 OBITOP (O_BLD, 1, 0, c = ea & m);
1406 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1407 OBITOP (O_BST, 1, 1, ea &= ~m;
1409 OBITOP (O_BIST, 1, 1, ea &= ~m;
1411 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1412 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1413 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1414 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1415 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1416 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1419 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1421 case O (O_MULS, SB):
1424 case O (O_MULS, SW):
1427 case O (O_MULU, SB):
1430 case O (O_MULU, SW):
1435 case O (O_DIVU, SB):
1437 rd = GET_W_REG (code->dst.reg);
1438 ea = GET_B_REG (code->src.reg);
1441 tmp = (unsigned)rd % ea;
1442 rd = (unsigned)rd / ea;
1444 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1450 case O (O_DIVU, SW):
1452 rd = GET_L_REG (code->dst.reg);
1453 ea = GET_W_REG (code->src.reg);
1458 tmp = (unsigned)rd % ea;
1459 rd = (unsigned)rd / ea;
1461 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1465 case O (O_DIVS, SB):
1468 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1469 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1472 tmp = (int) rd % (int) ea;
1473 rd = (int) rd / (int) ea;
1479 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1482 case O (O_DIVS, SW):
1484 rd = GET_L_REG (code->dst.reg);
1485 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1488 tmp = (int) rd % (int) ea;
1489 rd = (int) rd / (int) ea;
1490 n = rd & 0x80000000;
1495 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1498 case O (O_EXTS, SW):
1499 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1500 ea = rd & 0x80 ? -256 : 0;
1503 case O (O_EXTS, SL):
1504 rd = GET_W_REG (code->src.reg) & 0xffff;
1505 ea = rd & 0x8000 ? -65536 : 0;
1508 case O (O_EXTU, SW):
1509 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1513 case O (O_EXTU, SL):
1514 rd = GET_W_REG (code->src.reg) & 0xffff;
1524 int nregs, firstreg, i;
1526 nregs = GET_MEMORY_B (pc + 1);
1529 firstreg = GET_MEMORY_B (pc + 3);
1531 for (i = firstreg; i <= firstreg + nregs; i++)
1534 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1541 int nregs, firstreg, i;
1543 nregs = GET_MEMORY_B (pc + 1);
1546 firstreg = GET_MEMORY_B (pc + 3);
1548 for (i = firstreg; i >= firstreg - nregs; i--)
1550 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1557 cpu.state = SIM_STATE_STOPPED;
1558 cpu.exception = SIGILL;
1570 /* When a branch works */
1571 pc = code->src.literal;
1574 /* Set the cond codes from res */
1577 /* Set the flags after an 8 bit inc/dec operation */
1581 v = (rd & 0x7f) == 0x7f;
1585 /* Set the flags after an 16 bit inc/dec operation */
1589 v = (rd & 0x7fff) == 0x7fff;
1593 /* Set the flags after an 32 bit inc/dec operation */
1595 n = res & 0x80000000;
1596 nz = res & 0xffffffff;
1597 v = (rd & 0x7fffffff) == 0x7fffffff;
1602 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1605 SET_B_REG (code->src.reg, rd);
1609 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1612 SET_W_REG (code->src.reg, rd);
1616 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1617 n = (rd & 0x80000000);
1618 nz = rd & 0xffffffff;
1619 SET_L_REG (code->src.reg, rd);
1623 store (&code->dst, res);
1625 /* flags after a 32bit logical operation */
1626 n = res & 0x80000000;
1627 nz = res & 0xffffffff;
1632 store (&code->dst, res);
1634 /* flags after a 16bit logical operation */
1642 store (&code->dst, res);
1650 SET_B_REG (code->dst.reg, res);
1655 switch (code->opcode / 4)
1658 v = ((rd & 0x80) == (ea & 0x80)
1659 && (rd & 0x80) != (res & 0x80));
1663 v = ((rd & 0x80) != (-ea & 0x80)
1664 && (rd & 0x80) != (res & 0x80));
1673 SET_W_REG (code->dst.reg, res);
1677 c = (res & 0x10000);
1678 switch (code->opcode / 4)
1681 v = ((rd & 0x8000) == (ea & 0x8000)
1682 && (rd & 0x8000) != (res & 0x8000));
1686 v = ((rd & 0x8000) != (-ea & 0x8000)
1687 && (rd & 0x8000) != (res & 0x8000));
1696 SET_L_REG (code->dst.reg, res);
1698 n = res & 0x80000000;
1699 nz = res & 0xffffffff;
1700 switch (code->opcode / 4)
1703 v = ((rd & 0x80000000) == (ea & 0x80000000)
1704 && (rd & 0x80000000) != (res & 0x80000000));
1705 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1709 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1710 && (rd & 0x80000000) != (res & 0x80000000));
1711 c = (unsigned) rd < (unsigned) -ea;
1714 v = (rd == 0x80000000);
1725 /* if (cpu.regs[8] ) abort(); */
1727 if (--poll_count < 0)
1730 if ((*sim_callback->poll_quit) != NULL
1731 && (*sim_callback->poll_quit) (sim_callback))
1736 while (cpu.state == SIM_STATE_RUNNING);
1737 cpu.ticks += get_now () - tick_start;
1738 cpu.cycles += cycles;
1744 signal (SIGINT, prev);
1751 /* FIXME: unfinished */
1756 sim_write (sd, addr, buffer, size)
1759 unsigned char *buffer;
1767 for (i = 0; i < size; i++)
1769 if (addr < memory_size)
1771 cpu.memory[addr + i] = buffer[i];
1772 cpu.cache_idx[addr + i] = 0;
1775 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1781 sim_read (sd, addr, buffer, size)
1784 unsigned char *buffer;
1790 if (addr < memory_size)
1791 memcpy (buffer, cpu.memory + addr, size);
1793 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1807 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1808 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1811 #define CCR_REGNUM 8 /* Contains processor status */
1812 #define PC_REGNUM 9 /* Contains program counter */
1814 #define CYCLE_REGNUM 10
1815 #define INST_REGNUM 11
1816 #define TICK_REGNUM 12
1820 sim_store_register (sd, rn, value, length)
1823 unsigned char *value;
1829 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1830 shortval = (value[0] << 8) | (value[1]);
1831 intval = h8300hmode ? longval : shortval;
1849 cpu.regs[rn] = intval;
1855 cpu.cycles = longval;
1859 cpu.insts = longval;
1863 cpu.ticks = longval;
1870 sim_fetch_register (sd, rn, buf, length)
1914 if (h8300hmode || longreg)
1930 sim_stop_reason (sd, reason, sigrc)
1932 enum sim_stop *reason;
1935 #if 0 /* FIXME: This should work but we can't use it.
1936 grep for SLEEP above. */
1939 case SIM_STATE_EXITED : *reason = sim_exited; break;
1940 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1941 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1945 *reason = sim_stopped;
1947 *sigrc = cpu.exception;
1950 /* FIXME: Rename to sim_set_mem_size. */
1956 /* Memory size is fixed. */
1960 sim_set_simcache_size (n)
1966 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1967 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1973 sim_info (sd, verbose)
1977 double timetaken = (double) cpu.ticks / (double) now_persec ();
1978 double virttime = cpu.cycles / 10.0e6;
1980 (*sim_callback->printf_filtered) (sim_callback,
1981 "\n\n#instructions executed %10d\n",
1983 (*sim_callback->printf_filtered) (sim_callback,
1984 "#cycles (v approximate) %10d\n",
1986 (*sim_callback->printf_filtered) (sim_callback,
1987 "#real time taken %10.4f\n",
1989 (*sim_callback->printf_filtered) (sim_callback,
1990 "#virtual time taked %10.4f\n",
1992 if (timetaken != 0.0)
1993 (*sim_callback->printf_filtered) (sim_callback,
1994 "#simulation ratio %10.4f\n",
1995 virttime / timetaken);
1996 (*sim_callback->printf_filtered) (sim_callback,
1999 (*sim_callback->printf_filtered) (sim_callback,
2000 "#cache size %10d\n",
2004 /* This to be conditional on `what' (aka `verbose'),
2005 however it was never passed as non-zero. */
2009 for (i = 0; i < O_LAST; i++)
2012 (*sim_callback->printf_filtered) (sim_callback,
2013 "%d: %d\n", i, cpu.stats[i]);
2019 /* Indicate whether the cpu is an h8/300 or h8/300h.
2020 FLAG is non-zero for the h8/300h. */
2026 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2027 This function being replaced by a sim_open:ARGV configuration
2033 sim_open (kind, ptr, abfd, argv)
2035 struct host_callback_struct *ptr;
2039 /* FIXME: Much of the code in sim_load can be moved here */
2044 /* fudge our descriptor */
2045 return (SIM_DESC) 1;
2049 sim_close (sd, quitting)
2056 /* Called by gdb to load a program into memory. */
2059 sim_load (sd, prog, abfd, from_tty)
2067 /* FIXME: The code below that sets a specific variant of the h8/300
2068 being simulated should be moved to sim_open(). */
2070 /* See if the file is for the h8/300 or h8/300h. */
2071 /* ??? This may not be the most efficient way. The z8k simulator
2072 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2076 prog_bfd = bfd_openr (prog, "coff-h8300");
2077 if (prog_bfd != NULL)
2079 /* Set the cpu type. We ignore failure from bfd_check_format
2080 and bfd_openr as sim_load_file checks too. */
2081 if (bfd_check_format (prog_bfd, bfd_object))
2083 unsigned long mach = bfd_get_mach (prog_bfd);
2084 set_h8300h (mach == bfd_mach_h8300h
2085 || mach == bfd_mach_h8300s);
2089 /* If we're using gdb attached to the simulator, then we have to
2090 reallocate memory for the simulator.
2092 When gdb first starts, it calls fetch_registers (among other
2093 functions), which in turn calls init_pointers, which allocates
2096 The problem is when we do that, we don't know whether we're
2097 debugging an h8/300 or h8/300h program.
2099 This is the first point at which we can make that determination,
2100 so we just reallocate memory now; this will also allow us to handle
2101 switching between h8/300 and h8/300h programs without exiting
2104 memory_size = H8300H_MSIZE;
2106 memory_size = H8300_MSIZE;
2111 free (cpu.cache_idx);
2113 free (cpu.eightbit);
2115 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2116 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2117 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2119 /* `msize' must be a power of two */
2120 if ((memory_size & (memory_size - 1)) != 0)
2122 cpu.mask = memory_size - 1;
2124 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2125 sim_kind == SIM_OPEN_DEBUG,
2129 /* Close the bfd if we opened it. */
2130 if (abfd == NULL && prog_bfd != NULL)
2131 bfd_close (prog_bfd);
2135 /* Close the bfd if we opened it. */
2136 if (abfd == NULL && prog_bfd != NULL)
2137 bfd_close (prog_bfd);
2142 sim_create_inferior (sd, abfd, argv, env)
2149 cpu.pc = bfd_get_start_address (abfd);
2156 sim_do_command (sd, cmd)
2160 (*sim_callback->printf_filtered) (sim_callback,
2161 "This simulator does not accept any commands.\n");
2165 sim_set_callbacks (ptr)
2166 struct host_callback_struct *ptr;